CircuitSimulation/sample.sch at master · manojkiraneda/CircuitSimulation · GitHub

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v 20130925 2
C 40000 40000 0 0 0 title-B.sym
C 43900 46700 1 270 0 voltage-3.sym
{
T 44600 46500 5 8 0 0 270 0 1
device=VOLTAGE_SOURCE
T 44400 46400 5 10 1 1 270 0 1
refdes=V1
T 43900 46700 5 10 1 1 0 0 1
value=3
}
C 45300 46900 1 0 0 resistor-1.sym
{
T 45600 47300 5 10 0 0 0 0 1
device=RESISTOR
T 45500 47200 5 10 1 1 0 0 1
refdes=R2
T 45300 46900 5 10 1 1 0 0 1
value=1
}
C 47600 46900 1 0 0 resistor-1.sym
{
T 47900 47300 5 10 0 0 0 0 1
device=RESISTOR
T 47800 47200 5 10 1 1 0 0 1
refdes=R3
T 47600 46900 5 10 1 1 0 0 1
value=1
}
C 49900 45900 1 90 0 resistor-1.sym
{
T 49500 46200 5 10 0 0 90 0 1
device=RESISTOR
T 49600 46100 5 10 1 1 90 0 1
refdes=R1
T 49900 45900 5 10 1 1 0 0 1
value=1
}
N 44100 46700 44100 47000 4
N 44100 47000 45300 47000 4
N 46200 47000 47600 47000 4
N 48500 47000 49800 47000 4
N 49800 47000 49800 46800 4
N 49800 45900 49800 45800 4
N 49800 45800 44100 45800 4
C 46800 44900 1 0 0 ground.sym
N 47000 45200 47000 45800 4
T 50200 40700 9 10 1 0 0 0 1
Sample Circuit using Gschem
T 50000 40400 9 10 1 0 0 0 1
sample.gschem
T 50200 40100 9 10 1 0 0 0 1
1
T 51800 40100 9 10 1 0 0 0 1
1
T 53900 40400 9 10 1 0 0 0 1
0.1
T 53900 40100 9 10 1 0 0 0 1
manojkiran