diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index 2f8981e9432cd..75f17cd745ee6 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -985,6 +985,8 @@ opentitan_test(
         DARJEELING_TEST_ENVS,
         {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival_rom_ext": None,
             "//hw/top_earlgrey:silicon_creator": None,
         },
     ),
@@ -1000,6 +1002,8 @@ opentitan_test(
         DARJEELING_TEST_ENVS,
         {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival_rom_ext": None,
             "//hw/top_earlgrey:silicon_creator": None,
         },
     ),
@@ -1015,6 +1019,8 @@ opentitan_test(
         DARJEELING_TEST_ENVS,
         {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival_rom_ext": None,
             "//hw/top_earlgrey:silicon_creator": None,
         },
     ),
@@ -1030,6 +1036,8 @@ opentitan_test(
         DARJEELING_TEST_ENVS,
         {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+            "//hw/top_earlgrey:fpga_cw340_sival_rom_ext": None,
         },
     ),
     deps = ["clkmgr_off_trans_impl"],
diff --git a/sw/device/tests/clkmgr_off_trans_impl.c b/sw/device/tests/clkmgr_off_trans_impl.c
index 6e224e2f1a7fc..4c468f241cdc9 100644
--- a/sw/device/tests/clkmgr_off_trans_impl.c
+++ b/sw/device/tests/clkmgr_off_trans_impl.c
@@ -114,7 +114,8 @@ static clock_error_info_t info[kTestTransCount];
  * Send CSR access to aes, expecting to timeout.
  */
 OT_NOINLINE void aes_csr_access(void) {
-  CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr));
+  bool status;
+  CHECK_DIF_OK(dif_aes_get_status(&aes, kDifAesStatusIdle, &status));
 }
 
 OT_NOINLINE static void hmac_csr_access(void) {
@@ -204,7 +205,7 @@ bool execute_off_trans_test(test_trans_block_t block) {
         inst = dt_aes_instance_id(kTestAes);
         info[trans].name = "aes";
         info[trans].csr_offset =
-            addr_as_offset(aes.base_addr, AES_ALERT_TEST_REG_OFFSET);
+            addr_as_offset(aes.base_addr, AES_STATUS_REG_OFFSET);
         info[trans].crash_function = aes_csr_access;
         break;