From b3bc686d2d7ab73038c3011283eff8870e14f072 Mon Sep 17 00:00:00 2001 From: James Wainwright Date: Tue, 4 Mar 2025 14:09:16 +0000 Subject: [PATCH] Bump binutils to v2.44 Upstream binutils now supports the fully ratified 1.0.0 bitmanip extensions. The patch has been updated to add only the unratified 0.93 instructions. Version 3.40 of binutils included a fix for generating verilog memory (vmem) files which is useful for OpenTitan. --- .github/workflows/toolchain_build.yml | 2 +- lowrisc-toolchain-gcc-rv32imcb.config | 9 +- .../binutils/git-7c9dd840/001-bitmanip.patch | 458 ------------------ .../binutils/git-815d9a14/001-bitmanip.patch | 339 +++++++++++++ 4 files changed, 344 insertions(+), 464 deletions(-) delete mode 100644 patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-7c9dd840/001-bitmanip.patch create mode 100644 patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-815d9a14/001-bitmanip.patch diff --git a/.github/workflows/toolchain_build.yml b/.github/workflows/toolchain_build.yml index 4c3d227..b938cd6 100644 --- a/.github/workflows/toolchain_build.yml +++ b/.github/workflows/toolchain_build.yml @@ -28,7 +28,7 @@ jobs: display_name: Toolchains targeting Ibex with bit-manipulation extensions target: riscv32-unknown-elf output_dir: /tools/riscv - march: rv32imc_zba_zbb_zbc_zbs + march: rv32imcb_zbc_zbp0p93_zbe0p93_zbf0p93_zbm0p93_zbr0p93_zbt0p93 mabi: ilp32 mcmodel: medany - name: rv64imac diff --git a/lowrisc-toolchain-gcc-rv32imcb.config b/lowrisc-toolchain-gcc-rv32imcb.config index e164625..accb9a8 100644 --- a/lowrisc-toolchain-gcc-rv32imcb.config +++ b/lowrisc-toolchain-gcc-rv32imcb.config @@ -58,13 +58,12 @@ CT_PREFIX_DIR="/tools/riscv" # Don't chmod the CT_PREFIX_DIR read-only after the install. # CT_PREFIX_DIR_RO is not set -# Binutils 2.35, RISC-V bitmanip fork (branch riscv-binutils-2.35-rvb, -# commit 7c9dd840fb from 2021-03-10). -# A bitmanip 1.0+0.93 patch will be applied on top. +# Binutils 2.44 (tag binutils-2_44), commit 815d9a14 from 2025-02-02). +# A bitmanip 0.93 patch will be applied on top. CT_BINUTILS_SRC_DEVEL=y CT_BINUTILS_DEVEL_VCS_git=y -CT_BINUTILS_DEVEL_URL="https://github.com/riscv-collab/riscv-binutils-gdb.git" -CT_BINUTILS_DEVEL_REVISION="7c9dd840fbb6a1171a51feb08afb859288615137" +CT_BINUTILS_DEVEL_URL="https://github.com/bminor/binutils-gdb.git" +CT_BINUTILS_DEVEL_REVISION="815d9a14cbbb3b81843f7566222c87fb22e7255d" # GCC 10.2.0, RISC-V bitmanip fork (branch riscv-gcc-10.2.0-rvb, # commit 73055647d33 from 2021-07-09) diff --git a/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-7c9dd840/001-bitmanip.patch b/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-7c9dd840/001-bitmanip.patch deleted file mode 100644 index 527bd1b..0000000 --- a/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-7c9dd840/001-bitmanip.patch +++ /dev/null @@ -1,458 +0,0 @@ -diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h -index 53b5e143bc..3ba700f234 100644 ---- a/include/opcode/riscv-opc.h -+++ b/include/opcode/riscv-opc.h -@@ -195,32 +195,40 @@ - #define MASK_ORN 0xfe00707f - #define MATCH_XNOR 0x40004033 - #define MASK_XNOR 0xfe00707f -+#define MATCH_SLO 0x20001033 -+#define MASK_SLO 0xfe00707f -+#define MATCH_SRO 0x20005033 -+#define MASK_SRO 0xfe00707f - #define MATCH_ROL 0x60001033 - #define MASK_ROL 0xfe00707f - #define MATCH_ROR 0x60005033 - #define MASK_ROR 0xfe00707f --#define MATCH_SBCLR 0x48001033 --#define MASK_SBCLR 0xfe00707f --#define MATCH_SBSET 0x28001033 --#define MASK_SBSET 0xfe00707f --#define MATCH_SBINV 0x68001033 --#define MASK_SBINV 0xfe00707f --#define MATCH_SBEXT 0x48005033 --#define MASK_SBEXT 0xfe00707f -+#define MATCH_BCLR 0x48001033 -+#define MASK_BCLR 0xfe00707f -+#define MATCH_BSET 0x28001033 -+#define MASK_BSET 0xfe00707f -+#define MATCH_BINV 0x68001033 -+#define MASK_BINV 0xfe00707f -+#define MATCH_BEXT 0x48005033 -+#define MASK_BEXT 0xfe00707f - #define MATCH_GORC 0x28005033 - #define MASK_GORC 0xfe00707f - #define MATCH_GREV 0x68005033 - #define MASK_GREV 0xfe00707f -+#define MATCH_SLOI 0x20001013 -+#define MASK_SLOI 0xfc00707f -+#define MATCH_SROI 0x20005013 -+#define MASK_SROI 0xfc00707f - #define MATCH_RORI 0x60005013 - #define MASK_RORI 0xfc00707f --#define MATCH_SBCLRI 0x48001013 --#define MASK_SBCLRI 0xfc00707f --#define MATCH_SBSETI 0x28001013 --#define MASK_SBSETI 0xfc00707f --#define MATCH_SBINVI 0x68001013 --#define MASK_SBINVI 0xfc00707f --#define MATCH_SBEXTI 0x48005013 --#define MASK_SBEXTI 0xfc00707f -+#define MATCH_BCLRI 0x48001013 -+#define MASK_BCLRI 0xfc00707f -+#define MATCH_BSETI 0x28001013 -+#define MASK_BSETI 0xfc00707f -+#define MATCH_BINVI 0x68001013 -+#define MASK_BINVI 0xfc00707f -+#define MATCH_BEXTI 0x48005013 -+#define MASK_BEXTI 0xfc00707f - #define MATCH_GORCI 0x28005013 - #define MASK_GORCI 0xfc00707f - #define MATCH_GREVI 0x68005013 -@@ -239,8 +247,8 @@ - #define MASK_CLZ 0xfff0707f - #define MATCH_CTZ 0x60101013 - #define MASK_CTZ 0xfff0707f --#define MATCH_PCNT 0x60201013 --#define MASK_PCNT 0xfff0707f -+#define MATCH_CPOP 0x60201013 -+#define MASK_CPOP 0xfff0707f - #define MATCH_SEXT_B 0x60401013 - #define MASK_SEXT_B 0xfff0707f - #define MATCH_SEXT_H 0x60501013 -@@ -281,10 +289,10 @@ - #define MASK_SHFL 0xfe00707f - #define MATCH_UNSHFL 0x8005033 - #define MASK_UNSHFL 0xfe00707f --#define MATCH_BEXT 0x8006033 --#define MASK_BEXT 0xfe00707f --#define MATCH_BDEP 0x48006033 --#define MASK_BDEP 0xfe00707f -+#define MATCH_BCOMPRESS 0x8006033 -+#define MASK_BCOMPRESS 0xfe00707f -+#define MATCH_BDECOMPRESS 0x48006033 -+#define MASK_BDECOMPRESS 0xfe00707f - #define MATCH_PACK 0x8004033 - #define MASK_PACK 0xfe00707f - #define MATCH_PACKU 0x48004033 -@@ -307,34 +315,42 @@ - #define MASK_BMATOR 0xfe00707f - #define MATCH_BMATXOR 0x48003033 - #define MASK_BMATXOR 0xfe00707f --#define MATCH_SLLIU_W 0x800101b --#define MASK_SLLIU_W 0xfc00707f --#define MATCH_ADDU_W 0x800003b --#define MASK_ADDU_W 0xfe00707f -+#define MATCH_SLLI_UW 0x800101b -+#define MASK_SLLI_UW 0xfc00707f -+#define MATCH_ADD_UW 0x800003b -+#define MASK_ADD_UW 0xfe00707f -+#define MATCH_SLOW 0x2000103b -+#define MASK_SLOW 0xfe00707f -+#define MATCH_SROW 0x2000503b -+#define MASK_SROW 0xfe00707f - #define MATCH_ROLW 0x6000103b - #define MASK_ROLW 0xfe00707f - #define MATCH_RORW 0x6000503b - #define MASK_RORW 0xfe00707f --#define MATCH_SBCLRW 0x4800103b --#define MASK_SBCLRW 0xfe00707f --#define MATCH_SBSETW 0x2800103b --#define MASK_SBSETW 0xfe00707f --#define MATCH_SBINVW 0x6800103b --#define MASK_SBINVW 0xfe00707f --#define MATCH_SBEXTW 0x4800503b --#define MASK_SBEXTW 0xfe00707f -+#define MATCH_BCLRW 0x4800103b -+#define MASK_BCLRW 0xfe00707f -+#define MATCH_BSETW 0x2800103b -+#define MASK_BSETW 0xfe00707f -+#define MATCH_BINVW 0x6800103b -+#define MASK_BINVW 0xfe00707f -+#define MATCH_BEXTW 0x4800503b -+#define MASK_BEXTW 0xfe00707f - #define MATCH_GORCW 0x2800503b - #define MASK_GORCW 0xfe00707f - #define MATCH_GREVW 0x6800503b - #define MASK_GREVW 0xfe00707f -+#define MATCH_SLOIW 0x2000101b -+#define MASK_SLOIW 0xfe00707f -+#define MATCH_SROIW 0x2000501b -+#define MASK_SROIW 0xfe00707f - #define MATCH_RORIW 0x6000501b - #define MASK_RORIW 0xfe00707f --#define MATCH_SBCLRIW 0x4800101b --#define MASK_SBCLRIW 0xfe00707f --#define MATCH_SBSETIW 0x2800101b --#define MASK_SBSETIW 0xfe00707f --#define MATCH_SBINVIW 0x6800101b --#define MASK_SBINVIW 0xfe00707f -+#define MATCH_BCLRIW 0x4800101b -+#define MASK_BCLRIW 0xfe00707f -+#define MATCH_BSETIW 0x2800101b -+#define MASK_BSETIW 0xfe00707f -+#define MATCH_BINVIW 0x6800101b -+#define MASK_BINVIW 0xfe00707f - #define MATCH_GORCIW 0x2800501b - #define MASK_GORCIW 0xfe00707f - #define MATCH_GREVIW 0x6800501b -@@ -349,22 +365,22 @@ - #define MASK_CLZW 0xfff0707f - #define MATCH_CTZW 0x6010101b - #define MASK_CTZW 0xfff0707f --#define MATCH_PCNTW 0x6020101b --#define MASK_PCNTW 0xfff0707f --#define MATCH_SH1ADDU_W 0x2000203b --#define MASK_SH1ADDU_W 0xfe00707f --#define MATCH_SH2ADDU_W 0x2000403b --#define MASK_SH2ADDU_W 0xfe00707f --#define MATCH_SH3ADDU_W 0x2000603b --#define MASK_SH3ADDU_W 0xfe00707f -+#define MATCH_CPOPW 0x6020101b -+#define MASK_CPOPW 0xfff0707f -+#define MATCH_SH1ADD_UW 0x2000203b -+#define MASK_SH1ADD_UW 0xfe00707f -+#define MATCH_SH2ADD_UW 0x2000403b -+#define MASK_SH2ADD_UW 0xfe00707f -+#define MATCH_SH3ADD_UW 0x2000603b -+#define MASK_SH3ADD_UW 0xfe00707f - #define MATCH_SHFLW 0x800103b - #define MASK_SHFLW 0xfe00707f - #define MATCH_UNSHFLW 0x800503b - #define MASK_UNSHFLW 0xfe00707f --#define MATCH_BEXTW 0x800603b --#define MASK_BEXTW 0xfe00707f --#define MATCH_BDEPW 0x4800603b --#define MASK_BDEPW 0xfe00707f -+#define MATCH_BCOMPRESSW 0x800603b -+#define MASK_BCOMPRESSW 0xfe00707f -+#define MATCH_BDECOMPRESSW 0x4800603b -+#define MASK_BDECOMPRESSW 0xfe00707f - #define MATCH_PACKW 0x800403b - #define MASK_PACKW 0xfe00707f - #define MATCH_PACKUW 0x4800403b -@@ -1121,19 +1137,23 @@ DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) - DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) - DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) - DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) -+DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) -+DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) - DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) - DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) --DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR) --DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET) --DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV) --DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT) -+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) -+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) -+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) -+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) - DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) - DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) -+DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) -+DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) - DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) --DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI) --DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI) --DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI) --DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI) -+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) -+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) -+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) -+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) - DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) - DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) - DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) -@@ -1143,7 +1163,7 @@ DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) - DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) - DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) - DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) --DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT) -+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) - DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) - DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) - DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) -@@ -1164,8 +1184,8 @@ DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) - DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) - DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) - DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) --DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) --DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP) -+DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) -+DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) - DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) - DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) - DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) -@@ -1177,20 +1197,24 @@ DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) - DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) - DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) - DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) --DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W) --DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W) -+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) -+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) -+DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) -+DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) - DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) - DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) --DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW) --DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW) --DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW) --DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW) -+DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW) -+DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW) -+DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW) -+DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW) - DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) - DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) -+DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) -+DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) - DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) --DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW) --DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW) --DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW) -+DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW) -+DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW) -+DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW) - DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) - DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) - DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) -@@ -1198,14 +1222,14 @@ DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) - DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) - DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) - DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) --DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW) --DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W) --DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W) --DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W) -+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) -+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) -+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) -+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) - DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) - DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) --DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW) --DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW) -+DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) -+DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) - DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) - DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) - DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) -diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c -index 3a59630101..0d962fa8a5 100644 ---- a/opcodes/riscv-opc.c -+++ b/opcodes/riscv-opc.c -@@ -502,24 +502,30 @@ const struct riscv_opcode riscv_opcodes[] = - {"andn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 }, - {"orn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 }, - {"xnor", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 }, -+{"sloi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 }, -+{"sroi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 }, - {"rori", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 }, -+{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 }, -+{"slo", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, INSN_ALIAS }, -+{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 }, -+{"sro", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, INSN_ALIAS }, - {"rol", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 }, - {"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 }, - {"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS }, --{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 }, --{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 }, --{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 }, --{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 }, -+{"bclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 }, -+{"bseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 }, -+{"binvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 }, -+{"bexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 }, - {"gorci", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 }, - {"grevi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 }, --{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 }, --{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS }, --{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 }, --{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS }, --{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 }, --{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS }, --{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 }, --{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS }, -+{"bclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 }, -+{"bclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS }, -+{"bset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 }, -+{"bset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS }, -+{"binv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 }, -+{"binv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS }, -+{"bext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 }, -+{"bext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS }, - {"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 }, - {"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS }, - {"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 }, -@@ -532,7 +538,7 @@ const struct riscv_opcode riscv_opcodes[] = - {"fsr", 0, INSN_CLASS_B_OR_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS }, - {"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, - {"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, --{"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 }, -+{"cpop", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 }, - {"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 }, - {"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 }, - {"bmatflip", 64, INSN_CLASS_B_OR_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 }, -@@ -560,8 +566,8 @@ const struct riscv_opcode riscv_opcodes[] = - {"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS }, - {"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 }, - {"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS }, --{"bdep", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 }, --{"bext", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 }, -+{"bdecompress", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 }, -+{"bcompress", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 }, - {"pack", 0, INSN_CLASS_B_OR_ZBF_OR_ZBP, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 }, - {"zext.h", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, - {"zext.h", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, -@@ -571,24 +577,30 @@ const struct riscv_opcode riscv_opcodes[] = - {"bmator", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 }, - {"bmatxor", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 }, - {"bfp", 0, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 }, --{"slliu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 }, --{"addu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 }, -+{"slli.uw", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 }, -+{"add.uw", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 }, -+{"sloiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 }, -+{"sroiw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 }, - {"roriw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 }, -+{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 }, -+{"slow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, INSN_ALIAS }, -+{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SROW, MASK_SROW, match_opcode, 0 }, -+{"srow", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, INSN_ALIAS }, - {"rolw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 }, - {"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 }, - {"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS }, --{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 }, --{"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 }, --{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 }, -+{"bclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 }, -+{"bsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 }, -+{"binviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 }, - {"gorciw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 }, - {"greviw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 }, --{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 }, --{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS }, --{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 }, --{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS }, --{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 }, --{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS }, --{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 }, -+{"bclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 }, -+{"bclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS }, -+{"bsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 }, -+{"bsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS }, -+{"binvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 }, -+{"binvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS }, -+{"bextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 }, - {"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 }, - {"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS }, - {"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 }, -@@ -599,21 +611,21 @@ const struct riscv_opcode riscv_opcodes[] = - {"fsrw", 64, INSN_CLASS_B_OR_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS }, - {"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 }, - {"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 }, --{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 }, --{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 }, --{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 }, --{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 }, -+{"cpopw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 }, -+{"sh1add.uw",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 }, -+{"sh2add.uw",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 }, -+{"sh3add.uw",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 }, - {"shflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 }, - {"unshflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 }, --{"bdepw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 }, --{"bextw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 }, -+{"bdecompressw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 }, -+{"bcompressw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 }, - {"packw", 64, INSN_CLASS_B_OR_ZBF_OR_ZBP, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 }, - {"packuw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 }, - {"bfpw", 64, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 }, - {"xperm.n", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 }, - {"xperm.b", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 }, - {"xperm.h", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 }, --{"xperm.w", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 }, -+{"xperm.w", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 }, - - /* Bitmanip pseudo-instructions */ - {"rev.p", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO }, -@@ -1133,17 +1145,17 @@ const struct riscv_ext_version riscv_ext_version_table[] = - {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvqmac", ISA_SPEC_CLASS_NONE, 1, 0}, - --{"b", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbb", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbs", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zba", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbp", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbe", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbf", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbc", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbr", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbm", ISA_SPEC_CLASS_NONE, 0, 92}, --{"zbt", ISA_SPEC_CLASS_NONE, 0, 92}, -+{"b", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbb", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbs", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zba", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbp", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbe", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbf", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbc", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbr", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbm", ISA_SPEC_CLASS_NONE, 0, 93}, -+{"zbt", ISA_SPEC_CLASS_NONE, 0, 93}, - - /* Terminate the list. */ - {NULL, 0, 0, 0} diff --git a/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-815d9a14/001-bitmanip.patch b/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-815d9a14/001-bitmanip.patch new file mode 100644 index 0000000..3a0fabd --- /dev/null +++ b/patches/lowrisc-toolchain-gcc-rv32imcb/binutils/git-815d9a14/001-bitmanip.patch @@ -0,0 +1,339 @@ +commit fd6e38698009f8c402102d60010503447d1748ab +Author: James Wainwright +Date: Mon Mar 3 17:42:38 2025 +0000 + + Add unratified bitmanip instructions + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index c9e4b03b17d..b0a8c07ff5c 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1381,6 +1381,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zbp", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, ++ {"zbe", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, ++ {"zbf", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, ++ {"zbm", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, ++ {"zbr", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, ++ {"zbt", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 }, + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2679,6 +2686,18 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zbc"); + case INSN_CLASS_ZBS: + return riscv_subset_supports (rps, "zbs"); ++ case INSN_CLASS_ZBP: ++ return riscv_subset_supports (rps, "zbp"); ++ case INSN_CLASS_ZBE: ++ return riscv_subset_supports (rps, "zbe"); ++ case INSN_CLASS_ZBF: ++ return riscv_subset_supports (rps, "zbf"); ++ case INSN_CLASS_ZBM: ++ return riscv_subset_supports (rps, "zbm"); ++ case INSN_CLASS_ZBR: ++ return riscv_subset_supports (rps, "zbr"); ++ case INSN_CLASS_ZBT: ++ return riscv_subset_supports (rps, "zbt"); + case INSN_CLASS_ZBKB: + return riscv_subset_supports (rps, "zbkb"); + case INSN_CLASS_ZBKC: +@@ -2997,6 +3016,18 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "zbc"; + case INSN_CLASS_ZBS: + return "zbs"; ++ case INSN_CLASS_ZBP: ++ return "zbp"; ++ case INSN_CLASS_ZBE: ++ return "zbe"; ++ case INSN_CLASS_ZBF: ++ return "zbf"; ++ case INSN_CLASS_ZBM: ++ return "zbm"; ++ case INSN_CLASS_ZBR: ++ return "zbr"; ++ case INSN_CLASS_ZBT: ++ return "zbt"; + case INSN_CLASS_ZBKB: + return "zbkb"; + case INSN_CLASS_ZBKC: +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 71ad7fff84d..64033885032 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3786,6 +3786,109 @@ + #define MASK_SFVFNRCLIPXUFQF 0xfe00707f + #define MATCH_SFVFNRCLIPXFQF 0x8e00505b + #define MASK_SFVFNRCLIPXFQF 0xfe00707f ++/* Unratified Zbp instructions */ ++#define MATCH_PACKU 0x48004033 ++#define MASK_PACKU 0xfe00707f ++#define MATCH_PACKUW 0x4800403b ++#define MASK_PACKUW 0xfe00707f ++#define MATCH_GREV 0x68005033 ++#define MASK_GREV 0xfe00707f ++#define MATCH_GREVIW 0x68005013 ++#define MASK_GREVIW 0xfc00707f ++#define MATCH_GREVW 0x6800503b ++#define MASK_GREVW 0xfe00707f ++#define MATCH_GORC 0x28005033 ++#define MASK_GORC 0xfe00707f ++#define MATCH_GORCIW 0x2800501b ++#define MASK_GORCIW 0xfe00707f ++#define MATCH_GORCW 0x2800503b ++#define MASK_GORCW 0xfe00707f ++#define MATCH_SHFL 0x8001033 ++#define MASK_SHFL 0xfe00707f ++#define MATCH_SHFLW 0x800103b ++#define MASK_SHFLW 0xfe00707f ++#define MATCH_UNSHFL 0x8005033 ++#define MASK_UNSHFL 0xfe00707f ++#define MATCH_UNSHFLW 0x800503b ++#define MASK_UNSHFLW 0xfe00707f ++#define MATCH_XPERMN 0x28002033 ++#define MASK_XPERMN 0xfe00707f ++#define MATCH_XPERMB 0x28004033 ++#define MASK_XPERMB 0xfe00707f ++#define MATCH_XPERMH 0x28006033 ++#define MASK_XPERMH 0xfe00707f ++#define MATCH_XPERMW 0x28000033 ++#define MASK_XPERMW 0xfe00707f ++/* Unratified Zbs instructions */ ++#define MATCH_BSETW 0x2800103b ++#define MASK_BSETW 0xfe00707f ++#define MATCH_BSETIW 0x2800101b ++#define MASK_BSETIW 0xfe00707f ++#define MATCH_BCLRW 0x4800103b ++#define MASK_BCLRW 0xfe00707f ++#define MATCH_BCLRIW 0x4800101b ++#define MASK_BCLRIW 0xfe00707f ++#define MATCH_BEXTW 0x4800503b ++#define MASK_BEXTW 0xfe00707f ++#define MATCH_BINVW 0x6800103b ++#define MASK_BINVW 0xfe00707f ++#define MATCH_BINVIW 0x6800101b ++#define MASK_BINVIW 0xfe00707f ++/* Unratified Zbe instructions */ ++#define MATCH_BCOMPRESS 0x8006033 ++#define MASK_BCOMPRESS 0xfe00707f ++#define MATCH_BDECOMPRESS 0x48006033 ++#define MASK_BDECOMPRESS 0xfe00707f ++#define MATCH_BCOMPRESSW 0x800603b ++#define MASK_BCOMPRESSW 0xfe00707f ++#define MATCH_BDECOMPRESSW 0x4800603b ++#define MASK_BDECOMPRESSW 0xfe00707f ++/* Unratified Zbf instructions */ ++#define MATCH_BFP 0x48007033 ++#define MASK_BFP 0xfe00707f ++#define MATCH_BFPW 0x4800703b ++#define MASK_BFPW 0xfe00707f ++/* Unratified Zbm instructions */ ++#define MATCH_BMATFLIP 0x60301013 ++#define MASK_BMATFLIP 0xfff0707f ++#define MATCH_BMATOR 0x8003033 ++#define MASK_BMATOR 0xfe00707f ++#define MATCH_BMATXOR 0x48003033 ++#define MASK_BMATXOR 0xfe00707f ++/* Unratified Zbr instructions */ ++#define MATCH_CRC32_B 0x61001013 ++#define MASK_CRC32_B 0xfff0707f ++#define MATCH_CRC32C_B 0x61801013 ++#define MASK_CRC32C_B 0xfff0707f ++#define MATCH_CRC32_H 0x61101013 ++#define MASK_CRC32_H 0xfff0707f ++#define MATCH_CRC32C_H 0x61901013 ++#define MASK_CRC32C_H 0xfff0707f ++#define MATCH_CRC32_W 0x61201013 ++#define MASK_CRC32_W 0xfff0707f ++#define MATCH_CRC32C_W 0x61a01013 ++#define MASK_CRC32C_W 0xfff0707f ++#define MATCH_CRC32_D 0x61301013 ++#define MASK_CRC32_D 0xfff0707f ++#define MATCH_CRC32C_D 0x61b01013 ++#define MASK_CRC32C_D 0xfff0707f ++/* Unratified Zbt instructions */ ++#define MATCH_CMIX 0x6001033 ++#define MASK_CMIX 0x600707f ++#define MATCH_CMOV 0x6005033 ++#define MASK_CMOV 0x600707f ++#define MATCH_FSL 0x4001033 ++#define MASK_FSL 0x600707f ++#define MATCH_FSLW 0x400103b ++#define MASK_FSLW 0x600707f ++#define MATCH_FSR 0x4005033 ++#define MASK_FSR 0x600707f ++#define MATCH_FSRI 0x4005013 ++#define MASK_FSRI 0x400707f ++#define MATCH_FSRW 0x400503b ++#define MASK_FSRW 0x600707f ++#define MATCH_FSRIW 0x400501b ++#define MASK_FSRIW 0x600707f + /* Unprivileged Counter/Timers CSR addresses. */ + #define CSR_CYCLE 0xc00 + #define CSR_TIME 0xc01 +@@ -4923,6 +5026,61 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) + DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) + /* Zicfilp instructions. */ + DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) ++/* Unratified Zbp instructions */ ++DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) ++DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) ++DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) ++DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) ++DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) ++DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) ++DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) ++DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) ++DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) ++DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) ++DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) ++DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) ++DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N) ++DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B) ++DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H) ++DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W) ++/* Unratified Zbs instructions */ ++DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW) ++DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW) ++DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW) ++DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW) ++DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW) ++DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW) ++DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW) ++/* Unratified Zbe instructions */ ++DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) ++DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) ++DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) ++DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) ++/* Unratified Zbf instructions */ ++DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) ++DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) ++/* Unratified Zbm instructions */ ++DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) ++DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) ++DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) ++/* Unratified Zbr instructions */ ++DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) ++DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) ++DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) ++DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) ++DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) ++DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) ++DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) ++DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) ++/* Unratified Zbt instructions */ ++DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) ++DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) ++DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) ++DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) ++DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) ++DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) ++DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) ++DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) + #endif /* DECLARE_INSN */ + #ifdef DECLARE_CSR + /* Unprivileged Counter/Timers CSRs. */ +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 6bcea638025..24916f1a4d8 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -492,6 +492,12 @@ enum riscv_insn_class + INSN_CLASS_ZBB, + INSN_CLASS_ZBC, + INSN_CLASS_ZBS, ++ INSN_CLASS_ZBP, ++ INSN_CLASS_ZBE, ++ INSN_CLASS_ZBF, ++ INSN_CLASS_ZBM, ++ INSN_CLASS_ZBR, ++ INSN_CLASS_ZBT, + INSN_CLASS_ZBKB, + INSN_CLASS_ZBKC, + INSN_CLASS_ZBKX, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index ceb94a563e2..4a6cf65a08d 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -3510,6 +3510,79 @@ const struct riscv_opcode riscv_opcodes[] = + {"sf.vfnrclip.xu.f.qf", 0, INSN_CLASS_XSFVFNRCLIPXFQF, "Vd,Vt,S", MATCH_SFVFNRCLIPXUFQF, MASK_SFVFNRCLIPXUFQF, match_opcode, 0}, + {"sf.vfnrclip.x.f.qf", 0, INSN_CLASS_XSFVFNRCLIPXFQF, "Vd,Vt,S", MATCH_SFVFNRCLIPXFQF, MASK_SFVFNRCLIPXFQF, match_opcode, 0}, + ++/* Unratified Zbp instructions */ ++{"packu", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 }, ++{"packuw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 }, ++{"grev", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 }, ++{"grev", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS }, ++{"greviw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 }, ++{"grevw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 }, ++{"grevw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS }, ++{"gorc", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 }, ++{"gorc", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS }, ++{"gorciw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 }, ++{"gorcw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 }, ++{"gorcw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS }, ++{"shfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 }, ++{"shfl", 0, INSN_CLASS_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS }, ++{"shflw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 }, ++{"unshfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 }, ++{"unshfl", 0, INSN_CLASS_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS }, ++{"unshflw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 }, ++{"xperm.n", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 }, ++{"xperm.b", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 }, ++{"xperm.h", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 }, ++{"xperm.w", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 }, ++ ++/* Unratified Zbs instructions */ ++{"bsetw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 }, ++{"bsetw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS }, ++{"bsetiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 }, ++{"bclrw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 }, ++{"bclrw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS }, ++{"bclriw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 }, ++{"bextw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 }, ++{"binvw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 }, ++{"binvw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS }, ++{"binviw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 }, ++ ++/* Unratified Zbe instructions */ ++{"bcompress", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 }, ++{"bdecompress", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 }, ++{"bcompressw", 64, INSN_CLASS_ZBE, "d,s,t", MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 }, ++{"bdecompressw", 64, INSN_CLASS_ZBE, "d,s,t", MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 }, ++ ++/* Unratified Zbf instructions */ ++{"bfp", 0, INSN_CLASS_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 }, ++{"bfpw", 64, INSN_CLASS_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 }, ++ ++/* Unratified Zbm instructions */ ++{"bmatflip", 64, INSN_CLASS_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 }, ++{"bmator", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 }, ++{"bmatxor", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 }, ++ ++/* Unratified Zbr instructions */ ++{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 }, ++{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 }, ++{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 }, ++{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 }, ++{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 }, ++{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 }, ++{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 }, ++{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 }, ++ ++/* Unratified Zbt instructions */ ++{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 }, ++{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 }, ++{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 }, ++{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 }, ++{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 }, ++{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS }, ++{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 }, ++{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 }, ++{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS }, ++{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 }, ++ + /* Terminate the list. */ + {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} + };