Search results

[RegAlloc] Fix use-after-free in <code>RegAllocBase::cleanupFailedVReg</code>

backend:AMDGPU

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151435

#151435 In llvm/llvm-project;

· shiltian opened on Jul 31, 2025

[CodeGen] MachineVerifier to check early-clobber constraint

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151421

#151421 In llvm/llvm-project;

· AbhayKanhere opened on Jul 30, 2025

[RISCV] Put Large Code Model Constant Pools in .text

backend:Lanai

backend:MIPS

backend:NVPTX

backend:RISC-V

backend:SPIR-V

backend:X86

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151393

#151393 In llvm/llvm-project;

· lenary opened on Jul 30, 2025

[DebugInfo][DWARF] Don't emit bogus DW_AT_call_target for complex calls

backend:AArch64

backend:X86

debuginfo

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151378

#151378 In llvm/llvm-project;

· thejh opened on Jul 30, 2025

[LLVM][CGP] Allow finer control for sinking compares.

backend:AArch64

backend:AMDGPU

backend:PowerPC

llvm:codegen

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 151366

#151366 In llvm/llvm-project;

· paulwalker-arm opened on Jul 30, 2025

[MachineBB] Make sure there are successors in terminatorIsComputedGoto.

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151342

#151342 In llvm/llvm-project;

· fhahn opened on Jul 30, 2025

[AArch64] Support symmetric complex deinterleaving with higher factors

backend:AArch64

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151295

#151295 In llvm/llvm-project;

· david-arm opened on Jul 30, 2025

[DWARF] Emit 0/1 for constant boolean values

backend:NVPTX

debuginfo

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151225

#151225 In llvm/llvm-project;

· laxmansole opened on Jul 29, 2025

[WIP][AMDGPU][CopyPhysReg] Expand the COPY instructions using the encoded liveness mask.

backend:AMDGPU

llvm:codegen

llvm:globalisel

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 151124

#151124 In llvm/llvm-project;

· vg0204 opened on Jul 29, 2025

[WIP][CodeGen] Encode liveness for COPY instructions after virtRegRewriter pass.

backend:AMDGPU

llvm:codegen

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 151123

#151123 In llvm/llvm-project;

· vg0204 opened on Jul 29, 2025

[X86][GlobalIsel] Support IS_FP_CLASS intrinsic 1/4

backend:X86

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 151084

#151084 In llvm/llvm-project;

· mahesh-attarde opened on Jul 29, 2025

[AMDGPU]: Do not provide AGPR for AV if !mayNeedAGPRs

backend:AMDGPU

llvm:codegen

llvm:regalloc

Status: Open (in progress).

llvm/llvm-projectnumber 151063

#151063 In llvm/llvm-project;

· jrbyrnes opened on Jul 29, 2025