Search results

[RISCV] Fix Compression with Symbols for Xqci

backend:RISC-V

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 146184

#146184 In llvm/llvm-project;

· lenary opened on Jun 28, 2025

[ISel/RISCV] Refactor isPromotedOpNeedingSplit (NFC)

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 146059

#146059 In llvm/llvm-project;

· artagnon opened on Jun 27, 2025

[CostModel/RISCV] Fix costs of [l]lrint

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

Status: Open (in progress).

llvm/llvm-projectnumber 146058

#146058 In llvm/llvm-project;

· artagnon opened on Jun 27, 2025

[NFC] Remove getDefaultCallingConvention IsBuiltin

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

Status: Open (in progress).

llvm/llvm-projectnumber 145904

#145904 In llvm/llvm-project;

· hvdijk opened on Jun 26, 2025

[ISel/RISCV] Fix fixed-vector [l]lrint lowering

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 145898

#145898 In llvm/llvm-project;

· artagnon opened on Jun 26, 2025

[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700.

backend:MIPS

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 145647

#145647 In llvm/llvm-project;

· ukalappa-mips opened on Jun 25, 2025

[clang][RISCV] Fix crash on VLS calling convention

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

Status: Open (in progress).

llvm/llvm-projectnumber 145489

#145489 In llvm/llvm-project;

· 4vtomat opened on Jun 24, 2025

DAG: Emit an error if trying to legalize read/write register with illegal types

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SystemZ

backend:X86

llvm:codegen

llvm:globalisel

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145197

#145197 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 145147

#145147 In llvm/llvm-project;

· tclin914 opened on Jun 21, 2025

[LangRef] Require that vscale be a power of two

backend:AArch64

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 145098

#145098 In llvm/llvm-project;

· preames opened on Jun 20, 2025

[RISCV] Large code model places integer/FP constant pool entries in .rodata and uses PC-relative accesses.

backend:RISC-V

Status: Open.

#145080 In llvm/llvm-project;

· topperc opened on Jun 20, 2025

[VPlan] Emit VPVectorEndPointerRecipe for reverse interleave pointer adjustment

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 144864

#144864 In llvm/llvm-project;

· Mel-Chen opened on Jun 19, 2025