[fhahn]

InterferenceCache::Entry::update rescans all regunit iterators for the earliest interference start in each interference-free block it precomputes, but the iterators don't move in that loop. Compute the earliest start once before the loop.

stage1-O3: -0.10%
stage1-ReleaseThinLTO: -0.09%
stage1-ReleaseLTO-g: -0.09%
stage1-aarch64-O3: -0.14%
stage2-O3: -0.09%
stage2-clang: -0.05%

https://llvm-compile-time-tracker.com/compare.php?from=9fadd0df057adb0489b91c7efb02c6f32ce8b8d6&to=7b94287220946edc86f6308e04521c4ec7709566&stat=instructions:u

Found by Opus 5.5

[llvmorg-github-actions]

@llvm/pr-subscribers-llvm-regalloc

Author: Florian Hahn (fhahn)

Changes

InterferenceCache::Entry::update rescans all regunit iterators for the earliest interference start in each interference-free block it precomputes, but the iterators don't move in that loop. Compute the earliest start once before the loop.

stage1-O3: -0.10%
stage1-ReleaseThinLTO: -0.09%
stage1-ReleaseLTO-g: -0.09%
stage1-aarch64-O3: -0.14%
stage2-O3: -0.09%
stage2-clang: -0.05%

https://llvm-compile-time-tracker.com/compare.php?from=9fadd0df057adb0489b91c7efb02c6f32ce8b8d6&to=7b94287220946edc86f6308e04521c4ec7709566&stat=instructions:u

Found by Opus 5.5

---

Full diff: https://github.com/llvm/llvm-project/pull/240064.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/InterferenceCache.cpp (+16-24)

diff --git a/llvm/lib/CodeGen/InterferenceCache.cpp b/llvm/lib/CodeGen/InterferenceCache.cpp
index 0a4e4c36504e5..a7d4e20d7c2d1 100644
--- a/llvm/lib/CodeGen/InterferenceCache.cpp
+++ b/llvm/lib/CodeGen/InterferenceCache.cpp
@@ -154,34 +154,26 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
   BlockInterference *BI = &Blocks[MBBNum];
   ArrayRef<SlotIndex> RegMaskSlots;
   ArrayRef<const uint32_t*> RegMaskBits;
+
+  // Find the earliest virtreg and fixed interference start.
+  SlotIndex FirstStart;
+  for (RegUnitInfo &RUI : RegUnits) {
+    LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
+    if (I.valid() && (!FirstStart.isValid() || I.start() < FirstStart))
+      FirstStart = I.start();
+    LiveInterval::const_iterator FI = RUI.FixedI;
+    if (FI != RUI.Fixed->end() &&
+        (!FirstStart.isValid() || FI->start < FirstStart))
+      FirstStart = FI->start;
+  }
+
   while (true) {
     BI->Tag = Tag;
     BI->First = BI->Last = SlotIndex();
 
-    // Check for first interference from virtregs.
-    for (RegUnitInfo &RUI : RegUnits) {
-      LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
-      if (!I.valid())
-        continue;
-      SlotIndex StartI = I.start();
-      if (StartI >= Stop)
-        continue;
-      if (!BI->First.isValid() || StartI < BI->First)
-        BI->First = StartI;
-    }
-
-    // Same thing for fixed interference.
-    for (RegUnitInfo &RUI : RegUnits) {
-      LiveInterval::const_iterator I = RUI.FixedI;
-      LiveInterval::const_iterator E = RUI.Fixed->end();
-      if (I == E)
-        continue;
-      SlotIndex StartI = I->start;
-      if (StartI >= Stop)
-        continue;
-      if (!BI->First.isValid() || StartI < BI->First)
-        BI->First = StartI;
-    }
+    // Check for first interference from virtregs and fixed interference.
+    if (FirstStart.isValid() && FirstStart < Stop)
+      BI->First = FirstStart;
 
     // Also check for register mask interference.
     RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);