Repository navigation
Conversation
If both predicates have matching LHS and RHS, check if one implies the other via isImpliedByMatchingCmp. This handles a few more cases and fixes a miscompile where previously we did not check the predicate of N.
llvmorg-github-actions
Bot
added
llvm:analysis
|
@llvm/pr-subscribers-llvm-transforms @llvm/pr-subscribers-llvm-loopaccessanalysis Author: Florian Hahn (fhahn) ChangesIf both predicates have matching LHS and RHS, check if one implies the other via isImpliedByMatchingCmp. This handles a few more cases and fixes a miscompile where previously we did not check the predicate of N. Full diff: https://github.com/llvm/llvm-project/pull/240053.diff 4 Files Affected:
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 08b2348f0218c..2b86b45e729f5 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -15293,10 +15293,10 @@ bool SCEVComparePredicate::implies(const SCEVPredicate *N,
if (!Op)
return false;
- if (Pred != ICmpInst::ICMP_EQ)
+ if (Op->LHS != LHS || Op->RHS != RHS)
return false;
- return Op->LHS == LHS && Op->RHS == RHS;
+ return ICmpInst::isImpliedByMatchingCmp(Pred, Op->Pred) == true;
}
bool SCEVComparePredicate::isAlwaysTrue() const { return false; }
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging-unknown-deps.ll b/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging-unknown-deps.ll
index 062725063f07a..cd420e5321f8a 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging-unknown-deps.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging-unknown-deps.ll
@@ -84,8 +84,6 @@ define void @stencil_loads_and_independent_stores_with_unknown_deps(ptr %a, ptr
; FORCE-NEXT: SCEV assumptions:
; FORCE-NEXT: Compare predicate: %m sgt) 0
; FORCE-NEXT: Compare predicate: %m sle) 1152921504606846975
-; FORCE-NEXT: Compare predicate: %m sgt) 0
-; FORCE-NEXT: Compare predicate: %m sle) 1152921504606846975
; FORCE-EMPTY:
; FORCE-NEXT: Expressions re-written:
;
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging.ll b/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging.ll
index 496e97813a7d1..b261f585fffd9 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/stencil-group-merging.ll
@@ -4069,6 +4069,7 @@ define void @equal_predicate_does_not_imply_positive_stride(ptr %src, ptr %dst,
; MERGE-NEXT: Non vectorizable stores to invariant address were not found in loop.
; MERGE-NEXT: SCEV assumptions:
; MERGE-NEXT: Equal predicate: (zext i2 (trunc i64 %k to i2) to i64) == 0
+; MERGE-NEXT: Compare predicate: (zext i2 (trunc i64 %k to i2) to i64) sgt) 0
; MERGE-EMPTY:
; MERGE-NEXT: Expressions re-written:
;
diff --git a/llvm/test/Transforms/LoopVectorize/predicated-inductions.ll b/llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
index 2c022395c9794..942b14d961829 100644
--- a/llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
@@ -1135,11 +1135,11 @@ define void @btc_predicate_added_multiple_times(ptr %dst, i64 %stride, i64 %n) {
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[IDX_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IDX_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IDX]]
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
; CHECK-NEXT: [[IDX_NEXT]] = add nuw nsw i64 [[IDX]], 1
@@ -1168,16 +1168,47 @@ define void @btc_predicate_added_multiple_times(ptr %dst, i64 %stride, i64 %n) {
; THRESHOLD1-LABEL: define void @btc_predicate_added_multiple_times(
; THRESHOLD1-SAME: ptr [[DST:%.*]], i64 [[STRIDE:%.*]], i64 [[N:%.*]]) {
; THRESHOLD1-NEXT: [[ENTRY:.*]]:
+; THRESHOLD1-NEXT: [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[STRIDE]])
+; THRESHOLD1-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[STRIDE]]
+; THRESHOLD1-NEXT: [[TMP2:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 1)
+; THRESHOLD1-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], [[TMP2]]
+; THRESHOLD1-NEXT: [[TMP4:%.*]] = call i64 @llvm.umax.i64(i64 [[STRIDE]], i64 1)
+; THRESHOLD1-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP3]], [[TMP4]]
+; THRESHOLD1-NEXT: [[TMP6:%.*]] = add i64 [[TMP2]], [[TMP5]]
+; THRESHOLD1-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 1
+; THRESHOLD1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP7]], 4
+; THRESHOLD1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; THRESHOLD1: [[VECTOR_SCEVCHECK]]:
+; THRESHOLD1-NEXT: [[IDENT_CHECK:%.*]] = icmp sle i64 [[STRIDE]], 0
+; THRESHOLD1-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; THRESHOLD1: [[VECTOR_PH]]:
+; THRESHOLD1-NEXT: [[TMP8:%.*]] = and i64 [[TMP7]], 3
+; THRESHOLD1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP7]], [[TMP8]]
+; THRESHOLD1-NEXT: [[TMP9:%.*]] = mul i64 [[N_VEC]], [[STRIDE]]
+; THRESHOLD1-NEXT: br label %[[VECTOR_BODY:.*]]
+; THRESHOLD1: [[VECTOR_BODY]]:
+; THRESHOLD1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; THRESHOLD1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[INDEX]]
+; THRESHOLD1-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP10]], align 4
+; THRESHOLD1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; THRESHOLD1-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; THRESHOLD1-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; THRESHOLD1: [[MIDDLE_BLOCK]]:
+; THRESHOLD1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP7]], [[N_VEC]]
+; THRESHOLD1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; THRESHOLD1: [[SCALAR_PH]]:
+; THRESHOLD1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; THRESHOLD1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; THRESHOLD1-NEXT: br label %[[LOOP:.*]]
; THRESHOLD1: [[LOOP]]:
-; THRESHOLD1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; THRESHOLD1-NEXT: [[IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IDX_NEXT:%.*]], %[[LOOP]] ]
+; THRESHOLD1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; THRESHOLD1-NEXT: [[IDX:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IDX_NEXT:%.*]], %[[LOOP]] ]
; THRESHOLD1-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IDX]]
; THRESHOLD1-NEXT: store i32 0, ptr [[GEP]], align 4
; THRESHOLD1-NEXT: [[IDX_NEXT]] = add nuw nsw i64 [[IDX]], 1
; THRESHOLD1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], [[STRIDE]]
; THRESHOLD1-NEXT: [[EC:%.*]] = icmp slt i64 [[IV_NEXT]], [[N]]
-; THRESHOLD1-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]]
+; THRESHOLD1-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]
; THRESHOLD1: [[EXIT]]:
; THRESHOLD1-NEXT: ret void
;
|
This branch has not been deployed
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
If both predicates have matching LHS and RHS, check if one implies the other via isImpliedByMatchingCmp. This handles a few more cases and fixes a miscompile where previously we did not check the predicate of N.