Missed Optimization: eliminate redundant modulus when divisor divides previous modulus

[Leo0506]

define i8 @src(i64 %arg0) {
  %v0 = trunc i64 %arg0 to i8
  %v1 = urem i8 %v0, 25
  %v2 = urem i8 %v1, 5
  ret i8 %v2
}

define i8 @tgt(i64 %arg0) {
  %v0 = trunc i64 %arg0 to i8
  %v2 = urem i8 %v0, 5
  ret i8 %v2
}

godbolt: https://godbolt.org/z/ebK55TMnE
alive2: https://alive2.llvm.org/ce/z/pDxaza

Pattern found in: https://github.com/dtcxzyw/llvm-opt-benchmark/blob/main/bench/ffmpeg/optimized/ac3dec_fixed.ll

[RKSimon]

More general alive2:

define i4 @src(i4 %a0, i4 %mod0, i4 %mod1) {
  %v1 = urem i4 %a0, %mod0
  %v2 = urem i4 %v1, %mod1
  %m = urem i4 %mod0, %mod1
  %mz = icmp eq i4 %m, 0
  call void @llvm.assume(i1 %mz)
  ret i4 %v2
}
define i4 @tgt(i4 %a0, i4 %mod0, i4 %mod1) {
  %v2 = urem i4 %a0, %mod1
  ret i4 %v2
}

[kper]

I would like to work on that :)

[kper]

As discussed in the linked PR, it is not profitable to do the optimisation.
(I don't have the rights to close the issue)

[RKSimon]

Worth trying to do it in DAG instead?

[kper]

Yeah sure :)
But I am leaving soon for vacation; gonna start working on it next weekend.

Could you point me to the direction where to fix it? @RKSimon

[RKSimon]

At the bottom of DAGCombiner::visitREM makes sense to me - you can use the sd_match equivalent of the pattern matchers you were using in instcombine - sd_match, m_URem, m_OneUse, m_ConstInt etc.