[CIR][AArch64] Implement NEON builtin vaddvq_s16

Implement vaddvq_s16 (add across vector, signed 16-bit quadword)
using the generic vector.reduce.add intrinsic to match OG codegen.

Test includes CIR, LLVM, and OGCG check patterns.

Author: bcardosolopes

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -4318,7 +4318,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
     llvm_unreachable("NEON::BI__builtin_neon_vaddvq_u16 NYI");
     [[fallthrough]];
   case NEON::BI__builtin_neon_vaddvq_s16: {
-    llvm_unreachable("NEON::BI__builtin_neon_vaddvq_s16 NYI");
+    return emitCommonNeonVecAcrossCall(*this, "vector.reduce.add", SInt16Ty, 8,
+                                       E);
   }
   case NEON::BI__builtin_neon_vmaxv_u8: {
     return emitCommonNeonVecAcrossCall(*this, "aarch64.neon.umaxv", UInt8Ty, 8,

clang/test/CIR/CodeGen/AArch64/neon.c

@@ -18803,6 +18803,22 @@ int8_t test_vminvq_s8(int8x16_t a) {
   // OGCG: ret i8
 }
 
+int16_t test_vaddvq_s16(int16x8_t a) {
+  return vaddvq_s16(a);
+
+  // CIR-LABEL: vaddvq_s16
+  // CIR: cir.llvm.intrinsic "vector.reduce.add" {{%.*}} : (!cir.vector<!s16i x 8>) -> !s16i
+
+  // LLVM-LABEL: @test_vaddvq_s16
+  // LLVM-SAME: (<8 x i16> [[a:%.*]])
+  // LLVM: [[VADDVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> {{.*}})
+  // LLVM: ret i16 [[VADDVQ_S16_I]]
+
+  // OGCG-LABEL: @test_vaddvq_s16
+  // OGCG: {{%.*}} = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> {{%.*}})
+  // OGCG: ret i16
+}
+
 
 int32_t test_vaddv_s32(int32x2_t a) {
   return vaddv_s32(a);