Skip to content

Commit 808925d

Browse files
lweiss-fairphonelweiss-fairphone
committed
Add Milos (SM7635 / volcano)
Signed-off-by: Luca Weiss <[email protected]>
1 parent 6444cf9 commit 808925d

File tree

2 files changed

+350
-0
lines changed

2 files changed

+350
-0
lines changed

‎meson.build‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ project('debugcc',
1111

1212
platforms = [
1313
'ipq8064',
14+
'milos',
1415
'msm8936',
1516
'msm8994',
1617
'msm8996',

‎milos.c‎

Lines changed: 349 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,349 @@
1+
// SPDX-License-Identifier: BSD-3-Clause
2+
/* Copyright (c) 2025, Luca Weiss */
3+
4+
#include <sys/mman.h>
5+
#include <err.h>
6+
#include <fcntl.h>
7+
#include <stdio.h>
8+
#include <stdint.h>
9+
#include <stdlib.h>
10+
#include <string.h>
11+
#include <unistd.h>
12+
13+
#include "debugcc.h"
14+
15+
static struct gcc_mux gcc = {
16+
.mux = {
17+
.phys = 0x100000,
18+
.size = 0x1f4200,
19+
20+
.measure = measure_gcc,
21+
22+
.enable_reg = 0x62004,
23+
.enable_mask = BIT(0),
24+
25+
.mux_reg = 0x62024,
26+
.mux_mask = 0x3ff,
27+
28+
.div_reg = 0x62000,
29+
.div_mask = 0xf,
30+
.div_val = 2,
31+
},
32+
33+
.xo_div4_reg = 0x62008,
34+
.debug_ctl_reg = 0x62048,
35+
.debug_status_reg = 0x6204c,
36+
};
37+
38+
static struct debug_mux cam_cc = {
39+
.phys = 0xadb0000,
40+
.size = 0x40000,
41+
.block_name = "cam",
42+
43+
.measure = measure_leaf,
44+
.parent = &gcc.mux,
45+
.parent_mux_val = 0x87,
46+
47+
.enable_reg = 0x26008,
48+
.enable_mask = BIT(0),
49+
50+
.mux_reg = 0x30128,
51+
.mux_mask = 0xff,
52+
53+
.div_reg = 0x26004,
54+
.div_mask = 0xf,
55+
.div_val = 2,
56+
};
57+
58+
static struct debug_mux disp_cc = {
59+
.phys = 0xaf00000,
60+
.size = 0x20000,
61+
.block_name = "disp",
62+
63+
.measure = measure_leaf,
64+
.parent = &gcc.mux,
65+
.parent_mux_val = 0x8c,
66+
67+
.enable_reg = 0xd004,
68+
.enable_mask = BIT(0),
69+
70+
.mux_reg = 0x11000,
71+
.mux_mask = 0x1ff,
72+
73+
.div_reg = 0xd000,
74+
.div_mask = 0xf,
75+
.div_val = 4,
76+
};
77+
78+
static struct debug_mux gpu_cc = {
79+
.phys = 0x3d90000,
80+
.size = 0xa000,
81+
.block_name = "gpu",
82+
83+
.measure = measure_leaf,
84+
.parent = &gcc.mux,
85+
.parent_mux_val = 0x187,
86+
87+
.enable_reg = 0x9274,
88+
.enable_mask = BIT(0),
89+
90+
.mux_reg = 0x9564,
91+
.mux_mask = 0xff,
92+
93+
.div_reg = 0x9270,
94+
.div_mask = 0xf,
95+
.div_val = 2,
96+
};
97+
98+
static struct debug_mux video_cc = {
99+
.phys = 0xaaf0000,
100+
.size = 0x10000,
101+
.block_name = "video",
102+
103+
.measure = measure_leaf,
104+
.parent = &gcc.mux,
105+
.parent_mux_val = 0x95,
106+
107+
.enable_reg = 0x80fc,
108+
.enable_mask = BIT(0),
109+
110+
.mux_reg = 0x9a4c,
111+
.mux_mask = 0x3f,
112+
113+
.div_reg = 0x80f8,
114+
.div_mask = 0xf,
115+
.div_val = 3,
116+
};
117+
118+
static struct measure_clk milos_clocks[] = {
119+
/* GCC entries */
120+
{ "gcc_aggre_noc_pcie_axi_clk", &gcc.mux, 0x4d },
121+
{ "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x4f },
122+
{ "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x4e },
123+
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0xe9 },
124+
{ "gcc_camera_hf_axi_clk", &gcc.mux, 0x83 },
125+
{ "gcc_camera_sf_axi_clk", &gcc.mux, 0x84 },
126+
{ "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc.mux, 0x39 },
127+
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x20 },
128+
{ "gcc_cnoc_pcie_sf_axi_clk", &gcc.mux, 0x19 },
129+
{ "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0x105 },
130+
{ "gcc_ddrss_pcie_sf_qtb_clk", &gcc.mux, 0x106 },
131+
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x8d },
132+
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x8a },
133+
{ "gcc_gp1_clk", &gcc.mux, 0x148 },
134+
{ "gcc_gp2_clk", &gcc.mux, 0x149 },
135+
{ "gcc_gp3_clk", &gcc.mux, 0x14a },
136+
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x18b },
137+
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x18c },
138+
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x188 },
139+
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x18a },
140+
{ "gcc_pcie_0_aux_clk", &gcc.mux, 0x150 },
141+
{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x14f },
142+
{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x14e },
143+
{ "gcc_pcie_0_phy_rchng_clk", &gcc.mux, 0x152 },
144+
{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0x151 },
145+
{ "gcc_pcie_0_pipe_div2_clk", &gcc.mux, 0x153 },
146+
{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x14d },
147+
{ "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0x14c },
148+
{ "gcc_pcie_1_aux_clk", &gcc.mux, 0x1b7 },
149+
{ "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x1b6 },
150+
{ "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x1b5 },
151+
{ "gcc_pcie_1_phy_rchng_clk", &gcc.mux, 0x1b9 },
152+
{ "gcc_pcie_1_pipe_clk", &gcc.mux, 0x1b8 },
153+
{ "gcc_pcie_1_pipe_div2_clk", &gcc.mux, 0x1ba },
154+
{ "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x1b4 },
155+
{ "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x1b3 },
156+
{ "gcc_pcie_rscc_cfg_ahb_clk", &gcc.mux, 0x1a0 },
157+
{ "gcc_pcie_rscc_xo_clk", &gcc.mux, 0x1a1 },
158+
{ "gcc_pdm2_clk", &gcc.mux, 0xda },
159+
{ "gcc_pdm_ahb_clk", &gcc.mux, 0xd8 },
160+
{ "gcc_pdm_xo4_clk", &gcc.mux, 0xd9 },
161+
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x81 },
162+
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x82 },
163+
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x89 },
164+
{ "gcc_qmip_gpu_ahb_clk", &gcc.mux, 0x185 },
165+
{ "gcc_qmip_pcie_ahb_clk", &gcc.mux, 0x14b },
166+
{ "gcc_qmip_video_cv_cpu_ahb_clk", &gcc.mux, 0x92 },
167+
{ "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x8f },
168+
{ "gcc_qmip_video_v_cpu_ahb_clk", &gcc.mux, 0x91 },
169+
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x90 },
170+
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0xc3 },
171+
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0xc2 },
172+
{ "gcc_qupv3_wrap0_qspi_ref_clk", &gcc.mux, 0xcb },
173+
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0xc4 },
174+
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0xc5 },
175+
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0xc6 },
176+
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0xc7 },
177+
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0xc8 },
178+
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0xc9 },
179+
{ "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0xca },
180+
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xcf },
181+
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xce },
182+
{ "gcc_qupv3_wrap1_qspi_ref_clk", &gcc.mux, 0xd7 },
183+
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xd0 },
184+
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xd1 },
185+
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xd2 },
186+
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xd3 },
187+
{ "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xd4 },
188+
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xd5 },
189+
{ "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0xd6 },
190+
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0xc0 },
191+
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0xc1 },
192+
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xcc },
193+
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xcd },
194+
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x1af },
195+
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x1b0 },
196+
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x1b1 },
197+
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0xbe },
198+
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0xbd },
199+
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x157 },
200+
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x156 },
201+
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x15d },
202+
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x15e },
203+
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x159 },
204+
{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x15f },
205+
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x158 },
206+
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x15c },
207+
{ "gcc_usb30_prim_atb_clk", &gcc.mux, 0xb8 },
208+
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0xaf },
209+
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0xb1 },
210+
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0xb0 },
211+
{ "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0xb2 },
212+
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0xb3 },
213+
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0xb4 },
214+
{ "gcc_video_axi0_clk", &gcc.mux, 0x93 },
215+
{ "mc_cc_debug_mux", &gcc.mux, 0x112 },
216+
{ "measure_only_cnoc_clk", &gcc.mux, 0x17 },
217+
{ "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x80 },
218+
{ "measure_only_gcc_camera_hf_xo_clk", &gcc.mux, 0x85 },
219+
{ "measure_only_gcc_camera_sf_xo_clk", &gcc.mux, 0x86 },
220+
{ "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x88 },
221+
{ "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x8b },
222+
{ "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x184 },
223+
{ "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x8e },
224+
{ "measure_only_gcc_video_xo_clk", &gcc.mux, 0x94 },
225+
{ "measure_only_ipa_2x_clk", &gcc.mux, 0x170 },
226+
{ "measure_only_memnoc_clk", &gcc.mux, 0x10a },
227+
{ "measure_only_pcie_0_pipe_clk", &gcc.mux, 0x154 },
228+
{ "measure_only_pcie_1_pipe_clk", &gcc.mux, 0x1bb },
229+
{ "measure_only_snoc_clk", &gcc.mux, 0xb },
230+
{ "measure_only_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x15b },
231+
{ "measure_only_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x161 },
232+
{ "measure_only_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x15a },
233+
{ "measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0xb9 },
234+
/* CAMCC Entries */
235+
{ "cam_cc_bps_ahb_clk", &cam_cc, 0x12 },
236+
{ "cam_cc_bps_areg_clk", &cam_cc, 0x11 },
237+
{ "cam_cc_bps_clk", &cam_cc, 0xe },
238+
{ "cam_cc_camnoc_atb_clk", &cam_cc, 0x3e },
239+
{ "cam_cc_camnoc_axi_hf_clk", &cam_cc, 0x39 },
240+
{ "cam_cc_camnoc_axi_sf_clk", &cam_cc, 0x38 },
241+
{ "cam_cc_camnoc_nrt_axi_clk", &cam_cc, 0x3f },
242+
{ "cam_cc_camnoc_rt_axi_clk", &cam_cc, 0x3c },
243+
{ "cam_cc_cci_0_clk", &cam_cc, 0x35 },
244+
{ "cam_cc_cci_1_clk", &cam_cc, 0x36 },
245+
{ "cam_cc_core_ahb_clk", &cam_cc, 0x42 },
246+
{ "cam_cc_cpas_ahb_clk", &cam_cc, 0x37 },
247+
{ "cam_cc_cre_ahb_clk", &cam_cc, 0x47 },
248+
{ "cam_cc_cre_clk", &cam_cc, 0x46 },
249+
{ "cam_cc_csi0phytimer_clk", &cam_cc, 0x6 },
250+
{ "cam_cc_csi1phytimer_clk", &cam_cc, 0x8 },
251+
{ "cam_cc_csi2phytimer_clk", &cam_cc, 0xa },
252+
{ "cam_cc_csi3phytimer_clk", &cam_cc, 0xc },
253+
{ "cam_cc_csiphy0_clk", &cam_cc, 0x7 },
254+
{ "cam_cc_csiphy1_clk", &cam_cc, 0x9 },
255+
{ "cam_cc_csiphy2_clk", &cam_cc, 0xb },
256+
{ "cam_cc_csiphy3_clk", &cam_cc, 0xd },
257+
{ "cam_cc_icp_atb_clk", &cam_cc, 0x2e },
258+
{ "cam_cc_icp_clk", &cam_cc, 0x32 },
259+
{ "cam_cc_icp_cti_clk", &cam_cc, 0x2f },
260+
{ "cam_cc_icp_ts_clk", &cam_cc, 0x30 },
261+
{ "cam_cc_mclk0_clk", &cam_cc, 0x1 },
262+
{ "cam_cc_mclk1_clk", &cam_cc, 0x2 },
263+
{ "cam_cc_mclk2_clk", &cam_cc, 0x3 },
264+
{ "cam_cc_mclk3_clk", &cam_cc, 0x4 },
265+
{ "cam_cc_mclk4_clk", &cam_cc, 0x5 },
266+
{ "cam_cc_ope_0_ahb_clk", &cam_cc, 0x17 },
267+
{ "cam_cc_ope_0_areg_clk", &cam_cc, 0x16 },
268+
{ "cam_cc_ope_0_clk", &cam_cc, 0x13 },
269+
{ "cam_cc_soc_ahb_clk", &cam_cc, 0x41 },
270+
{ "cam_cc_sys_tmr_clk", &cam_cc, 0x34 },
271+
{ "cam_cc_tfe_0_ahb_clk", &cam_cc, 0x1f },
272+
{ "cam_cc_tfe_0_clk", &cam_cc, 0x18 },
273+
{ "cam_cc_tfe_0_cphy_rx_clk", &cam_cc, 0x1e },
274+
{ "cam_cc_tfe_0_csid_clk", &cam_cc, 0x1b },
275+
{ "cam_cc_tfe_1_ahb_clk", &cam_cc, 0x26 },
276+
{ "cam_cc_tfe_1_clk", &cam_cc, 0x20 },
277+
{ "cam_cc_tfe_1_cphy_rx_clk", &cam_cc, 0x25 },
278+
{ "cam_cc_tfe_1_csid_clk", &cam_cc, 0x23 },
279+
{ "cam_cc_tfe_2_ahb_clk", &cam_cc, 0x2d },
280+
{ "cam_cc_tfe_2_clk", &cam_cc, 0x27 },
281+
{ "cam_cc_tfe_2_cphy_rx_clk", &cam_cc, 0x2c },
282+
{ "cam_cc_tfe_2_csid_clk", &cam_cc, 0x2a },
283+
{ "cam_cc_top_shift_clk", &cam_cc, 0x44 },
284+
{ "measure_only_cam_cc_gdsc_clk", &cam_cc, 0x43 },
285+
{ "measure_only_cam_cc_sleep_clk", &cam_cc, 0x45 },
286+
/* DISPCC Entries */
287+
{ "disp_cc_mdss_accu_clk", &disp_cc, 0x70 },
288+
{ "disp_cc_mdss_ahb1_clk", &disp_cc, 0x5d },
289+
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x5a },
290+
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x24 },
291+
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x25 },
292+
{ "disp_cc_mdss_dptx0_aux_clk", &disp_cc, 0x51 },
293+
{ "disp_cc_mdss_dptx0_crypto_clk", &disp_cc, 0x33 },
294+
{ "disp_cc_mdss_dptx0_link_clk", &disp_cc, 0x30 },
295+
{ "disp_cc_mdss_dptx0_link_intf_clk", &disp_cc, 0x32 },
296+
{ "disp_cc_mdss_dptx0_pixel0_clk", &disp_cc, 0x3c },
297+
{ "disp_cc_mdss_dptx0_pixel1_clk", &disp_cc, 0x3d },
298+
{ "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &disp_cc, 0x31 },
299+
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x17 },
300+
{ "disp_cc_mdss_mdp1_clk", &disp_cc, 0x5b },
301+
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x58 },
302+
{ "disp_cc_mdss_mdp_lut1_clk", &disp_cc, 0x5c },
303+
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x59 },
304+
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x5e },
305+
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0x20 },
306+
{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x5f },
307+
{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x56 },
308+
{ "disp_cc_mdss_vsync1_clk", &disp_cc, 0x55 },
309+
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x50 },
310+
{ "measure_only_disp_cc_sleep_clk", &disp_cc, 0x67 },
311+
{ "measure_only_disp_cc_xo_clk", &disp_cc, 0x57 },
312+
/* GPUCC entries */
313+
{ "gpu_cc_ahb_clk", &gpu_cc, 0x17 },
314+
{ "gpu_cc_cx_accu_shift_clk", &gpu_cc, 0x24 },
315+
{ "gpu_cc_cx_ff_clk", &gpu_cc, 0x20 },
316+
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1d },
317+
{ "gpu_cc_cxo_clk", &gpu_cc, 0x1e },
318+
{ "gpu_cc_dpm_clk", &gpu_cc, 0x25 },
319+
{ "gpu_cc_freq_measure_clk", &gpu_cc, 0xf },
320+
{ "gpu_cc_gx_accu_shift_clk", &gpu_cc, 0x15 },
321+
{ "gpu_cc_gx_acd_ahb_ff_clk", &gpu_cc, 0x13 },
322+
{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x11 },
323+
{ "gpu_cc_gx_rcg_ahb_ff_clk", &gpu_cc, 0x14 },
324+
{ "gpu_cc_hub_aon_clk", &gpu_cc, 0x2a },
325+
{ "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x1f },
326+
{ "gpu_cc_memnoc_gfx_clk", &gpu_cc, 0x21 },
327+
{ "gx_clkctl_debug_mux", &gpu_cc, 0xb },
328+
{ "measure_only_gpu_cc_cb_clk", &gpu_cc, 0x28 },
329+
{ "measure_only_gpu_cc_cxo_aon_clk", &gpu_cc, 0xe },
330+
{ "measure_only_gpu_cc_demet_clk", &gpu_cc, 0x10 },
331+
{ "measure_only_gpu_cc_gx_ahb_ff_clk", &gpu_cc, 0x12 },
332+
{ "measure_only_gpu_cc_rscc_hub_aon_clk", &gpu_cc, 0x29 },
333+
{ "measure_only_gpu_cc_rscc_xo_aon_clk", &gpu_cc, 0xd },
334+
{ "measure_only_gpu_cc_sleep_clk", &gpu_cc, 0x1b },
335+
/* VIDEOCC Entries */
336+
{ "measure_only_video_cc_ahb_clk", &video_cc, 0x5 },
337+
{ "measure_only_video_cc_sleep_clk", &video_cc, 0x9 },
338+
{ "measure_only_video_cc_xo_clk", &video_cc, 0x6 },
339+
{ "video_cc_mvs0_clk", &video_cc, 0x3 },
340+
{ "video_cc_mvs0_shift_clk", &video_cc, 0x7 },
341+
{ "video_cc_mvs0c_clk", &video_cc, 0x1 },
342+
{ "video_cc_mvs0c_shift_clk", &video_cc, 0x8 },
343+
{}
344+
};
345+
346+
struct debugcc_platform milos_debugcc = {
347+
"milos",
348+
milos_clocks,
349+
};

0 commit comments

Comments
 (0)