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WIP Add MSM8974
Signed-off-by: Luca Weiss <[email protected]>
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‎meson.build‎

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@@ -12,6 +12,7 @@ project('debugcc',
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platforms = [
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'ipq8064',
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'msm8936',
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'msm8974',
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'msm8994',
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'msm8996',
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'msm8998',

‎msm8974.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Linaro Ltd.
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* Copyright (c) 2025, Luca Weiss
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*/
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#include <sys/mman.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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static struct gcc_mux gcc = {
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.mux = {
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.phys = 0xfc400000,
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.size = 0x4000,
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.measure = measure_gcc,
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.enable_reg = 0x1880,
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.enable_mask = BIT(16),
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.mux_reg = 0x1880,
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.mux_mask = 0x1ff,
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.div_reg = 0x1880,
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.div_mask = 0xf000,
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.div_val = 2, // FIXME
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},
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.xo_div4_reg = 0x10c8,
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.debug_ctl_reg = 0x1884,
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.debug_status_reg = 0x1888,
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};
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static struct debug_mux mmss = { // FIXME
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.phys = 0xfd8c0000,
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.size = 0x40000,
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.block_name = "mmss",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x6a, // FIXME
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.enable_reg = 0x14008, // FIXME
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.enable_mask = BIT(0), // FIXME
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.mux_reg = 0x16000, // FIXME
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.mux_mask = 0xff, // FIXME
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};
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static struct debug_mux lpass = { // FIXME
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.phys = 0xfe000000,
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.size = 0x40000,
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.block_name = "lpass",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x6f, // FIXME
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.enable_reg = 0xd004, // FIXME
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.enable_mask = BIT(0), // FIXME
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.mux_reg = 0x11000, // FIXME
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.mux_mask = 0x1ff, // FIXME
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};
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// static struct debug_mux apcs = { // FIXME
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// .phys = 0xf9011000,
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// .size = 0x1000,
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// .block_name = "apcs",
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//
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// .measure = measure_leaf,
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// .parent = &gcc.mux,
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// .parent_mux_val = 0x18d, // FIXME
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//
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// .enable_reg = 0x9274, // FIXME
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// .enable_mask = BIT(0), // FIXME
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//
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// .mux_reg = 0x9564, // FIXME
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// .mux_mask = 0xff, // FIXME
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// };
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static struct measure_clk msm8974_clocks[] = {
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/* GCC entries */
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{ "gcc_pdm_ahb_clk", &gcc.mux, 0x00d0 },
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{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0x00ab },
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{ "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0x00b3 },
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{ "gcc_blsp2_uart5_apps_clk", &gcc.mux, 0x00be },
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{ "gcc_usb30_master_clk", &gcc.mux, 0x0050 },
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{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0x00b4 },
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{ "gcc_usb_hsic_system_clk", &gcc.mux, 0x0059 },
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{ "gcc_sdcc1_cdccal_sleep_clk", &gcc.mux, 0x006a },
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{ "gcc_sdcc1_cdccal_ff_clk", &gcc.mux, 0x006b },
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{ "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0x00b5 },
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{ "gcc_usb_hsic_io_cal_clk", &gcc.mux, 0x005b },
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{ "gcc_ce2_axi_clk", &gcc.mux, 0x0141 },
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{ "gcc_sdcc3_ahb_clk", &gcc.mux, 0x0079 },
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{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x009d },
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{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x008a },
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{ "gcc_blsp2_uart4_apps_clk", &gcc.mux, 0x00ba },
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{ "gcc_ce2_clk", &gcc.mux, 0x0140 },
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{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x0091 },
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{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x0069 },
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{ "gcc_mss_cfg_ahb_clk", &gcc.mux, 0x0030 },
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{ "gcc_tsif_ahb_clk", &gcc.mux, 0x00e8 },
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{ "gcc_sdcc4_ahb_clk", &gcc.mux, 0x0081 },
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{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x0098 },
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{ "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0x00b8 },
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{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x0093 },
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{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0x00a2 },
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{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0x00c2 },
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{ "gcc_bam_dma_ahb_clk", &gcc.mux, 0x00e0 },
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{ "gcc_sdcc3_apps_clk", &gcc.mux, 0x0078 },
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{ "gcc_usb_hs_system_clk", &gcc.mux, 0x0060 },
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{ "gcc_blsp1_ahb_clk", &gcc.mux, 0x0088 },
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{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x0068 },
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{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0x00bd },
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{ "gcc_blsp1_uart4_apps_clk", &gcc.mux, 0x009a },
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{ "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0x00ae },
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{ "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0x00c1 },
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{ "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0x00b1 },
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{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x008e },
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{ "gcc_usb_hsic_ahb_clk", &gcc.mux, 0x0058 },
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{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x0095 },
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{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x0052 },
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{ "gcc_ce1_axi_clk", &gcc.mux, 0x0139 },
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{ "gcc_sdcc4_apps_clk", &gcc.mux, 0x0080 },
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{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x009c },
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{ "gcc_usb_hs_ahb_clk", &gcc.mux, 0x0061 },
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{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0x00a1 },
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{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0x00b0 },
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{ "gcc_prng_ahb_clk", &gcc.mux, 0x00d8 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x0094 },
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{ "gcc_usb_hsic_clk", &gcc.mux, 0x005a },
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{ "gcc_blsp1_uart6_apps_clk", &gcc.mux, 0x00a3 },
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{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x0070 },
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{ "gcc_tsif_ref_clk", &gcc.mux, 0x00e9 },
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{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x008c },
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{ "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0x00bc },
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{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x0099 },
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{ "gcc_mmss_noc_cfg_ahb_clk", &gcc.mux, 0x002a },
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{ "gcc_blsp2_ahb_clk", &gcc.mux, 0x00a8 },
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{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x00f8 },
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{ "gcc_ce1_ahb_clk", &gcc.mux, 0x013a },
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{ "gcc_pdm2_clk", &gcc.mux, 0x00d2 },
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{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0x00b9 },
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{ "gcc_ce2_ahb_clk", &gcc.mux, 0x0142 },
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{ "gcc_blsp1_uart5_apps_clk", &gcc.mux, 0x009e },
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{ "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0x00aa },
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{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x0090 },
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{ "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0x00ac },
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{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x008b },
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{ "gcc_blsp2_uart6_apps_clk", &gcc.mux, 0x00c3 },
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{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x0071 },
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{ "gcc_usb30_sleep_clk", &gcc.mux, 0x0051 },
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{ "gcc_usb2a_phy_sleep_clk", &gcc.mux, 0x0063 },
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{ "gcc_usb2b_phy_sleep_clk", &gcc.mux, 0x0064 },
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{ "gcc_sys_noc_usb3_axi_clk", &gcc.mux, 0x0001 },
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{ "gcc_ocmem_noc_cfg_ahb_clk", &gcc.mux, 0x0029 },
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{ "gcc_ce1_clk", &gcc.mux, 0x0138 },
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{ "gcc_lpass_q6_axi_clk", &gcc.mux, 0x0160 },
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{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x0031 },
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{ "cnoc_clk", &gcc.mux, 0x0008 },
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{ "pnoc_clk", &gcc.mux, 0x0010 },
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{ "snoc_clk", &gcc.mux, 0x0000 },
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{ "bimc_clk", &gcc.mux, 0x0155 },
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{ "wcnss_m_clk", &gcc.mux, 0x0198 },
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/* MMSS entries */
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{ "mmss_mmssnoc_axi_clk", &mmss, 0x0004 },
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{ "ocmemnoc_clk", &mmss, 0x0007 },
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{ "ocmemcx_ocmemnoc_clk", &mmss, 0x0009 },
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{ "camss_cci_cci_ahb_clk", &mmss, 0x002e },
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{ "camss_cci_cci_clk", &mmss, 0x002d },
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{ "camss_csi0_ahb_clk", &mmss, 0x0042 },
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{ "camss_csi0_clk", &mmss, 0x0041 },
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{ "camss_csi0phy_clk", &mmss, 0x0043 },
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{ "camss_csi0pix_clk", &mmss, 0x0045 },
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{ "camss_csi0rdi_clk", &mmss, 0x0044 },
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{ "camss_csi1_ahb_clk", &mmss, 0x0047 },
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{ "camss_csi1_clk", &mmss, 0x0046 },
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{ "camss_csi1phy_clk", &mmss, 0x0048 },
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{ "camss_csi1pix_clk", &mmss, 0x004a },
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{ "camss_csi1rdi_clk", &mmss, 0x0049 },
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{ "camss_csi2_ahb_clk", &mmss, 0x004c },
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{ "camss_csi2_clk", &mmss, 0x004b },
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{ "camss_csi2phy_clk", &mmss, 0x004d },
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{ "camss_csi2pix_clk", &mmss, 0x004f },
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{ "camss_csi2rdi_clk", &mmss, 0x004e },
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{ "camss_csi3_ahb_clk", &mmss, 0x0051 },
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{ "camss_csi3_clk", &mmss, 0x0050 },
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{ "camss_csi3phy_clk", &mmss, 0x0052 },
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{ "camss_csi3pix_clk", &mmss, 0x0054 },
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{ "camss_csi3rdi_clk", &mmss, 0x0053 },
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{ "camss_csi_vfe0_clk", &mmss, 0x003f },
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{ "camss_csi_vfe1_clk", &mmss, 0x0040 },
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{ "camss_gp0_clk", &mmss, 0x0027 },
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{ "camss_gp1_clk", &mmss, 0x0028 },
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{ "camss_ispif_ahb_clk", &mmss, 0x0055 },
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{ "camss_jpeg_jpeg0_clk", &mmss, 0x0032 },
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{ "camss_jpeg_jpeg1_clk", &mmss, 0x0033 },
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{ "camss_jpeg_jpeg2_clk", &mmss, 0x0034 },
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{ "camss_jpeg_jpeg_ahb_clk", &mmss, 0x0035 },
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{ "camss_jpeg_jpeg_axi_clk", &mmss, 0x0036 },
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{ "camss_jpeg_jpeg_ocmemnoc_clk", &mmss, 0x0037 },
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{ "camss_mclk0_clk", &mmss, 0x0029 },
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{ "camss_mclk1_clk", &mmss, 0x002a },
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{ "camss_mclk2_clk", &mmss, 0x002b },
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{ "camss_mclk3_clk", &mmss, 0x002c },
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{ "camss_micro_ahb_clk", &mmss, 0x0026 },
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{ "camss_phy0_csi0phytimer_clk", &mmss, 0x002f },
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{ "camss_phy1_csi1phytimer_clk", &mmss, 0x0030 },
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{ "camss_phy2_csi2phytimer_clk", &mmss, 0x0031 },
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{ "camss_top_ahb_clk", &mmss, 0x0025 },
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{ "camss_vfe_cpp_ahb_clk", &mmss, 0x003b },
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{ "camss_vfe_cpp_clk", &mmss, 0x003a },
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{ "camss_vfe_vfe0_clk", &mmss, 0x0038 },
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{ "camss_vfe_vfe1_clk", &mmss, 0x0039 },
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{ "camss_vfe_vfe_ahb_clk", &mmss, 0x003c },
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{ "camss_vfe_vfe_axi_clk", &mmss, 0x003d },
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{ "camss_vfe_vfe_ocmemnoc_clk", &mmss, 0x003e },
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{ "oxilicx_axi_clk", &mmss, 0x000b },
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{ "oxilicx_ahb_clk", &mmss, 0x000c },
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{ "ocmemcx_ocmemnoc_clk", &mmss, 0x0009 },
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{ "oxili_gfx3d_clk", &mmss, 0x000d },
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{ "venus0_axi_clk", &mmss, 0x000f },
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{ "venus0_ocmemnoc_clk", &mmss, 0x0010 },
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{ "venus0_ahb_clk", &mmss, 0x0011 },
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{ "venus0_vcodec0_clk", &mmss, 0x000e },
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{ "mmss_s0_axi_clk", &mmss, 0x0005 },
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{ "mmssnoc_ahb_clk", &mmss, 0x0001 },
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{ "mdss_ahb_clk", &mmss, 0x0022 },
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{ "mdss_hdmi_clk", &mmss, 0x001d },
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{ "mdss_mdp_clk", &mmss, 0x0014 },
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{ "mdss_mdp_lut_clk", &mmss, 0x0015 },
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{ "mdss_axi_clk", &mmss, 0x0024 },
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{ "mdss_vsync_clk", &mmss, 0x001c },
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{ "mdss_esc0_clk", &mmss, 0x0020 },
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{ "mdss_esc1_clk", &mmss, 0x0021 },
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{ "mdss_edpaux_clk", &mmss, 0x001b },
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{ "mdss_byte0_clk", &mmss, 0x001e },
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{ "mdss_byte1_clk", &mmss, 0x001f },
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{ "mdss_edplink_clk", &mmss, 0x001a },
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{ "mdss_edppixel_clk", &mmss, 0x0019 },
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{ "mdss_extpclk_clk", &mmss, 0x0018 },
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{ "mdss_hdmi_ahb_clk", &mmss, 0x0023 },
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{ "mdss_pclk0_clk", &mmss, 0x0016 },
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{ "mdss_pclk1_clk", &mmss, 0x0017 },
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/* LPASS entries */
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{ "q6ss_xo_clk", &lpass, 0x002b },
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{ "q6ss_ahb_lfabif_clk", &lpass, 0x001e },
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{ "q6ss_ahbm_clk", &lpass, 0x001d },
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/* APCS entries */
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// { "krait0_m_clk", &apcs, 0x00 },
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// { "krait1_m_clk", &apcs, 0x01 },
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// { "krait2_m_clk", &apcs, 0x02 },
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// { "krait3_m_clk", &apcs, 0x03 },
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// { "l2_m_clk", &apcs, 0x04 },
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{}
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};
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struct debugcc_platform msm8974_debugcc = {
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"msm8974",
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msm8974_clocks,
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};

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