chryse-to-niar: init.

Author: kivikakk

.gitignore

@@ -1,16 +1,7 @@
-build/
+__pycache__
+/build
 *.vcd
+
 .zig-cache/
 zig-out/
 rom.bin
-
-target/
-test_run_dir/
-
-.cache/
-.metals/
-.bloop/
-.bsp/
-metals.sbt
-
-.DS_Store

.scalafmt.conf

@@ -1,6 +1,12 @@
 {
-    "files.watcherExclude": {
-        "**/target": true
-    },
     "editor.formatOnSave": true,
+    "[python]": {
+        "editor.codeActionsOnSave": {
+            "source.organizeImports": "explicit"
+        }
+    },
+    "python.analysis.autoImportCompletions": true,
+    "python.analysis.diagnosticSeverityOverrides": {
+        "reportGeneralTypeIssues": "none"
+    }
 }

.vscode/settings.json

@@ -0,0 +1,13 @@
+import niar
+
+from . import rtl
+from .targets import cxxrtl, icebreaker, ulx3s
+
+__all__ = ["ILI9341SPI"]
+
+
+class ILI9341SPI(niar.Project):
+    name = "ili9341spi"
+    top = rtl.Top
+    targets = [icebreaker, ulx3s]
+    cxxrtl_targets = [cxxrtl]

build.sbt

@@ -0,0 +1,3 @@
+from . import ILI9341SPI
+
+ILI9341SPI().main()

ili9341spi/__init__.py

@@ -0,0 +1,119 @@
+from amaranth import Module, Signal
+from amaranth.build import Attrs, Pins, PinsN, Resource, Subsignal
+from amaranth.lib import wiring
+from amaranth.lib.cdc import FFSynchronizer
+from amaranth.lib.wiring import In, Out
+from amaranth_stdio.serial import AsyncSerial
+
+from ..targets import cxxrtl, icebreaker, ulx3s
+from .lcd import Lcd
+
+__all__ = ["Top"]
+
+
+icebreaker_spi_lcd = Resource(
+    "spi_lcd",
+    0,
+    Subsignal(
+        "clk", Pins("3", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+    Subsignal(
+        "copi", Pins("4", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+    Subsignal(
+        "res", PinsN("7", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+    Subsignal(
+        "dc", PinsN("8", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+    Subsignal(
+        "blk", Pins("9", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+    Subsignal(
+        "cipo", Pins("10", dir="i", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
+    ),
+)
+
+
+class Top(wiring.Component):
+    def __init__(self, platform):
+        if isinstance(platform, cxxrtl):
+            super().__init__(
+                {
+                    "lcd": Out(Lcd.PinSignature),
+                    "lcd_res": Out(1),
+                    "uart_rx": In(1),
+                    "uart_tx": Out(1),
+                }
+            )
+        else:
+            super().__init__({})
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules.serial = serial = AsyncSerial(
+            divisor=int(platform.default_clk_frequency // 115_200)
+        )
+
+        res = Signal(init=0)
+        blk = Signal(init=1)
+
+        ili = wiring.flipped(Lcd.PinSignature.create())
+
+        m.submodules.lcd = lcd = Lcd()
+        wiring.connect(m, lcd.pins, ili)
+
+        match platform:
+            case icebreaker():
+                platform.add_resources([icebreaker_spi_lcd])
+                plat_spi = platform.request("spi_lcd")
+                m.d.comb += [
+                    plat_spi.clk.o.eq(ili.clk),
+                    plat_spi.copi.o.eq(ili.copi),
+                    plat_spi.res.o.eq(res),
+                    plat_spi.dc.o.eq(ili.dc),
+                    plat_spi.blk.o.eq(blk),
+                    ili.cipo.eq(plat_spi.cipo.i),
+                ]
+
+                plat_uart = platform.request("uart")
+                m.d.comb += plat_uart.tx.o.eq(serial.tx.o)
+                m.submodules += FFSynchronizer(plat_uart.rx.i, serial.rx.i, init=1)
+
+            case ulx3s():
+                plat_uart = platform.request("uart")
+                m.d.comb += plat_uart.tx.o.eq(serial.tx.o)
+                m.submodules += FFSynchronizer(plat_uart.rx.i, serial.rx.i, init=1)
+
+            case cxxrtl():
+                m.d.comb += self.uart_tx.eq(serial.tx.o)
+                m.d.comb += serial.rx.i.eq(self.uart_rx)
+                wiring.connect(m, self.lcd, ili)
+                m.d.comb += self.lcd_res.eq(res)
+
+        return m
+
+
+class Blinker(wiring.Component):
+    ledr: Out(1)
+    ledg: Out(1)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += self.ledg.eq(1)
+
+        timer_top = (int(platform.default_clk_frequency) // 2) - 1
+        timer_half = (int(platform.default_clk_frequency) // 4) - 1
+        timer_reg = Signal(range(timer_top), init=timer_half)
+
+        with m.If(timer_reg == 0):
+            m.d.sync += [
+                self.ledr.eq(~self.ledr),
+                timer_reg.eq(timer_top),
+            ]
+        with m.Else():
+            m.d.sync += timer_reg.eq(timer_reg - 1)
+
+        return m

ili9341spi/__main__.py

@@ -0,0 +1,102 @@
+from amaranth import Cat, Module, Signal
+from amaranth.lib import data, stream, wiring
+from amaranth.lib.wiring import In, Out
+
+__all__ = ["Lcd"]
+
+
+class Lcd(wiring.Component):
+    PinSignature = wiring.Signature(
+        {
+            "clk": Out(1),
+            "copi": Out(1),
+            "dc": Out(1),
+            "cipo": In(1),
+        }
+    )
+
+    class Request(data.Struct):
+        data: 8
+        dc: 1
+        resp_len: 4
+
+    CommandSignature = wiring.Signature(
+        {
+            "req": In(stream.Signature(Request)),
+            "resp": Out(stream.Signature(8)),
+        }
+    )
+
+    pins: Out(PinSignature)
+    command: Out(CommandSignature)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += self.pins.clk.eq(0)
+
+        sr = Signal(8)
+        with m.If(self.pins.clk):
+            m.d.sync += sr.eq(Cat(self.pins.cipo, sr[:7]))
+        m.d.comb += self.pins.copi.eq(sr[7])
+
+        self.command.req.nodeq(m)
+        self.command.resp.noenq(m)
+
+        bit_rem = Signal(3)
+        rcv_byte_rem = Signal(4)
+
+        with m.FSM():
+            with m.State("idle"):
+                payload = self.command.req.deq(m)
+                with m.If(self.command.req.fire):
+                    m.d.sync += [
+                        sr.eq(payload.data),
+                        self.pins.dc.eq(payload.dc),
+                        bit_rem.eq(7),
+                        rcv_byte_rem.eq(payload.resp_len),
+                    ]
+                    m.next = "snd_low"
+
+            with m.State("snd_low"):
+                m.next = "snd_high"
+
+            with m.State("snd_high"):
+                m.d.comb += self.pins.clk.eq(1)
+                m.d.sync += bit_rem.eq(bit_rem - 1)
+                m.next = "snd_low"
+
+                with m.If(bit_rem == 0):
+                    m.d.sync += [
+                        bit_rem.eq(7),
+                        rcv_byte_rem.eq(rcv_byte_rem - 1),
+                        self.pins.dc.eq(0),
+                    ]
+                    with m.If(rcv_byte_rem == 0):
+                        m.next = "idle"
+                    with m.Else():
+                        m.next = "rcv_low"
+
+            with m.State("rcv_low"):
+                m.next = "rcv_high"
+
+            with m.State("rcv_high"):
+                m.d.comb += self.pins.clk.eq(1)
+                m.d.sync += bit_rem.eq(bit_rem - 1)
+                m.next = "rcv_low"
+
+                with m.If(bit_rem == 0):
+                    m.d.sync += bit_rem.eq(7)
+                    m.next = "rcv_done"
+
+            with m.State("rcv_done"):
+                # no backpressure, oops.
+                self.command.resp.enq(m, sr)
+                m.d.sync += rcv_byte_rem.eq(rcv_byte_rem - 1)
+
+                with m.If(rcv_byte_rem == 0):
+                    m.next = "idle"
+                with m.Else():
+                    m.next = "rcv_high"
+
+        return m

ili9341spi/rtl/__init__.py

@@ -0,0 +1,17 @@
+import niar
+from amaranth_boards.icebreaker import ICEBreakerPlatform
+from amaranth_boards.ulx3s import ULX3S_45F_Platform
+
+__all__ = ["icebreaker", "ulx3s", "cxxrtl"]
+
+
+class icebreaker(ICEBreakerPlatform):
+    pass
+
+
+class ulx3s(ULX3S_45F_Platform):
+    pass
+
+
+class cxxrtl(niar.CxxrtlPlatform):
+    default_clk_frequency = 1_000_000.0

ili9341spi/rtl/lcd.py

@@ -0,0 +1,17 @@
+[project]
+name = "ili9341spi"
+version = "0.0"
+description = ""
+authors = [{ name = "Asherah Connor", email = "[email protected]" }]
+dependencies = [
+    "amaranth >= 0.5, < 0.7",
+    "amaranth-boards",
+    "amaranth-stdio",
+    "niar >= 0.1",
+]
+requires-python = ">=3.8"
+license = { text = "BSD-2-Clause" }
+
+[build-system]
+requires = ["pdm-backend"]
+build-backend = "pdm.backend"