Verilog Matrix Multiplier

Final Project for Digital Systems Design Course, Fall 2020

Sharif University of Technology

Computer Engineering Department

Contributors

• Ahmad Salimi
• Kimia Noorbakhsh
• Saee Saadat
• Alireza Hosseinpour

Running simulation on a module

vlog -work work ./src/*.v
vsim -gui work.<testbench> -voptargs=+acc

python3 <model.py address> <input_a address> <input_b address> <simout.b address> <m> <n> <m>

License

MIT License, Copyright (c) 2021 Kimia Noorbakhsh (and the gang!)