README.md

⚠️ This headstage has moved to a dedicated repository: https://github.com/open-ephys/onix-fmc-host. This folder should be considered archived.

FMC Host Board

This card serves as host interface for serialized headstages and miniscopes, as well as general purpose analog and digital IO. This board is a VITA-57.1 compliant module that uses high pin-count FMC connector. In combination with a base FPGA board (e.g. Numato Lab Nereid, it provides host PC communication for the following:

• Two deserailizers for any multifunction headstage conforming to our serialization protocol
• 12x 16-bit, +/-10V analog outputs or inputs. Direction selected via analog switch controllable over the FMC connector. Analog inputs are separated into 2 simultaneously sampled 6-channel banks. When analog outputs are used, they are are always looped back using the analog inputs.
• 3x high speed LVDS input pairs
• 2x high speed LVDS outputs pairs
• 2x high speed, arbitrary logic-level, singled-ended lock inputs
• 1x high speed single ended, 50 ohm clock output
• 4x MLVDS input or output trigger lines

Easy access to IO is provided by the breakout board.

Gerber Files

{% include gerber_layers.md %}

Bill of Materials

The bill of materials for this device can be found here.

Manufacturing Requirements

In order to meet approximately correct trace impedances, the design assumes the following stackup:

1. Top Copper 0.035 mm
2. Prepreg (2313*1) 0.1 mm
3. Inner Copper 0.0175 mm
4. Core (Copper) 0.565 mm
5. Inner Copper 0.0175 mm
6. Prepeg (2116*1) 0.127 mm
7. Inner Copper 0.0175 mm
8. Core (Copper) 0.565 mm
9. Inner Copper 0.0175 mm
10. Prepreg (2313*1) 0.1 mm
11. Bottom Copper 0.0175 mm