Skip to content

Commit b7ecd17

Browse files
committed
Expand README.md
1 parent 4cd42db commit b7ecd17

File tree

1 file changed

+2
-2
lines changed

1 file changed

+2
-2
lines changed

README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
## verilog_spi - A simple verilog implementation of the SPI protocol.
1+
# verilog_spi - A simple verilog implementation of the SPI protocol.
22

33
I wanted to learn verilog, so I created an own SPI implementation.
44

@@ -19,7 +19,7 @@ Tested on Lattice ICE40UP5k.
1919
Makefile builds bitstream for WebFPGA with yosys, nextpnr, icepack and compress-bitstream (from WebFPGA toolchain).
2020
Extremely easy to modify for other FPGAs.
2121

22-
# Usage:
22+
## Usage:
2323

2424
Include these files in your own project:
2525
* spi_module.v

0 commit comments

Comments
 (0)