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add initial J1b support for ULX3S board
This patch adds initial J1b support for the ULX3S board, which is based on the Lattice ECP5 FPGA and can be programmed with either the Trellis (Yosys) or Diamond (vendor) toolchain. Currently only the J1b core and UART are hooked up. So no LEDs, GPIO ports, buttons, SDRAM, etc.. support yet. You can connect to the core with the `shell.py` script, and you can replicate the bootstap process: compiling swapforth.fs, writing out a new nuc.hex file containing the new words and creating a new bitstream containing the new `.hex` file. Flashing that on the ULX3S seems to replicate a functioning Forth system. The `bram` and `ram16k` modules were split out from the `xilinx-top.v` file into `ram.v` to foster some code reuse. Thanks to improved handling of bram within Yosys, the modules could be reused as is. Note that the changes weren't tested on either the Diamond or Xilinx toolchains. The changes to Xilinx parts were minimal so hopefully no regression was introduced. As for Diamond, it made sense to me to include the Makefile-related parts needed to compile for Diamond to aid others wanting to make this work.
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‎j1b/ulx3s/Makefile

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# ******* project, board and chip name *******
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PROJECT = swapforth
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BOARD = ulx3s
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# 12 25 45 85
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FPGA_SIZE = 85
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# ******* design files *******
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CONSTRAINTS = ulx3s_v20_segpdi.lpf
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TOP_MODULE = ulx3s_top
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PREFIX = ../verilog
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TOP_MODULE_FILE = $(PREFIX)/$(TOP_MODULE).v
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VERILOG_FILES = \
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$(TOP_MODULE_FILE) \
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$(PREFIX)/j1.v \
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$(PREFIX)/ram.v \
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$(PREFIX)/uart.v \
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$(PREFIX)/stack.v \
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# *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting)
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VHDL_FILES = \
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YOSYS_OPTIONS = -abc9
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NEXTPNR_OPTIONS = --timing-allow-fail
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SCRIPTS = scripts
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include $(SCRIPTS)/trellis_path.mk
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include $(SCRIPTS)/trellis_main.mk

‎j1b/ulx3s/README.md

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The ULX3S board is based upon the Lattice ECP5 FPGA. It's a it's a prototype
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board with lots of features in a small form factor. For more info, see
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https://ulx3s.github.io.
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Currently the only tested toolchain is Trellis (or rather the tools associated
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with Trellis).
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As with the other supported platforms, have the Trellis tools installed, and run
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make in this directory to create a bitstream. Run fujprog to install it over
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USB:
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fujprog ulx3s_85f_swapforth.bit
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Now you can use `shell.py` in the parent directory to attach to the Forth
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process over UART. The Verilator bootstrap process will also work for ULX3S.
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Currently only J1b itself and UART are supported. Support for low-hanging fruit
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like GPIOs, buttons and LEDs should follow shortly.

‎j1b/ulx3s/makefile.diamond

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# ******* project, board and chip name *******
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PROJECT = swapforth_hex
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BOARD = ulx3s
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# 12 25 45 85
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FPGA_SIZE = 12
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FPGA_PACKAGE = 6bg381c
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# config flash: 1:SPI (standard), 4:QSPI (quad)
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FLASH_SPI = 4
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# chip: is25lp032d is25lp128f s25fl164k
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FLASH_CHIP = is25lp128f
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# ******* design files *******
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CONSTRAINTS = ulx3s_v20_segpdi.lpf
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TOP_MODULE = ulx3s_top
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PREFIX = ../verilog
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TOP_MODULE_FILE = $(PREFIX)/$(TOP_MODULE).v
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VERILOG_FILES = \
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$(TOP_MODULE_FILE) \
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$(PREFIX)/j1.v \
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$(PREFIX)/ram.v \
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$(PREFIX)/uart.v \
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$(PREFIX)/stack.v \
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# *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting)
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VHDL_FILES = \
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SCRIPTS = ../../../../scripts/
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include $(SCRIPTS)/diamond_path.mk
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include $(SCRIPTS)/diamond_main.mk

‎j1b/ulx3s/scripts/diamond_main.mk

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# ******* project, board and chip name *******
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PROJECT ?= project
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BOARD ?= board
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FPGA_SIZE ?= 12
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FPGA_CHIP ?= lfe5u-$(FPGA_SIZE)f
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FPGA_PACKAGE ?= 6bg381c
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# config flash: 1:SPI (standard), 4:QSPI (quad)
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FLASH_SPI ?= 1
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# chip: is25lp032d is25lp128f s25fl164k
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FLASH_CHIP ?= is25lp032d
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# ******* design files *******
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CONSTRAINTS ?= board_constraints.lpf
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STRATEGY ?= $(SCRIPTS)/ulx3s.sty
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TOP_MODULE ?= top
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TOP_MODULE_FILE ?= $(TOP_MODULE).v
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VERILOG_FILES ?= $(TOP_MODULE_FILE)
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VHDL_FILES ?=
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SBX_FILES ?=
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# ******* tools installation paths *******
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# include $(SCRIPTS)/trellis_path.mk
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# https://github.com/ldoolitt/vhd2vl
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#VHDL2VL ?= /mt/scratch/tmp/openfpga/vhd2vl/src/vhd2vl
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# https://github.com/YosysHQ/yosys
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#YOSYS ?= /mt/scratch/tmp/openfpga/yosys/yosys
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# https://github.com/YosysHQ/nextpnr
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#NEXTPNR-ECP5 ?= /mt/scratch/tmp/openfpga/nextpnr/nextpnr-ecp5
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# https://github.com/SymbiFlow/prjtrellis
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#TRELLIS ?= /mt/scratch/tmp/openfpga/prjtrellis
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ifeq ($(FPGA_CHIP), lfe5u-12f)
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CHIP_ID=0x21111043
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MASK_FILE=LFE5U-45F.msk
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endif
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ifeq ($(FPGA_CHIP), lfe5u-25f)
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CHIP_ID=0x41111043
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MASK_FILE=LFE5U-45F.msk
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endif
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ifeq ($(FPGA_CHIP), lfe5u-45f)
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CHIP_ID=0x41112043
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MASK_FILE=LFE5U-45F.msk
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endif
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ifeq ($(FPGA_CHIP), lfe5u-85f)
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CHIP_ID=0x41113043
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MASK_FILE=LFE5U-85F.msk
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endif
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#ifeq ($(FPGA_SIZE), 12)
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# FPGA_K=25
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# IDCODE_CHIPID=--idcode $(CHIP_ID)
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#else
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FPGA_K=$(FPGA_SIZE)
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IDCODE_CHIPID=
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#endif
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FPGA_CHIP_EQUIVALENT ?= lfe5u-$(FPGA_K)f
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# open source synthesis tools
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ECPPLL ?= $(TRELLIS)/libtrellis/ecppll
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ECPPACK ?= $(TRELLIS)/libtrellis/ecppack
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TRELLISDB ?= $(TRELLIS)/database
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LIBTRELLIS ?= $(TRELLIS)/libtrellis
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BIT2SVF ?= $(TRELLIS)/tools/bit_to_svf.py
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#BASECFG ?= $(TRELLIS)/misc/basecfgs/empty_$(FPGA_CHIP_EQUIVALENT).config
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# yosys options, sometimes those can be used: -noccu2 -nomux -nodram
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YOSYS_OPTIONS ?=
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# clock generator
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CLK0_NAME ?= clk0
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CLK0_FILE_NAME ?= clocks/$(CLK0_NAME).v
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CLK0_OPTIONS ?= --input 25 --output 100 --s1 50 --p1 0 --s2 25 --p2 0 --s3 125 --p3 0
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CLK1_NAME ?= clk1
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CLK1_FILE_NAME ?= clocks/$(CLK1_NAME).v
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CLK1_OPTIONS ?= --input 25 --output 100 --s1 50 --p1 0 --s2 25 --p2 0 --s3 125 --p3 0
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CLK2_NAME ?= clk2
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CLK2_FILE_NAME ?= clocks/$(CLK2_NAME).v
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CLK2_OPTIONS ?= --input 25 --output 100 --s1 50 --p1 0 --s2 25 --p2 0 --s3 125 --p3 0
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CLK3_NAME ?= clk3
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CLK3_FILE_NAME ?= clocks/$(CLK3_NAME).v
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CLK3_OPTIONS ?= --input 25 --output 100 --s1 50 --p1 0 --s2 25 --p2 0 --s3 125 --p3 0
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# closed source synthesis tools
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# include $(SCRIPTS)/diamond_path.mk
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#DIAMOND_BASE ?= /usr/local/diamond
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ifneq ($(wildcard $(DIAMOND_BASE)),)
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DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1)
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DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc)
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DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd)
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MASK_PATH := $(shell find ${DIAMOND_BASE}/ -maxdepth 5 -name xpga -type d)/ecp5
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endif
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#PROJ_FILE := $(shell ls *.ldf | head -1)
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#PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4)
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#IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8)
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#IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4)
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# programming tools
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UJPROG ?= fujprog
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OPENFPGALOADER ?= openFPGALoader
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OPENFPGALOADER_OPTIONS ?= --board ulx3s
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FLEAFPGA_JTAG ?= FleaFPGA-JTAG
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OPENOCD ?= openocd
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OPENOCD_INTERFACE ?= $(SCRIPTS)/ft231x.ocd
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DFU_UTIL ?= dfu-util
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TINYFPGASP ?= tinyfpgasp
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# helper scripts directory
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SCRIPTS ?= scripts
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# rest of the include makefile
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FPGA_CHIP_UPPERCASE := $(shell echo $(FPGA_CHIP) | tr '[:lower:]' '[:upper:]')
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FPGA_PACKAGE_UPPERCASE := $(shell echo $(FPGA_PACKAGE) | tr '[:lower:]' '[:upper:]')
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BITSTREAM ?= $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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#BITSTREAM ?= $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme
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all: $(BITSTREAM)
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# VHDL to VERILOG conversion
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#%.v: %.vhd
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# $(VHDL2VL) $< $@
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#*.v: *.vhdl
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# $(VHDL2VL) $< $@
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#$(PROJECT).ys: makefile
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# $(SCRIPTS)/ysgen.sh $(VERILOG_FILES) $(VHDL_TO_VERILOG_FILES) > $@
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# echo "hierarchy -top ${TOP_MODULE}" >> $@
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# echo "synth_ecp5 -noccu2 -nomux -nodram -json ${PROJECT}.json" >> $@
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#$(PROJECT).json: $(PROJECT).ys $(VERILOG_FILES) $(VHDL_TO_VERILOG_FILES)
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# $(YOSYS) $(PROJECT).ys
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$(PROJECT).json: $(VERILOG_FILES) $(VHDL_TO_VERILOG_FILES)
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$(YOSYS) \
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-p "hierarchy -top ${TOP_MODULE}" \
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-p "synth_ecp5 ${YOSYS_OPTIONS} -json ${PROJECT}.json" \
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$(VERILOG_FILES) $(VHDL_TO_VERILOG_FILES)
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).config: $(PROJECT).json $(BASECFG)
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$(NEXTPNR-ECP5) --$(FPGA_K)k --json $(PROJECT).json --lpf $(CONSTRAINTS) --basecfg $(BASECFG) --textcfg $@
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#$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).config
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# LANG=C LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPACK) $(IDCODE_CHIPID) --db $(TRELLISDB) --input $< --bit $@
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# generate LDF project file for diamond
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).ldf: $(SCRIPTS)/project.ldf $(SCRIPTS)/ldf.xsl $(SCRIPTS)/$(BOARD)_sram.xcf
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xsltproc \
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--stringparam FPGA_DEVICE $(FPGA_CHIP_UPPERCASE)-$(FPGA_PACKAGE_UPPERCASE) \
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--stringparam CONSTRAINTS_FILE $(CONSTRAINTS) \
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--stringparam STRATEGY_FILE $(STRATEGY) \
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--stringparam XCF_FILE $(SCRIPTS)/$(BOARD)_sram.xcf \
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--stringparam TOP_MODULE $(TOP_MODULE) \
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--stringparam TOP_MODULE_FILE $(TOP_MODULE_FILE) \
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--stringparam VHDL_FILES "$(VHDL_FILES)" \
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--stringparam VERILOG_FILES "$(VERILOG_FILES)" \
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--stringparam SBX_FILES "$(SBX_FILES)" \
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$(SCRIPTS)/ldf.xsl $(SCRIPTS)/project.ldf > $@
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project/project_project.bit: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).ldf $(VERILOG_FILES) $(VHDL_FILES)
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echo prj_project open $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).ldf \; prj_run Export -task Bitgen | ${DIAMONDC}
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit: project/project_project.bit
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ln -sf project/project_project.bit $@
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$(CLK0_FILE_NAME):
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LANG=C LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPLL) $(CLK0_OPTIONS) --file $@
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$(CLK1_FILE_NAME):
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LANG=C LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPLL) $(CLK1_OPTIONS) --file $@
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$(CLK2_FILE_NAME):
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LANG=C LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPLL) $(CLK2_OPTIONS) --file $@
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$(CLK3_FILE_NAME):
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LANG=C LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPLL) $(CLK3_OPTIONS) --file $@
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# generate sram programming XCF file for DDTCMD
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$(BOARD)_$(FPGA_SIZE)f.xcf: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit $(SCRIPTS)/$(BOARD)_sram.xcf $(SCRIPTS)/xcf.xsl
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xsltproc \
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--stringparam FPGA_CHIP $(FPGA_CHIP_UPPERCASE) \
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--stringparam CHIP_ID $(CHIP_ID) \
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--stringparam BITSTREAM_FILE $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \
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$(SCRIPTS)/xcf.xsl $(SCRIPTS)/$(BOARD)_sram.xcf > $@
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# run DDTCMD to generate sram VME file
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme: $(BOARD)_$(FPGA_SIZE)f.xcf $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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LANG=C ${DDTCMD} -oft -fullvme -if $(BOARD)_$(FPGA_SIZE)f.xcf -nocompress -noheader -of $@
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# run DDTCMD to generate SVF file
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf: $(BOARD)_$(FPGA_SIZE)f.xcf $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if $(BOARD)_$(FPGA_SIZE)f.xcf -of $@
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# run DDTCMD to generate flash MCS file
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash.mcs: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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LANG=C ${DDTCMD} -dev $(FPGA_CHIP_UPPERCASE) \
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-if $< -oft -int -quad $(FPGA_SPI) -of $@
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# generate flash programming XCF file for DDTCMD
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$(BOARD)_$(FPGA_SIZE)f_flash_$(FLASH_CHIP).xcf: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit $(SCRIPTS)/$(BOARD)_flash_$(FLASH_CHIP).xcf $(SCRIPTS)/xcf.xsl
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xsltproc \
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--stringparam FPGA_CHIP $(FPGA_CHIP_UPPERCASE) \
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--stringparam CHIP_ID $(CHIP_ID) \
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--stringparam MASK_FILE $(MASK_PATH)/$(MASK_FILE) \
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--stringparam BITSTREAM_FILE $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash.mcs \
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$(SCRIPTS)/xcf.xsl $(SCRIPTS)/$(BOARD)_flash_$(FLASH_CHIP).xcf > $@
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# run DDTCMD to generate flash VME file
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$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme: $(BOARD)_$(FPGA_SIZE)f_flash_$(FLASH_CHIP).xcf $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash.mcs
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LANG=C ${DDTCMD} -oft -fullvme -if $(BOARD)_$(FPGA_SIZE)f_flash_$(FLASH_CHIP).xcf -nocompress -noheader -of $@
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# generate SVF file by prjtrellis python script
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#$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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# $(BIT2SVF) $< $@
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#$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).config
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# LD_LIBRARY_PATH=$(LIBTRELLIS) $(ECPPACK) $(IDCODE_CHIPID) --db $(TRELLISDB) $< --freq 62.0 --svf-rowsize 8000 --svf $@
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# program SRAM with ujrprog (temporary)
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prog: program
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program: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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$(UJPROG) $<
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# program SRAM with OPENFPGALOADER
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prog_ofl: program_ofl
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program_ofl: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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$(OPENFPGALOADER) $(OPENFPGALOADER_OPTIONS) $<
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# program SRAM with FleaFPGA-JTAG (temporary)
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program_flea: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme
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$(FLEAFPGA_JTAG) $<
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# program FLASH over US1 port with ujprog (permanently)
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flash: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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$(UJPROG) -j flash $<
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# program FLASH uver US1 with FleaFPGA-JTAG (permanent)
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flash_flea: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme
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$(FLEAFPGA_JTAG) $<
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# program FLASH over US2 port with DFU bootloader (permanently)
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flash_dfu: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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$(DFU_UTIL) -a 0 -D $<
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$(DFU_UTIL) -a 0 -e
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# program FLASH over US2 port with tinyfpgasp bootloader (permanently)
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flash_tiny: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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$(TINYFPGASP) -w $<
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# generate chip-specific openocd programming file
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$(BOARD)_$(FPGA_SIZE)f.ocd: $(SCRIPTS)/ecp5-ocd.sh
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$(SCRIPTS)/ecp5-ocd.sh $(CHIP_ID) $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf > $@
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# program SRAM with OPENOCD
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prog_ocd: program_ocd
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program_ocd: $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf $(BOARD)_$(FPGA_SIZE)f.ocd
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$(OPENOCD) --file=$(OPENOCD_INTERFACE) --file=$(BOARD)_$(FPGA_SIZE)f.ocd
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JUNK = *~
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#JUNK += $(PROJECT).ys
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JUNK += $(PROJECT).json
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JUNK += $(VHDL_TO_VERILOG_FILES)
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).config
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).ldf
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf
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JUNK += $(BOARD)_$(FPGA_SIZE)f.xcf
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash.mcs
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JUNK += $(BOARD)_$(FPGA_SIZE)f_flash_$(FLASH_CHIP).xcf
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JUNK += $(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme
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JUNK += $(BOARD)_$(FPGA_SIZE)f.ocd
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JUNK += $(CLK0_FILE_NAME) $(CLK1_FILE_NAME) $(CLK2_FILE_NAME) $(CLK3_FILE_NAME)
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# diamond junk
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JUNK += ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml
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JUNK += dummy_sym.sort project_tcl.html promote.xml .run_manager.ini
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JUNK += generate_core.tcl generate_ngd.tcl msg_file.log
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JUNK_DIR = project
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JUNK_DIR += project_tcr.dir
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clean:
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rm -rf $(JUNK_DIR)
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rm -f $(JUNK)

‎j1b/ulx3s/scripts/diamond_path.mk

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# the path of your diamond installation
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DIAMOND_BASE ?= /usr/local/diamond
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# it is a directory that looks like this:
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# ls /usr/local/diamond
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# 3.7_x64

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