Fix GenISA_Int4VectorPack (clear top 4 input bits)

Original GenISA_Int4VectorPack implementation assumed that upper
4 input bits will always be equal to zero.
Add `and` instructions which will clear upper 4 bits.

Author: fda0

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -21328,21 +21328,20 @@ void EmitPass::emitInt4VectorPack(llvm::GenIntrinsicInst *GII) {
   }
 
   CVariable *immFour = m_currShader->ImmToVariable(4, ISA_TYPE_UB);
+  CVariable *immMask4Bit = m_currShader->ImmToVariable(0b1111, ISA_TYPE_UB);
 
   for (int rowOffset = 0; rowOffset < dstNum; rowOffset += execSize) {
-    CVariable *row0 = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset * 2, execSize);
     CVariable *dst = m_currShader->GetNewAlias(m_destination, ISA_TYPE_UB, rowOffset, execSize);
+    CVariable *row0 = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset * 2, execSize);
+    m_encoder->And(dst, row0, immMask4Bit);
 
     // There is an edge case where we pack <3 x i8> into <2 x i8>.
     // The missing 4th i8 cannot be loaded.
     if (rowOffset * 2 + execSize < cinput->GetNumberElement()) {
       CVariable *row1 = m_currShader->GetNewAlias(cinput, ISA_TYPE_UB, rowOffset * 2 + execSize, execSize);
-      CVariable *shl4 = m_currShader->GetNewVariable(row1, "shl4");
-      m_encoder->Shl(shl4, row1, immFour);
-      m_encoder->Or(dst, row0, shl4);
-    } else {
-      // Due to missing last element pass row0 directly to dst.
-      m_encoder->Copy(dst, row0);
+      CVariable *row1Shl4 = m_currShader->GetNewVariable(row1, "row1Shl4");
+      m_encoder->Shl(row1Shl4, row1, immFour);
+      m_encoder->Or(dst, dst, row1Shl4);
     }
   }
 

IGC/Compiler/tests/EmitVISAPass/emit-int4-vector/pack-3-to-2-uniform.ll

@@ -31,11 +31,10 @@ entry:
   %i1 = insertelement <3 x i8> %i0, i8 %l1, i32 1
   %i2 = insertelement <3 x i8> %i1, i8 %l2, i32 2
 
-  ; CHECK: shl (M1_NM, 1) [[SHIFTED1:[A-z0-9]*]](0,0)<1> [[LOADED:[A-z0-9]*]](0,1)<0;1,0> 0x4:ub
-  ; CHECK: or (M1_NM, 1) [[PACKED:[A-z0-9]*]](0,0)<1> [[LOADED]](0,0)<0;1,0> [[SHIFTED1]](0,0)<0;1,0>
-  ; CHECK-NOT: shl
-  ; CHECK-NOT: or
-  ; CHECK: mov (M1_NM, 1) [[PACKED]](0,1)<1> [[LOADED]](0,2)<0;1,0>
+  ; CHECK: and (M1_NM, 1) [[PACKED:[A-z0-9]+]](0,0)<1> [[LOADED:[A-z0-9]+]](0,0)<0;1,0> 0xf:ub
+  ; CHECK: shl (M1_NM, 1) [[SHIFTED:[A-z0-9]+]](0,0)<1> [[LOADED]](0,1)<0;1,0> 0x4:ub
+  ; CHECK: or (M1_NM, 1) [[PACKED]](0,0)<1> [[PACKED]](0,0)<0;1,0> [[SHIFTED]](0,0)<0;1,0>
+  ; CHECK: and (M1_NM, 1) [[PACKED]](0,1)<1> [[LOADED]](0,2)<0;1,0> 0xf:ub
   %packed = call <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v3i8(<3 x i8> %i2)
 
   ; Store the packed result

IGC/Compiler/tests/EmitVISAPass/emit-int4-vector/pack-4-to-2.ll

@@ -33,10 +33,12 @@ entry:
   %loaded = load i32, i32 addrspace(1)* %srcOffsetted, align 4
   %loadedCast = bitcast i32 %loaded to <4 x i8>
 
-  ; CHECK: shl (M1, 16) [[SHIFTED1:[A-z0-9]*]](0,0)<1> [[LOADED:[A-z0-9]*]](0,16)<1;1,0> 0x4:ub
-  ; CHECK: or (M1, 16) [[PACKED:[A-z0-9]*]](0,0)<1> [[LOADED]](0,0)<1;1,0> [[SHIFTED1]](0,0)<1;1,0>
-  ; CHECK: shl (M1, 16) [[SHIFTED2:[A-z0-9]*]](0,0)<1> [[LOADED]](0,48)<1;1,0> 0x4:ub
-  ; CHECK: or (M1, 16) [[PACKED]](0,16)<1> [[LOADED]](0,32)<1;1,0> [[SHIFTED2]](0,0)<1;1,0>
+  ; CHECK: and (M1, 16) [[PACKED:[A-z0-9]+]](0,0)<1> [[LOADED:[A-z0-9]+]](0,0)<1;1,0> 0xf:ub
+  ; CHECK: shl (M1, 16) [[SHIFTED1:[A-z0-9]+]](0,0)<1> [[LOADED]](0,16)<1;1,0> 0x4:ub
+  ; CHECK: or (M1, 16) [[PACKED]](0,0)<1> [[PACKED]](0,0)<1;1,0> [[SHIFTED1]](0,0)<1;1,0>
+  ; CHECK: and (M1, 16) [[PACKED]](0,16)<1> [[LOADED]](0,32)<1;1,0> 0xf:ub
+  ; CHECK: shl (M1, 16) [[SHIFTED2:[A-z0-9]+]](0,0)<1> [[LOADED]](0,48)<1;1,0> 0x4:ub
+  ; CHECK: or (M1, 16) [[PACKED]](0,16)<1> [[PACKED]](0,16)<1;1,0> [[SHIFTED2]](0,0)<1;1,0>
   %packed = call <2 x i8> @llvm.genx.GenISA.Int4VectorPack.v2i8.v4i8(<4 x i8> %loadedCast)
 
   ; Store the packed result