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opcode.h
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/* OPCODE.H (c) Copyright Jan Jaeger, 2000-2012 */
/* Instruction decoding macros and prototypes */
/* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2012 */
/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2012 */
#ifndef _OPCODE_H
#define _OPCODE_H
#include "hercules.h"
#ifndef _CPU_C_
#ifndef _HENGINE_DLL_
#define CPU_DLL_IMPORT DLL_IMPORT
#else /* _HENGINE_DLL_ */
#define CPU_DLL_IMPORT extern
#endif /* _HENGINE_DLL_ */
#else /* _CPU_C_ */
#define CPU_DLL_IMPORT DLL_EXPORT
#endif /* _CPU_C_ */
#ifndef _OPCODE_C_
#ifndef _HENGINE_DLL_
#define OPC_DLL_IMPORT DLL_IMPORT
#else /* _HENGINE_DLL_ */
#define OPC_DLL_IMPORT extern
#endif /* _HENGINE_DLL_ */
#else /* _OPCODE_C_ */
#define OPC_DLL_IMPORT DLL_EXPORT
#endif /* _OPCODE_C_ */
/* Define the following as DLL_EXPORT from */
/* within files inside the engine which */
/* define instruction functions */
#undef DEF_INST_EXPORT
#define DEF_INST_EXPORT
#if defined(_370)
#define _GEN370(_name) &s370_ ## _name,
#else
#define _GEN370(_name)
#endif
#if defined(_390)
#define _GEN390(_name) &s390_ ## _name,
#else
#define _GEN390(_name)
#endif
#if defined(_900)
#define _GEN900(_name) &z900_ ## _name,
#else
#define _GEN900(_name)
#endif
#define GENx___x___x___ \
{ \
_GEN370(operation_exception) \
_GEN390(operation_exception) \
_GEN900(operation_exception) \
(void*)&disasm_none, \
(void*)&"?????" "\0" "?" \
}
#define GENx370x___x___(_name,_format,_mnemonic) \
{ \
_GEN370(_name) \
_GEN390(operation_exception) \
_GEN900(operation_exception) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx___x390x___(_name,_format,_mnemonic) \
{ \
_GEN370(operation_exception) \
_GEN390(_name) \
_GEN900(operation_exception) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx370x390x___(_name,_format,_mnemonic) \
{ \
_GEN370(_name) \
_GEN390(_name) \
_GEN900(operation_exception) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx___x___x900(_name,_format,_mnemonic) \
{ \
_GEN370(operation_exception) \
_GEN390(operation_exception) \
_GEN900(_name) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx370x___x900(_name,_format,_mnemonic) \
{ \
_GEN370(_name) \
_GEN390(operation_exception) \
_GEN900(_name) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx___x390x900(_name,_format,_mnemonic) \
{ \
_GEN370(operation_exception) \
_GEN390(_name) \
_GEN900(_name) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx370x390x900(_name,_format,_mnemonic) \
{ \
_GEN370(_name) \
_GEN390(_name) \
_GEN900(_name) \
(void*)&disasm_ ## _format, \
(void*)& _mnemonic "\0" #_name \
}
#define GENx37Xx390x___ GENx___x390x___
#define GENx37Xx___x900 GENx___x___x900
#define GENx37Xx390x900 GENx___x390x900
typedef void (ATTR_REGPARM(2) *zz_func) (BYTE inst[], REGS *regs);
#define ILC(_b) ((_b) < 0x40 ? 2 : (_b) < 0xc0 ? 4 : 6)
#define REAL_ILC(_regs) \
(likely(!(_regs)->execflag) ? (_regs)->psw.ilc : (_regs)->exrl ? 6 : 4)
#define DISASM_INSTRUCTION(_inst, p) \
disasm_table((_inst), 0, p)
typedef int (*func) ();
extern int disasm_table (BYTE inst[], char mnemonic[], char *p);
#if defined(OPTION_INSTRUCTION_COUNTING)
#define COUNT_INST(_inst, _regs) \
do { \
int used; \
switch((_inst)[0]) { \
case 0x01: \
used = sysblk.imap01[(_inst)[1]]++; \
break; \
case 0xA4: \
used = sysblk.imapa4[(_inst)[1]]++; \
break; \
case 0xA5: \
used = sysblk.imapa5[(_inst)[1] & 0x0F]++; \
break; \
case 0xA6: \
used = sysblk.imapa6[(_inst)[1]]++; \
break; \
case 0xA7: \
used = sysblk.imapa7[(_inst)[1] & 0x0F]++; \
break; \
case 0xB2: \
used = sysblk.imapb2[(_inst)[1]]++; \
break; \
case 0xB3: \
used = sysblk.imapb3[(_inst)[1]]++; \
break; \
case 0xB9: \
used = sysblk.imapb9[(_inst)[1]]++; \
break; \
case 0xC0: \
used = sysblk.imapc0[(_inst)[1] & 0x0F]++; \
break; \
case 0xC2: /*@Z9*/ \
used = sysblk.imapc2[(_inst)[1] & 0x0F]++; /*@Z9*/ \
break; /*@Z9*/ \
case 0xC4: /*208*/ \
used = sysblk.imapc4[(_inst)[1] & 0x0F]++; /*208*/ \
break; /*208*/ \
case 0xC6: /*208*/ \
used = sysblk.imapc6[(_inst)[1] & 0x0F]++; /*208*/ \
break; /*208*/ \
case 0xC8: \
used = sysblk.imapc8[(_inst)[1] & 0x0F]++; \
break; \
case 0xE3: \
used = sysblk.imape3[(_inst)[5]]++; \
break; \
case 0xE4: \
used = sysblk.imape4[(_inst)[1]]++; \
break; \
case 0xE5: \
used = sysblk.imape5[(_inst)[1]]++; \
break; \
case 0xEB: \
used = sysblk.imapeb[(_inst)[5]]++; \
break; \
case 0xEC: \
used = sysblk.imapec[(_inst)[5]]++; \
break; \
case 0xED: \
used = sysblk.imaped[(_inst)[5]]++; \
break; \
default: \
used = sysblk.imapxx[(_inst)[0]]++; \
} \
if(!used) \
{ \
WRMSG(HHC02292, "I", "First use"); \
ARCH_DEP(display_inst) ((_regs), (_inst)); \
} \
} while(0)
#else
#define COUNT_INST(_inst, _regs)
#endif
#if defined(_FEATURE_SIE)
#define SIE_MODE(_register_context) \
unlikely((_register_context)->sie_mode)
#define SIE_STATE(_register_context) \
((_register_context)->sie_state)
#define SIE_FEATB(_regs, _feat_byte, _feat_name) \
(((_regs)->siebk->SIE_ ## _feat_byte) & (SIE_ ## _feat_byte ## _ ## _feat_name))
#define SIE_STATB(_regs, _feat_byte, _feat_name) \
(SIE_MODE((_regs)) && SIE_FEATB((_regs), _feat_byte, _feat_name) )
#define SIE_STATNB(_regs, _feat_byte, _feat_name) \
(SIE_MODE((_regs)) && !SIE_FEATB((_regs), _feat_byte, _feat_name) )
#else
#define SIE_MODE(_register_context) (0)
#define SIE_STATE(_register_context) (0)
#define SIE_FEATB(_register_context, _feat_byte, _feat_name) (0)
#define SIE_STATB(_register_context, _feat_byte, _feat_name) (0)
#endif
/* The footprint_buffer option saves a copy of the register context
every time an instruction is executed. This is for problem
determination only, as it severely impacts performance. *JJ */
#if defined(OPTION_FOOTPRINT_BUFFER)
#define FOOTPRINT(_ip, _regs) \
do { \
sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]] = *(_regs); \
memcpy(&sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]++].inst,(_ip),6); \
sysblk.footprptr[(_regs)->cpuad] &= OPTION_FOOTPRINT_BUFFER - 1; \
} while(0)
#endif
#if !defined(FOOTPRINT)
#define FOOTPRINT(_ip, _regs)
#endif
/* PSW Instruction Address manipulation */
#define _PSW_IA(_regs, _n) \
(VADR)((_regs)->AIV + ((intptr_t)(_regs)->ip - (intptr_t)(_regs)->aip) + (_n))
#define PSW_IA(_regs, _n) \
(_PSW_IA((_regs), (_n)) & ADDRESS_MAXWRAP((_regs)))
#define SET_PSW_IA(_regs) \
do { \
if ((_regs)->aie) (_regs)->psw.IA = PSW_IA((_regs), 0); \
} while (0)
#define UPD_PSW_IA(_regs, _addr) \
do { \
(_regs)->psw.IA = (_addr) & ADDRESS_MAXWRAP(_regs); \
if (likely((_regs)->aie != NULL)) { \
if (likely((_regs)->AIV == ((_regs)->psw.IA & (PAGEFRAME_PAGEMASK|1)))) \
(_regs)->ip = _PSW_IA_MAIN((_regs), (_regs)->psw.IA); \
else \
(_regs)->aie = NULL; \
} \
} while (0)
/*
* The next three macros are used by branch-and-link type instructions
* where the addressing mode is known.
* Note that wrap is not performed for PSW_IA64 and for PSW_IA31.
* For the latter, we expect branch-and-link code to `or' the hi bit
* on so there is no need to `and' it off.
*/
#define PSW_IA64(_regs, _n) \
((_regs)->AIV \
+ (((uintptr_t)(_regs)->ip + (unsigned int)(_n)) - (uintptr_t)(_regs)->aip))
#define PSW_IA31(_regs, _n) \
((_regs)->AIV_L + ((uintptr_t)(_regs)->ip + (unsigned int)(_n)) \
- (uintptr_t)(_regs)->aip)
#define PSW_IA24(_regs, _n) \
(((_regs)->AIV_L + ((uintptr_t)(_regs)->ip + (unsigned int)(_n)) \
- (uintptr_t)(_regs)->aip) & AMASK24)
/* Accelerator for instruction addresses */
#define INVALIDATE_AIA(_regs) \
do { \
if ((_regs)->aie) { \
(_regs)->psw.IA = PSW_IA((_regs), 0); \
(_regs)->aie = NULL; \
} \
} while (0)
#define INVALIDATE_AIA_MAIN(_regs, _main) \
do { \
if ((_main) == (_regs)->aip && (_regs)->aie) { \
(_regs)->psw.IA = PSW_IA((_regs), 0); \
(_regs)->aie = NULL; \
} \
} while (0)
#if 1
#define _PSW_IA_MAIN(_regs, _addr) \
((BYTE *)((uintptr_t)(_regs)->aip | (uintptr_t)((_addr) & PAGEFRAME_BYTEMASK)))
#else
#define _PSW_IA_MAIN(_regs, _addr) \
((BYTE *)((_regs)->aim ^ (uintptr_t)(_addr)))
#endif
#define _VALID_IP(_regs, _exec) \
( \
( !(_exec) && (_regs)->ip < (_regs)->aie ) \
|| \
( (_exec) && ((_regs)->ET & (PAGEFRAME_PAGEMASK|0x01)) == (_regs)->AIV \
&& _PSW_IA_MAIN((_regs), (_regs)->ET) < (_regs)->aie \
) \
)
/* Instruction fetching */
#define INSTRUCTION_FETCH(_regs, _exec) \
likely(_VALID_IP((_regs),(_exec))) \
? ((_exec) ? _PSW_IA_MAIN((_regs), (_regs)->ET) : (_regs)->ip) \
: ARCH_DEP(instfetch) ((_regs), (_exec))
/* Instruction execution */
#define EXECUTE_INSTRUCTION(_oct, _ip, _regs) \
do { \
FOOTPRINT ((_ip), (_regs)); \
COUNT_INST ((_ip), (_regs)); \
(_oct)[fetch_hw((_ip))]((_ip), (_regs)); \
} while(0)
#define UNROLLED_EXECUTE(_oct, _regs) \
if ((_regs)->ip >= (_regs)->aie) break; \
EXECUTE_INSTRUCTION((_oct), (_regs)->ip, (_regs))
/* Branching */
#define SUCCESSFUL_BRANCH(_regs, _addr, _len) \
do { \
VADR _newia; \
UPDATE_BEAR((_regs), 0); \
_newia = (_addr) & ADDRESS_MAXWRAP((_regs)); \
if (likely(!(_regs)->permode && !(_regs)->execflag) \
&& likely((_newia & (PAGEFRAME_PAGEMASK|0x01)) == (_regs)->AIV)) { \
(_regs)->ip = (BYTE *)((uintptr_t)(_regs)->aim ^ (uintptr_t)_newia); \
return; \
} else { \
if (unlikely((_regs)->execflag)) \
UPDATE_BEAR((_regs), (_len) - ((_regs)->exrl ? 6 : 4)); \
(_regs)->psw.IA = _newia; \
(_regs)->aie = NULL; \
PER_SB((_regs), (_regs)->psw.IA); \
} \
} while (0)
#define SUCCESSFUL_RELATIVE_BRANCH(_regs, _offset, _len) \
do { \
UPDATE_BEAR((_regs), 0); \
if (likely(!(_regs)->permode && !(_regs)->execflag) \
&& likely((_regs)->ip + (_offset) >= (_regs)->aip) \
&& likely((_regs)->ip + (_offset) < (_regs)->aie)) { \
(_regs)->ip += (_offset); \
return; \
} else { \
if (likely(!(_regs)->execflag)) \
(_regs)->psw.IA = PSW_IA((_regs), (_offset)); \
else { \
UPDATE_BEAR((_regs), (_len) - ((_regs)->exrl ? 6 : 4)); \
(_regs)->psw.IA = (_regs)->ET + (_offset); \
(_regs)->psw.IA &= ADDRESS_MAXWRAP((_regs)); \
} \
(_regs)->aie = NULL; \
PER_SB((_regs), (_regs)->psw.IA); \
} \
} while (0)
/* BRCL, BRASL can branch +/- 4G. This is problematic on a 32 bit host */
#define SUCCESSFUL_RELATIVE_BRANCH_LONG(_regs, _offset) \
do { \
UPDATE_BEAR((_regs), 0); \
if (likely(!(_regs)->permode && !(_regs)->execflag) \
&& likely((_offset) > -4096) \
&& likely((_offset) < 4096) \
&& likely((_regs)->ip + (_offset) >= (_regs)->aip) \
&& likely((_regs)->ip + (_offset) < (_regs)->aie)) { \
(_regs)->ip += (_offset); \
return; \
} else { \
if (likely(!(_regs)->execflag)) \
(_regs)->psw.IA = PSW_IA((_regs), (_offset)); \
else { \
UPDATE_BEAR((_regs), 6 - ((_regs)->exrl ? 6 : 4)); \
(_regs)->psw.IA = (_regs)->ET + (_offset); \
(_regs)->psw.IA &= ADDRESS_MAXWRAP((_regs)); \
} \
(_regs)->aie = NULL; \
PER_SB((_regs), (_regs)->psw.IA); \
} \
} while (0)
/* CPU Stepping or Tracing */
#define CPU_STEPPING(_regs, _ilc) \
( \
sysblk.inststep \
&& ( \
(sysblk.stepaddr[0] == 0 && sysblk.stepaddr[1] == 0) \
|| (sysblk.stepaddr[0] <= sysblk.stepaddr[1] \
&& PSW_IA((_regs), -(_ilc)) >= sysblk.stepaddr[0] \
&& PSW_IA((_regs), -(_ilc)) <= sysblk.stepaddr[1] \
) \
|| (sysblk.stepaddr[0] > sysblk.stepaddr[1] \
&& PSW_IA((_regs), -(_ilc)) >= sysblk.stepaddr[1] \
&& PSW_IA((_regs), -(_ilc)) <= sysblk.stepaddr[0] \
) \
) \
)
#define CPU_TRACING(_regs, _ilc) \
( \
sysblk.insttrace \
&& ( \
(sysblk.traceaddr[0] == 0 && sysblk.traceaddr[1] == 0) \
|| (sysblk.traceaddr[0] <= sysblk.traceaddr[1] \
&& PSW_IA((_regs), -(_ilc)) >= sysblk.traceaddr[0] \
&& PSW_IA((_regs), -(_ilc)) <= sysblk.traceaddr[1] \
) \
|| (sysblk.traceaddr[0] > sysblk.traceaddr[1] \
&& PSW_IA((_regs), -(_ilc)) >= sysblk.traceaddr[1] \
&& PSW_IA((_regs), -(_ilc)) <= sysblk.traceaddr[0] \
) \
) \
)
#define CPU_STEPPING_OR_TRACING(_regs, _ilc) \
( unlikely((_regs)->tracing) && \
(CPU_STEPPING((_regs), (_ilc)) || CPU_TRACING((_regs), (_ilc))) \
)
#define CPU_TRACING_ALL \
(sysblk.insttrace && sysblk.traceaddr[0] == 0 && sysblk.traceaddr[1] == 0)
#define CPU_STEPPING_ALL \
(sysblk.inststep && sysblk.stepaddr[0] == 0 && sysblk.stepaddr[1] == 0)
#define CPU_STEPPING_OR_TRACING_ALL \
( CPU_TRACING_ALL || CPU_STEPPING_ALL )
#define RETURN_INTCHECK(_regs) \
longjmp((_regs)->progjmp, SIE_NO_INTERCEPT)
#define ODD_CHECK(_r, _regs) \
if( (_r) & 1 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define ODD2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 1) || ((_r2) & 1) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define HW_CHECK(_value, _regs) \
if( (_value) & 1 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define FW_CHECK(_value, _regs) \
if( (_value) & 3 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define DW_CHECK(_value, _regs) \
if( (_value) & 7 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define QW_CHECK(_value, _regs) \
if( (_value) & 15 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if m is not 0, 1, or 4 to 7 */
#define HFPM_CHECK(_m, _regs) \
if (((_m) == 2) || ((_m) == 3) || ((_m) & 8)) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define PRIV_CHECK(_regs) \
if( PROBSTATE(&(_regs)->psw) ) \
(_regs)->program_interrupt( (_regs), PGM_PRIVILEGED_OPERATION_EXCEPTION)
/* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating
the lower-numbered register of a floating-point register pair) */
#define BFPREGPAIR_CHECK(_r, _regs) \
if( ((_r) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define BFPREGPAIR2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating
the lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR_CHECK(_r, _regs) \
if( ((_r) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1, r2, r3 are not all 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR3_CHECK(_r1, _r2, _r3, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) || ((_r3) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define SSID_CHECK(_regs) \
if((!((_regs)->GR_LHH(1) & 0x0001)) \
|| (_regs)->GR_LHH(1) > (0x0001|(FEATURE_LCSS_MAX-1))) \
(_regs)->program_interrupt( (_regs), PGM_OPERAND_EXCEPTION)
#define IOID_TO_SSID(_ioid) \
((_ioid) >> 16)
#define IOID_TO_LCSS(_ioid) \
((_ioid) >> 17)
#define SSID_TO_LCSS(_ssid) \
((_ssid) >> 1)
#define LCSS_TO_SSID(_lcss) \
(((_lcss) << 1) | 1)
/* Virtual Architecture Level Set Facility */
#define FACILITY_ENABLED(_faci, _regs) \
(((_regs)->facility_list[((STFL_ ## _faci)/8)]) & (0x80 >> ((STFL_ ## _faci) % 8)))
#define FACILITY_ENABLED_DEV(_faci) \
((sysblk.facility_list[sysblk.arch_mode][((STFL_ ## _faci)/8)]) & (0x80 >> ((STFL_ ## _faci) % 8)))
#define FACILITY_CHECK(_faci, _regs) \
do { \
if(!FACILITY_ENABLED( _faci, _regs ) ) \
(_regs)->program_interrupt( (_regs), PGM_OPERATION_EXCEPTION); \
} while (0)
#define PER_RANGE_CHECK(_addr, _low, _high) \
( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \
(((_addr) >= ((_low) & MAXADDRESS)) && (_addr) <= ((_high) & MAXADDRESS)) : \
(((_addr) >= ((_low) & MAXADDRESS)) || (_addr) <= ((_high) & MAXADDRESS)) )
#define PER_RANGE_CHECK2(_addr1, _addr2, _low, _high) \
( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \
(((_addr1) >= ((_low) & MAXADDRESS)) && (_addr1) <= ((_high) & MAXADDRESS)) || \
(((_addr2) >= ((_low) & MAXADDRESS)) && (_addr2) <= ((_high) & MAXADDRESS)) || \
(((_addr1) <= ((_low) & MAXADDRESS)) && (_addr2) >= ((_high) & MAXADDRESS)) : \
(((_addr2) >= ((_low) & MAXADDRESS)) || (_addr1) <= ((_high) & MAXADDRESS)) )
#ifdef WORDS_BIGENDIAN
#define CSWAP16(_x) (_x)
#define CSWAP32(_x) (_x)
#define CSWAP64(_x) (_x)
#else
#define CSWAP16(_x) bswap_16(_x)
#define CSWAP32(_x) bswap_32(_x)
#define CSWAP64(_x) bswap_64(_x)
#endif
#define FETCH_HW(_value, _storage) (_value) = fetch_hw(_storage)
#define FETCH_FW(_value, _storage) (_value) = fetch_fw(_storage)
#define FETCH_F3(_value, _storage) (_value) = fetch_f3(_storage)
#define FETCH_DW(_value, _storage) (_value) = fetch_dw(_storage)
#define STORE_HW(_storage, _value) store_hw(_storage, _value)
#define STORE_FW(_storage, _value) store_fw(_storage, _value)
#define STORE_F3(_storage, _value) store_f3(_storage, _value)
#define STORE_DW(_storage, _value) store_dw(_storage, _value)
#include "machdep.h"
#endif /*!defined(_OPCODE_H)*/
/* Program check if fpc is not valid contents for FPC register */
#undef FPC_BRM
#undef FPC_CHECK
#if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
#define FPC_BRM FPC_BRM_3BIT
#define FPC_CHECK(_fpc, _regs) \
if(((_fpc) & FPC_RESV_FPX) \
|| ((_fpc) & FPC_BRM_3BIT) == BRM_RESV4 \
|| ((_fpc) & FPC_BRM_3BIT) == BRM_RESV5 \
|| ((_fpc) & FPC_BRM_3BIT) == BRM_RESV6) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#else /*!defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
#define FPC_BRM FPC_BRM_2BIT
#define FPC_CHECK(_fpc, _regs) \
if((_fpc) & FPC_RESERVED) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#endif /*!defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
#undef SIE_ACTIVE
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
#define SIE_ACTIVE(_regs) ((_regs)->sie_active)
#else
#define SIE_ACTIVE(_regs) (0)
#endif
#undef MULTIPLE_CONTROLLED_DATA_SPACE
#if defined(_FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
#define MULTIPLE_CONTROLLED_DATA_SPACE(_regs) \
( SIE_FEATB((_regs), MX, XC) && AR_BIT(&(_regs)->psw) )
#else
#define MULTIPLE_CONTROLLED_DATA_SPACE(_regs) (0)
#endif
/* PER3 Breaking Event Address Recording (BEAR) */
#undef UPDATE_BEAR
#undef SET_BEAR_REG
#if defined(FEATURE_PER3)
#define UPDATE_BEAR(_regs, _n) (_regs)->bear_ip = (_regs)->ip + (_n)
#define SET_BEAR_REG(_regs, _ip) \
do { \
if ((_ip)) { \
(_regs)->bear = (_regs)->AIV \
+ (intptr_t)((_ip) - (_regs)->aip); \
(_regs)->bear &= ADDRESS_MAXWRAP((_regs)); \
regs->bear_ip = NULL; \
} \
} while (0)
#else
#define UPDATE_BEAR(_regs, _n) while (0)
#define SET_BEAR_REG(_regs, _ip) while (0)
#endif
/* Set addressing mode (BASSM, BSM) */
#undef SET_ADDRESSING_MODE
#if defined(FEATURE_ESAME)
#define SET_ADDRESSING_MODE(_regs, _addr) \
do { \
if ((_addr) & 1) { \
(_regs)->psw.amode64 = regs->psw.amode = 1; \
(_regs)->psw.AMASK = AMASK64; \
(_addr) ^= 1; \
} else if ((_addr) & 0x80000000) { \
(_regs)->psw.amode64 = 0; \
(_regs)->psw.amode = 1; \
(_regs)->psw.AMASK = AMASK31; \
} else { \
(_regs)->psw.amode64 = (_regs)->psw.amode = 0; \
(_regs)->psw.AMASK = AMASK24; \
} \
} while (0)
#else /* !defined(FEATURE_ESAME) */
#define SET_ADDRESSING_MODE(_regs, _addr) \
do { \
if ((_addr) & 0x80000000) { \
(_regs)->psw.amode = 1; \
(_regs)->psw.AMASK = AMASK31; \
} else { \
(_regs)->psw.amode = 0; \
(_regs)->psw.AMASK = AMASK24; \
} \
} while (0)
#endif
#undef HFPREG_CHECK
#undef HFPREG2_CHECK
#undef HFPODD_CHECK
#undef HFPODD2_CHECK
#undef FPR2I
#undef FPREX
#if defined(FEATURE_BASIC_FP_EXTENSIONS)
#if defined(_FEATURE_SIE)
/* Program check if BFP instruction is executed when AFP control is zero */
#define BFPINST_CHECK(_regs) \
if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
(_regs)->dxc = DXC_BFP_INSTRUCTION; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
}
/* Program check if DFP instruction is executed when AFP control is zero */
#define DFPINST_CHECK(_regs) \
if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
(_regs)->dxc = DXC_DFP_INSTRUCTION; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
}
/* Program check if r1 is not 0, 2, 4, or 6 */
#define HFPREG_CHECK(_r, _regs) \
if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
if( (_r) & 9 ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 and r2 are not 0, 2, 4, or 6 */
#define HFPREG2_CHECK(_r1, _r2, _regs) \
if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
if( ((_r1) & 9) || ((_r2) & 9) ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 is not 0 or 4 */
#define HFPODD_CHECK(_r, _regs) \
if( (_r) & 2 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \
else if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
if( (_r) & 9 ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 and r2 are not 0 or 4 */
#define HFPODD2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \
else if( !((_regs)->CR(0) & CR0_AFP) \
|| (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \
if( ((_r1) & 9) || ((_r2) & 9) ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
#else /*!defined(_FEATURE_SIE)*/
/* Program check if BFP instruction is executed when AFP control is zero */
#define BFPINST_CHECK(_regs) \
if( !((_regs)->CR(0) & CR0_AFP) ) { \
(_regs)->dxc = DXC_BFP_INSTRUCTION; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
}
/* Program check if DFP instruction is executed when AFP control is zero */
#define DFPINST_CHECK(_regs) \
if( !((_regs)->CR(0) & CR0_AFP) ) { \
(_regs)->dxc = DXC_DFP_INSTRUCTION; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
}
/* Program check if r1 is not 0, 2, 4, or 6 */
#define HFPREG_CHECK(_r, _regs) \
if( !((_regs)->CR(0) & CR0_AFP) ) { \
if( (_r) & 9 ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 and r2 are not 0, 2, 4, or 6 */
#define HFPREG2_CHECK(_r1, _r2, _regs) \
if( !((_regs)->CR(0) & CR0_AFP) ) { \
if( ((_r1) & 9) || ((_r2) & 9) ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 is not 0 or 4 */
#define HFPODD_CHECK(_r, _regs) \
if( (_r) & 2 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \
else if( !((_regs)->CR(0) & CR0_AFP) ) { \
if( (_r) & 9 ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
/* Program check if r1 and r2 are not 0 or 4 */
#define HFPODD2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \
else if( !((_regs)->CR(0) & CR0_AFP) ) { \
if( ((_r1) & 9) || ((_r2) & 9) ) { \
(_regs)->dxc = DXC_AFP_REGISTER; \
(_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \
} \
}
#endif /*!defined(_FEATURE_SIE)*/
/* Convert fpr to index */
#define FPR2I(_r) \
((_r) << 1)
/* Offset of extended register */
#define FPREX 4
#else /*!defined(FEATURE_BASIC_FP_EXTENSIONS)*/
/* Program check if r1 is not 0, 2, 4, or 6 */
#define HFPREG_CHECK(_r, _regs) \
if( (_r) & 9 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not 0, 2, 4, or 6 */
#define HFPREG2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 9) || ((_r2) & 9) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 is not 0 or 4 */
#define HFPODD_CHECK(_r, _regs) \
if( (_r) & 11 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not 0 or 4 */
#define HFPODD2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 11) || ((_r2) & 11) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Convert fpr to index */
#define FPR2I(_r) \
(_r)
/* Offset of extended register */
#define FPREX 2
#endif /*!defined(FEATURE_BASIC_FP_EXTENSIONS)*/
#define TLBIX(_addr) (((VADR_L)(_addr) >> TLB_PAGESHIFT) & TLB_MASK)
#define MAINADDR(_main, _addr) \
(BYTE*)((uintptr_t)(_main) ^ (uintptr_t)(_addr))
#define NEW_MAINADDR(_regs, _addr, _aaddr) \
(BYTE*)((uintptr_t)((_regs)->mainstor \
+ (uintptr_t)(_aaddr)) \
^ (uintptr_t)((_addr) & TLB_PAGEMASK))
/* Perform invalidation after storage key update.
* If the REF or CHANGE bit is turned off for an absolute
* address then we need to invalidate any cached entries
* for that address on *all* CPUs.
* FIXME: Synchronization, esp for the CHANGE bit, should
* be tighter than what is provided here.
*/
#define STORKEY_INVALIDATE(_regs, _n) \
do { \
BYTE *mn; \
mn = (_regs)->mainstor + ((_n) & PAGEFRAME_PAGEMASK); \
ARCH_DEP(invalidate_tlbe)((_regs), mn); \
if (sysblk.cpus > 1) { \
int i; \
OBTAIN_INTLOCK ((_regs)); \
for (i = 0; i < sysblk.hicpu; i++) { \
if (IS_CPU_ONLINE(i) && i != (_regs)->cpuad) { \
if ( sysblk.waiting_mask & CPU_BIT(i) ) \
ARCH_DEP(invalidate_tlbe)(sysblk.regs[i], mn); \
else { \
ON_IC_INTERRUPT(sysblk.regs[i]); \
if (!sysblk.regs[i]->invalidate) { \
sysblk.regs[i]->invalidate = 1; \
sysblk.regs[i]->invalidate_main = mn; \
} else \
sysblk.regs[i]->invalidate_main = NULL; \
} \
} \
} \
RELEASE_INTLOCK((_regs)); \
} \
} while (0)
#if defined(INLINE_STORE_FETCH_ADDR_CHECK)
#define FETCH_MAIN_ABSOLUTE(_addr, _regs, _len) \
ARCH_DEP(fetch_main_absolute)((_addr), (_regs), (_len))
#else
#define FETCH_MAIN_ABSOLUTE(_addr, _regs, _len) \
ARCH_DEP(fetch_main_absolute)((_addr), (_regs))
#endif
#define INST_UPDATE_PSW(_regs, _len, _ilc) \
do { \
if (_len) (_regs)->ip += (_len); \
if (_ilc) (_regs)->psw.ilc = (_ilc); \
} while(0)
/* Instruction decoders */
/*
* A decoder is placed at the start of each instruction. The purpose
* of a decoder is to extract the operand fields according to the
* instruction format; to increment the instruction address (IA) field
* of the PSW by 2, 4, or 6 bytes; and to set the instruction length
* code (ILC) field of the PSW in case a program check occurs.
*
* Certain decoders have additional forms with 0 and _B suffixes.
* - the 0 suffix version does not update the PSW ILC.
* - the _B suffix version updates neither the PSW ILC nor the PSW IA.
*
* The "0" versions of the decoders are chosen whenever we know
* that past this point, no program interrupt will be generated
* (like most general instructions when no storage access is needed)
* therefore needing simpler prologue code.
* The "_B" versions for some of the decoders are intended for
* "branch" type operations where updating the PSW IA to IA+ILC
* should only be done after the branch is deemed impossible.
*/
#undef DECODER_TEST_RRE
#define DECODER_TEST_RRF_R
#define DECODER_TEST_RRF_M
#define DECODER_TEST_RRF_M4
#define DECODER_TEST_RRF_RM
#define DECODER_TEST_RRF_MM
#define DECODER_TEST_RRR
#undef DECODER_TEST_RX
#define DECODER_TEST_RXE
#define DECODER_TEST_RXF
#define DECODER_TEST_RXY
#undef DECODER_TEST_RS
#define DECODER_TEST_RSY
#undef DECODER_TEST_RSL
#undef DECODER_TEST_RSI
#undef DECODER_TEST_RI
#define DECODER_TEST_RIL
#define DECODER_TEST_RIL_A
#undef DECODER_TEST_RIS
#undef DECODER_TEST_RRS
#undef DECODER_TEST_SI
#define DECODER_TEST_SIY
#undef DECODER_TEST_SIL
#undef DECODER_TEST_S
#define DECODER_TEST_SS
#define DECODER_TEST_SS_L
#define DECODER_TEST_SSE
#define DECODER_TEST_SSF
/* E implied operands and extended op code */
#undef E
#define E(_inst,_regs) E_DECODER((_inst), (_regs), 2, 2)
#define E_DECODER(_inst, _regs, _len, _ilc) \
{ \
INST_UPDATE_PSW((_regs), (_len), (_ilc)); \
UNREFERENCED(_inst); \
}
/* IE extended op code with two 4-bit immediate fields */ /*912*/
#undef IE
#undef IE0
#define IE(_inst, _regs, _i1, _i2) \
IE_DECODER(_inst, _regs, _i1, _i2, 4, 4)
#define IE0(_inst, _regs, _i1, _i2) \
IE_DECODER(_inst, _regs, _i1, _i2, 4, 0)
#define IE_DECODER(_inst, _regs, _i1, _i2, _len, _ilc) \
{ \
int i = (_inst)[3]; \
(_i1) = i >> 4; \
(_i2) = i & 0x0F; \
INST_UPDATE_PSW((_regs), (_len), (_ilc)); \
}
/* MII mask with 12-bit and 24-bit relative address fields */ /*912*/
#undef MII_A
#undef MII_A0
#define MII_A(_inst, _regs, _m1, _addr2, _addr3) \
MII_A_DECODER(_inst, _regs, _m1, _addr2, _addr3, 6, 6)