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esame.c
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/* ESAME.C (c) Copyright Jan Jaeger, 2000-2012 */
/* ESAME (z/Architecture) instructions */
/*-------------------------------------------------------------------*/
/* This module implements the instructions which exist in ESAME */
/* mode but not in ESA/390 mode, as described in the manual */
/* SA22-7832-00 z/Architecture Principles of Operation */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* EPSW/EREGG/LMD instructions - Roger Bowler */
/* PKA/PKU/UNPKA/UNPKU instructions - Roger Bowler */
/* Multiply/Divide Logical instructions - Vic Cross Feb2001*/
/* Long displacement facility - Roger Bowler June2003*/
/* DAT enhancement facility - Roger Bowler July2004*/
/* Extended immediate facility - Roger Bowler Aug2005*/
/*-------------------------------------------------------------------*/
#include "hstdinc.h"
#if !defined(_HENGINE_DLL_)
#define _HENGINE_DLL_
#endif
#if !defined(_ESAME_C_)
#define _ESAME_C_
#endif
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
#include "clock.h"
/* When an operation code has unused operand(s) (IPK, e.g.), it will */
/* attract a diagnostic for a set, but unused variable. Fixing the */
/* macros to support e.g., RS_NOOPS is not productive, so: */
DISABLE_GCC_UNUSED_SET_WARNING
#if defined(FEATURE_BINARY_FLOATING_POINT)
/*-------------------------------------------------------------------*/
/* B29C STFPC - Store FPC [S] */
/*-------------------------------------------------------------------*/
DEF_INST(store_fpc)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
BFPINST_CHECK(regs);
/* Store register contents at operand address */
ARCH_DEP(vstore4) ( regs->fpc, effective_addr2, b2, regs );
} /* end DEF_INST(store_fpc) */
#endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
#if defined(FEATURE_BINARY_FLOATING_POINT)
/*-------------------------------------------------------------------*/
/* B29D LFPC - Load FPC [S] */
/*-------------------------------------------------------------------*/
DEF_INST(load_fpc)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
U32 tmp_fpc;
S(inst, regs, b2, effective_addr2);
BFPINST_CHECK(regs);
/* Load FPC register from operand address */
tmp_fpc = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
/* Program check if reserved bits are non-zero */
FPC_CHECK(tmp_fpc, regs);
/* Update FPC register */
regs->fpc = tmp_fpc;
} /* end DEF_INST(load_fpc) */
#endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
#if defined(FEATURE_BINARY_FLOATING_POINT)
/*-------------------------------------------------------------------*/
/* B384 SFPC - Set FPC [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(set_fpc)
{
int r1, unused; /* Values of R fields */
RRE(inst, regs, r1, unused);
BFPINST_CHECK(regs);
/* Program check if reserved bits are non-zero */
FPC_CHECK(regs->GR_L(r1), regs);
/* Load FPC register from R1 register bits 32-63 */
regs->fpc = regs->GR_L(r1);
} /* end DEF_INST(set_fpc) */
#endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
#if defined(FEATURE_BINARY_FLOATING_POINT)
/*-------------------------------------------------------------------*/
/* B38C EFPC - Extract FPC [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(extract_fpc)
{
int r1, unused; /* Values of R fields */
RRE(inst, regs, r1, unused);
BFPINST_CHECK(regs);
/* Load R1 register bits 32-63 from FPC register */
regs->GR_L(r1) = regs->fpc;
} /* end DEF_INST(extract_fpc) */
#endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
#if defined(FEATURE_BINARY_FLOATING_POINT)
/*-------------------------------------------------------------------*/
/* B299 SRNM - Set BFP Rounding Mode (2-bit) [S] */
/*-------------------------------------------------------------------*/
DEF_INST(set_bfp_rounding_mode_2bit)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
BFPINST_CHECK(regs);
/* Set FPC register BFP rounding mode bits from operand address */
regs->fpc &= ~(FPC_BRM_2BIT);
regs->fpc |= (effective_addr2 & FPC_BRM_2BIT);
#if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
/* Zeroize FPC bit 29 if FP Extension Facility is installed */
regs->fpc &= ~(FPC_BIT29);
#endif /*defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
} /* end DEF_INST(set_bfp_rounding_mode_2bit) */
#endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
#if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
/*-------------------------------------------------------------------*/
/* B2B8 SRNMB - Set BFP Rounding Mode (3-bit) [S] */
/*-------------------------------------------------------------------*/
DEF_INST(set_bfp_rounding_mode_3bit) /*810*/
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
BFPINST_CHECK(regs);
/* Program check if operand address bits 56-60 are non-zero */
if ((effective_addr2 & 0xFF) & ~(FPC_BRM_3BIT))
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
/* Program check if operand address bits 61-63 not a valid BRM */
if ((effective_addr2 & FPC_BRM_3BIT) == BRM_RESV4
|| (effective_addr2 & FPC_BRM_3BIT) == BRM_RESV5
|| (effective_addr2 & FPC_BRM_3BIT) == BRM_RESV6)
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
/* Set FPC 3-bit BFP rounding mode bits from operand address */
regs->fpc &= ~(FPC_BRM_3BIT);
regs->fpc |= (effective_addr2 & FPC_BRM_3BIT);
} /* end DEF_INST(set_bfp_rounding_mode_3bit) */
#endif /*defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
#if defined(FEATURE_LINKAGE_STACK)
/*-------------------------------------------------------------------*/
/* 01FF TRAP2 - Trap [E] */
/*-------------------------------------------------------------------*/
DEF_INST(trap2)
{
E(inst, regs);
UNREFERENCED(inst);
ARCH_DEP(trap_x) (0, regs, 0);
} /* end DEF_INST(trap2) */
#endif /*defined(FEATURE_LINKAGE_STACK)*/
#if defined(FEATURE_LINKAGE_STACK)
/*-------------------------------------------------------------------*/
/* B2FF TRAP4 - Trap [S] */
/*-------------------------------------------------------------------*/
DEF_INST(trap4)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
ARCH_DEP(trap_x) (1, regs, effective_addr2);
} /* end DEF_INST(trap4) */
#endif /*defined(FEATURE_LINKAGE_STACK)*/
#if defined(FEATURE_RESUME_PROGRAM)
/*-------------------------------------------------------------------*/
/* B277 RP - Resume Program [S] */
/*-------------------------------------------------------------------*/
DEF_INST(resume_program)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
VADR pl_addr; /* Address of parmlist */
U16 flags; /* Flags in parmfield */
U16 psw_offset; /* Offset to new PSW */
U16 ar_offset; /* Offset to new AR */
U16 gr_offset; /* Offset to new GR */
U32 ar; /* Copy of new AR */
U32 gr = 0; /* Copy of new GR */
#if defined(FEATURE_ESAME)
U16 grd_offset = 0; /* Offset of disjoint GR_H */
BYTE psw[16]; /* Copy of new PSW */
U64 gr8 = 0; /* Copy of new GR - 8 bytes */
U32 grd = 0; /* Copy of new GR - disjoint */
U64 ia; /* ia for trace */
BYTE amode64; /* save for amod64 */
#else /*!defined(FEATURE_ESAME)*/
BYTE psw[8]; /* Copy of new PSW */
U32 ia; /* ia for trace */
#endif /*!defined(FEATURE_ESAME)*/
BYTE amode; /* amode for trace */
PSW save_psw; /* Saved copy of current PSW */
BYTE *mn; /* Mainstor address of parm */
#ifdef FEATURE_TRACING
CREG newcr12 = 0; /* CR12 upon completion */
#endif /*FEATURE_TRACING*/
S(inst, regs, b2, effective_addr2);
/* Determine the address of the parameter list */
pl_addr = likely(!regs->execflag) ? PSW_IA(regs, 0) :
regs->exrl ? (regs->ET + 6) : (regs->ET + 4);
/* Fetch flags from the instruction address space */
mn = MADDR (pl_addr, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
FETCH_HW(flags, mn);
#if defined(FEATURE_ESAME)
/* Bits 0-12 must be zero */
if(flags & 0xFFF8)
#else /*!defined(FEATURE_ESAME)*/
/* All flag bits must be zero in ESA/390 mode */
if(flags)
#endif /*!defined(FEATURE_ESAME)*/
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
/* Fetch the offset to the new psw */
mn = MADDR (pl_addr + 2, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
FETCH_HW(psw_offset, mn);
/* Fetch the offset to the new ar */
mn = MADDR (pl_addr + 4, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
FETCH_HW(ar_offset, mn);
/* Fetch the offset to the new gr */
mn = MADDR (pl_addr + 6, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
FETCH_HW(gr_offset, mn);
#if defined(FEATURE_ESAME)
/* Fetch the offset to the new disjoint gr_h */
if((flags & 0x0003) == 0x0003)
{
mn = MADDR (pl_addr + 8, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
FETCH_HW(grd_offset, mn);
}
#endif /*defined(FEATURE_ESAME)*/
/* Fetch the PSW from the operand address + psw offset */
#if defined(FEATURE_ESAME)
if(flags & 0x0004)
ARCH_DEP(vfetchc) (psw, 15, (effective_addr2 + psw_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
else
#endif /*defined(FEATURE_ESAME)*/
ARCH_DEP(vfetchc) (psw, 7, (effective_addr2 + psw_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
/* Fetch new AR (B2) from operand address + AR offset */
ar = ARCH_DEP(vfetch4) ((effective_addr2 + ar_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
/* Fetch the new gr from operand address + GPR offset */
#if defined(FEATURE_ESAME)
/* General Register Field 1 is eight bytes */
if((flags & 0x0003) == 0x0002)
{
gr8 = ARCH_DEP(vfetch8) ((effective_addr2 + gr_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
}
/* General Register Field 1 and 2 are four bytes - disjoint */
else if((flags & 0x0003) == 0x0003)
{
gr = ARCH_DEP(vfetch4) ((effective_addr2 + gr_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
grd = ARCH_DEP(vfetch4) ((effective_addr2 + grd_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
}
else
#endif /*defined(FEATURE_ESAME)*/
gr = ARCH_DEP(vfetch4) ((effective_addr2 + gr_offset)
& ADDRESS_MAXWRAP(regs), b2, regs);
#if defined(FEATURE_TRACING)
#if defined(FEATURE_ESAME)
/* fetch 8 or 4 byte IA depending on psw operand size */
if (flags & 0x0004)
FETCH_DW(ia, psw + 8);
else
FETCH_FW(ia, psw + 4);
amode64 = psw[3] & 0x01;
#else /*!defined(FEATURE_ESAME)*/
FETCH_FW(ia, psw + 4);
ia &= 0x7FFFFFFF;
#endif /*!defined(FEATURE_ESAME)*/
amode = psw[4] & 0x80;
#if defined(FEATURE_ESAME)
/* Add a mode trace entry when switching in/out of 64 bit mode */
if((regs->CR(12) & CR12_MTRACE) && (regs->psw.amode64 != amode64))
newcr12 = ARCH_DEP(trace_ms) (regs->CR(12) & CR12_BRTRACE ? 1 : 0, ia, regs);
else
#endif /*defined(FEATURE_ESAME)*/
if (regs->CR(12) & CR12_BRTRACE)
newcr12 = ARCH_DEP(trace_br) (amode, ia, regs);
#endif /*defined(FEATURE_TRACING)*/
INVALIDATE_AIA(regs);
/* Save current PSW */
save_psw = regs->psw;
/* Use bytes 0 and 1 of old psw and byte 2 from operand */
psw[0] = save_psw.sysmask;
psw[1] = save_psw.pkey | save_psw.states;
/* ignore bits 24-30 */
psw[3] = 0x01 & psw[3];
#if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
if(SIE_STATB(regs, MX, XC)
&& (psw[2] & 0x80))
regs->program_interrupt (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
#endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
/* Special operation exception when setting AR space mode
and ASF is off */
if(!REAL_MODE(®s->psw)
&& ((psw[2] & 0xC0) == 0x40)
&& !ASF_ENABLED(regs) )
regs->program_interrupt (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Privileged Operation exception when setting home
space mode in problem state */
if(!REAL_MODE(®s->psw)
&& PROBSTATE(®s->psw)
&& ((psw[2] & 0xC0) == 0xC0) )
regs->program_interrupt (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
#if defined(FEATURE_ESAME)
/* Handle 16 byte psw operand */
if(flags & 0x0004)
{
psw[1] &= ~0x08; /* force bit 12 off */
if( ARCH_DEP(load_psw) (regs, psw) )/* only check invalid IA not odd */
{
/* restore the psw */
regs->psw = save_psw;
/* And generate a program interrupt */
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
}
}
/* Handle 8 byte psw operand */
else
{
/* Save amode64, do not check amode64 bit (force to zero) */
/* This is so s390_load_psw will work. */
/* Checks for amode64 will be done a few lines later */
amode64 = psw[3] & 01;
psw[3] &= ~0x01;
#endif /*defined(FEATURE_ESAME)*/
psw[1] |= 0x08; /* force bit 12 on */
if( s390_load_psw(regs, psw) )
{
/* restore the psw */
regs->psw = save_psw;
/* And generate a program interrupt */
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
}
#if defined(FEATURE_ESAME)
regs->psw.states &= ~BIT(PSW_NOTESAME_BIT);
/* clear high word of IA since operand was 8-byte psw */
regs->psw.IA_H = 0;
/* Check original amode64 and restore and do checks */
if (amode64)
{
/* if amode64 (31) on, then amode (32) must be on too */
if (!regs->psw.amode)
{
/* restore the psw */
regs->psw = save_psw;
/* And generate a program interrupt */
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
}
regs->psw.amode64 = 1;
regs->psw.AMASK = AMASK64;
}
else
{
regs->psw.amode64 = 0;
regs->psw.AMASK_H = 0;
}
}
#endif /*defined(FEATURE_ESAME)*/
/* Check for odd IA in psw */
if(regs->psw.IA & 0x01)
{
/* restore the psw */
regs->psw = save_psw;
/* And generate a program interrupt */
regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
}
/* Update access register b2 */
regs->AR(b2) = ar;
/* Update general register b2 */
#if defined(FEATURE_ESAME)
if((flags & 0x0003) == 0x0002)
regs->GR_G(b2) = gr8;
else if((flags & 0x0003) == 0x0003)
{
regs->GR_L(b2) = gr;
regs->GR_H(b2) = grd;
}
else
#endif /*defined(FEATURE_ESAME)*/
regs->GR_L(b2) = gr;
#ifdef FEATURE_TRACING
/* Update trace table address if branch tracing is on */
if (newcr12)
regs->CR(12) = newcr12;
#endif /*FEATURE_TRACING*/
SET_BEAR_REG(regs, regs->ip - 4);
SET_IC_ECMODE_MASK(regs);
SET_AEA_MODE(regs);
PER_SB(regs, regs->psw.IA);
/* Space switch event when switching into or
out of home space mode AND space-switch-event on in CR1 or CR13 */
if((HOME_SPACE_MODE(&(regs->psw)) ^ HOME_SPACE_MODE(&save_psw))
&& (!REAL_MODE(®s->psw))
&& ((regs->CR(1) & SSEVENT_BIT) || (regs->CR(13) & SSEVENT_BIT)
|| OPEN_IC_PER(regs) ))
{
if (HOME_SPACE_MODE(&(regs->psw)))
{
/* When switching into home-space mode, set the
translation exception address equal to the primary
ASN, with the high-order bit set equal to the value
of the primary space-switch-event control bit */
regs->TEA = regs->CR_LHL(4);
if (regs->CR(1) & SSEVENT_BIT)
regs->TEA |= TEA_SSEVENT;
}
else
{
/* When switching out of home-space mode, set the
translation exception address equal to zero, with
the high-order bit set equal to the value of the
home space-switch-event control bit */
regs->TEA = 0;
if (regs->CR(13) & SSEVENT_BIT)
regs->TEA |= TEA_SSEVENT;
}
regs->program_interrupt (regs, PGM_SPACE_SWITCH_EVENT);
}
RETURN_INTCHECK(regs);
} /* end DEF_INST(resume_program) */
#endif /*defined(FEATURE_RESUME_PROGRAM)*/
#if defined(FEATURE_ESAME) && defined(FEATURE_TRACING)
/*-------------------------------------------------------------------*/
/* EB0F TRACG - Trace Long [RSY] */
/*-------------------------------------------------------------------*/
DEF_INST(trace_long)
{
int r1, r3; /* Register numbers */
int b2; /* effective address base */
VADR effective_addr2; /* effective address */
#if defined(FEATURE_TRACING)
U32 op; /* Operand */
#endif /*defined(FEATURE_TRACING)*/
RSY(inst, regs, r1, r3, b2, effective_addr2);
PRIV_CHECK(regs);
FW_CHECK(effective_addr2, regs);
/* Exit if explicit tracing (control reg 12 bit 31) is off */
if ( (regs->CR(12) & CR12_EXTRACE) == 0 )
return;
/* Fetch the trace operand */
op = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
/* Exit if bit zero of the trace operand is one */
if ( (op & 0x80000000) )
return;
/* Perform serialization and checkpoint-synchronization */
PERFORM_SERIALIZATION (regs);
PERFORM_CHKPT_SYNC (regs);
regs->CR(12) = ARCH_DEP(trace_tg) (r1, r3, op, regs);
/* Perform serialization and checkpoint-synchronization */
PERFORM_SERIALIZATION (regs);
PERFORM_CHKPT_SYNC (regs);
} /* end DEF_INST(trace_long) */
#endif /*defined(FEATURE_ESAME) && defined(FEATURE_TRACING)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E30E CVBG - Convert to Binary Long [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(convert_to_binary_long)
{
U64 dreg; /* 64-bit result accumulator */
int r1; /* Value of R1 field */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
int ovf; /* 1=overflow */
int dxf; /* 1=data exception */
BYTE dec[16]; /* Packed decimal operand */
RXY(inst, regs, r1, b2, effective_addr2);
/* Fetch 16-byte packed decimal operand */
ARCH_DEP(vfetchc) ( dec, 16-1, effective_addr2, b2, regs );
/* Convert 16-byte packed decimal to 64-bit signed binary */
packed_to_binary (dec, 16-1, &dreg, &ovf, &dxf);
/* Data exception if invalid digits or sign */
if (dxf)
{
regs->dxc = DXC_DECIMAL;
regs->program_interrupt (regs, PGM_DATA_EXCEPTION);
}
/* Exception if overflow (operation suppressed, R1 unchanged) */
if (ovf)
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
/* Store 64-bit result into R1 register */
regs->GR_G(r1) = dreg;
} /* end DEF_INST(convert_to_binary_long) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E32E CVDG - Convert to Decimal Long [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(convert_to_decimal_long)
{
S64 bin; /* Signed value to convert */
int r1; /* Value of R1 field */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
BYTE dec[16]; /* Packed decimal result */
RXY(inst, regs, r1, b2, effective_addr2);
/* Load signed value of register */
bin = (S64)(regs->GR_G(r1));
/* Convert to 16-byte packed decimal number */
binary_to_packed (bin, dec);
/* Store 16-byte packed decimal result at operand address */
ARCH_DEP(vstorec) ( dec, 16-1, effective_addr2, b2, regs );
} /* end DEF_INST(convert_to_decimal_long) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E396 ML - Multiply Logical [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(multiply_logical)
{
int r1; /* Values of R fields */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective Address */
U32 m;
U64 p;
RXY(inst, regs, r1, b2, effective_addr2);
ODD_CHECK(r1, regs);
/* Load second operand from operand address */
m = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
/* Multiply unsigned values */
p = (U64)regs->GR_L(r1 + 1) * m;
/* Store the result */
regs->GR_L(r1) = (p >> 32);
regs->GR_L(r1 + 1) = (p & 0xFFFFFFFF);
} /* end DEF_INST(multiply_logical) */
#endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E386 MLG - Multiply Logical Long [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_long)
{
int r1; /* Values of R fields */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective Address */
U64 m, ph, pl;
RXY(inst, regs, r1, b2, effective_addr2);
ODD_CHECK(r1, regs);
/* Load second operand from operand address */
m = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
/* Multiply unsigned values */
mult_logical_long(&ph, &pl, regs->GR_G(r1 + 1), m);
/* Store the result */
regs->GR_G(r1) = ph;
regs->GR_G(r1 + 1) = pl;
} /* end DEF_INST(multiply_logical_long) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B996 MLR - Multiply Logical Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_register)
{
int r1, r2; /* Values of R fields */
U64 p;
RRE(inst, regs, r1, r2);
ODD_CHECK(r1, regs);
/* Multiply unsigned values */
p = (U64)regs->GR_L(r1 + 1) * (U64)regs->GR_L(r2);
/* Store the result */
regs->GR_L(r1) = (p >> 32);
regs->GR_L(r1 + 1) = (p & 0xFFFFFFFF);
} /* end DEF_INST(multiply_logical_register) */
#endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B986 MLGR - Multiply Logical Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_long_register)
{
int r1, r2; /* Values of R fields */
U64 ph, pl;
RRE(inst, regs, r1, r2);
ODD_CHECK(r1, regs);
/* Multiply unsigned values */
mult_logical_long(&ph, &pl, regs->GR_G(r1 + 1), regs->GR_G(r2));
/* Store the result */
regs->GR_G(r1) = ph;
regs->GR_G(r1 + 1) = pl;
} /* end DEF_INST(multiply_logical_long_register) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E397 DL - Divide Logical [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(divide_logical)
{
int r1; /* Values of R fields */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective Address */
U32 d;
U64 n;
RXY(inst, regs, r1, b2, effective_addr2);
ODD_CHECK(r1, regs);
n = ((U64)regs->GR_L(r1) << 32) | (U32)regs->GR_L(r1 + 1);
/* Load second operand from operand address */
d = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
if (d == 0
|| (n / d) > 0xFFFFFFFF)
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
/* Divide unsigned registers */
regs->GR_L(r1) = n % d;
regs->GR_L(r1 + 1) = n / d;
} /* end DEF_INST(divide_logical) */
#endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* E387 DLG - Divide Logical Long [RXY] */
/*-------------------------------------------------------------------*/
DEF_INST(divide_logical_long)
{
int r1; /* Values of R fields */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective Address */
U64 d, r, q;
RXY(inst, regs, r1, b2, effective_addr2);
ODD_CHECK(r1, regs);
/* Load second operand from operand address */
d = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
if (regs->GR_G(r1) == 0) /* check for the simple case */
{
if (d == 0)
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
/* Divide signed registers */
regs->GR_G(r1) = regs->GR_G(r1 + 1) % d;
regs->GR_G(r1 + 1) = regs->GR_G(r1 + 1) / d;
}
else
{
if (div_logical_long(&r, &q, regs->GR_G(r1), regs->GR_G(r1 + 1), d) )
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
else
{
regs->GR_G(r1) = r;
regs->GR_G(r1 + 1) = q;
}
}
} /* end DEF_INST(divide_logical_long) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B997 DLR - Divide Logical Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(divide_logical_register)
{
int r1, r2; /* Values of R fields */
U64 n;
U32 d;
RRE(inst, regs, r1, r2);
ODD_CHECK(r1, regs);
n = ((U64)regs->GR_L(r1) << 32) | regs->GR_L(r1 + 1);
d = regs->GR_L(r2);
if(d == 0
|| (n / d) > 0xFFFFFFFF)
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
/* Divide signed registers */
regs->GR_L(r1) = n % d;
regs->GR_L(r1 + 1) = n / d;
} /* end DEF_INST(divide_logical_register) */
#endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B987 DLGR - Divide Logical Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(divide_logical_long_register)
{
int r1, r2; /* Values of R fields */
U64 r, q, d;
RRE(inst, regs, r1, r2);
ODD_CHECK(r1, regs);
d = regs->GR_G(r2);
if (regs->GR_G(r1) == 0) /* check for the simple case */
{
if(d == 0)
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
/* Divide signed registers */
regs->GR_G(r1) = regs->GR_G(r1 + 1) % d;
regs->GR_G(r1 + 1) = regs->GR_G(r1 + 1) / d;
}
else
{
if (div_logical_long(&r, &q, regs->GR_G(r1), regs->GR_G(r1 + 1), d) )
regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
else
{
regs->GR_G(r1) = r;
regs->GR_G(r1 + 1) = q;
}
}
} /* end DEF_INST(divide_logical_long_register) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B988 ALCGR - Add Logical with Carry Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(add_logical_carry_long_register)
{
int r1, r2; /* Values of R fields */
int carry = 0;
U64 n;
RRE0(inst, regs, r1, r2);
n = regs->GR_G(r2);
/* Add the carry to operand */
if(regs->psw.cc & 2)
carry = add_logical_long(&(regs->GR_G(r1)),
regs->GR_G(r1),
1) & 2;
/* Add unsigned operands and set condition code */
regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
regs->GR_G(r1),
n) | carry;
} /* end DEF_INST(add_logical_carry_long_register) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_ESAME)
/*-------------------------------------------------------------------*/
/* B989 SLBGR - Subtract Logical with Borrow Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_borrow_long_register)
{
int r1, r2; /* Values of R fields */
int borrow = 2;
U64 n;
RRE0(inst, regs, r1, r2);
n = regs->GR_G(r2);
/* Subtract the borrow from operand */
if(!(regs->psw.cc & 2))
borrow = sub_logical_long(&(regs->GR_G(r1)),
regs->GR_G(r1),
1);
/* Subtract unsigned operands and set condition code */
regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
regs->GR_G(r1),
n) & (borrow|1);
} /* end DEF_INST(subtract_logical_borrow_long_register) */
#endif /*defined(FEATURE_ESAME)*/
#if defined(FEATURE_DAT_ENHANCEMENT)
/*-------------------------------------------------------------------*/
/* B98A CSPG - Compare and Swap and Purge Long [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_and_purge_long)
{
int r1, r2; /* Values of R fields */
U64 n2; /* Virtual address of op2 */
BYTE *main2; /* Mainstor address of op2 */
U64 old; /* Old value */
RRE(inst, regs, r1, r2);
PRIV_CHECK(regs);
ODD_CHECK(r1, regs);
#if defined(_FEATURE_SIE)
if(SIE_STATB(regs,IC0, IPTECSP))
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
#endif /*defined(_FEATURE_SIE)*/
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs) && regs->sie_scao)
{
STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
if(regs->mainstor[regs->sie_scao] & 0x80)
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
}
#endif /*defined(_FEATURE_SIE)*/
/* Perform serialization before starting operation */
PERFORM_SERIALIZATION (regs);
/* Obtain 2nd operand address from r2 */
n2 = regs->GR(r2) & 0xFFFFFFFFFFFFFFF8ULL & ADDRESS_MAXWRAP(regs);
main2 = MADDR (n2, r2, regs, ACCTYPE_WRITE, regs->psw.pkey);
old = CSWAP64 (regs->GR_G(r1));
/* Obtain main-storage access lock */
OBTAIN_MAINLOCK(regs);
/* Attempt to exchange the values */
regs->psw.cc = cmpxchg8 (&old, CSWAP64(regs->GR_G(r1+1)), main2);
/* Release main-storage access lock */
RELEASE_MAINLOCK(regs);
if (regs->psw.cc == 0)
{
/* Perform requested funtion specified as per request code in r2 */
if (regs->GR_L(r2) & 3)
{
OBTAIN_INTLOCK(regs);
SYNCHRONIZE_CPUS(regs);
if (regs->GR_L(r2) & 1)
ARCH_DEP(purge_tlb_all)();
if (regs->GR_L(r2) & 2)
ARCH_DEP(purge_alb_all)();
RELEASE_INTLOCK(regs);
}
}
else
{
PTT_CSF("*CSPG",regs->GR_L(r1),regs->GR_L(r2),regs->psw.IA_L);
/* Otherwise yield */
regs->GR_G(r1) = CSWAP64(old);