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cpu.c
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/* CPU.C (c) Copyright Roger Bowler, 1994-2012 */
/* (c) Copyright Jan Jaeger, 1999-2012 */
/* ESA/390 CPU Emulator */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
/* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2012 */
/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2012 */
/*-------------------------------------------------------------------*/
/* This module implements the CPU instruction execution function of */
/* the S/370 and ESA/390 architectures, as described in the manuals */
/* GA22-7000-03 System/370 Principles of Operation */
/* SA22-7201-06 ESA/390 Principles of Operation */
/* SA22-7832-00 z/Architecture Principles of Operation */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* Nullification corrections by Jan Jaeger */
/* Set priority by Reed H. Petty from an idea by Steve Gay */
/* Corrections to program check by Jan Jaeger */
/* Light optimization on critical path by Valery Pogonchenko */
/* OSTAILOR parameter by Jay Maynard */
/* CPU timer and clock comparator interrupt improvements by */
/* Jan Jaeger, after a suggestion by Willem Konynenberg */
/* Instruction decode rework - Jan Jaeger */
/* Modifications for Interpretive Execution (SIE) by Jan Jaeger */
/* Basic FP extensions support - Peter Kuschnerus v209*/
/* ASN-and-LX-reuse facility - Roger Bowler, June 2004 @ALR*/
/*-------------------------------------------------------------------*/
#include "hstdinc.h"
#if !defined(_HENGINE_DLL_)
#define _HENGINE_DLL_
#endif
#if !defined(_CPU_C_)
#define _CPU_C_
#endif
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
// #define JPHTEST
/*-------------------------------------------------------------------*/
/* Put a CPU in check-stop state */
/* Must hold the system intlock */
/*-------------------------------------------------------------------*/
void ARCH_DEP(checkstop_cpu)(REGS *regs)
{
regs->cpustate=CPUSTATE_STOPPING;
regs->checkstop=1;
ON_IC_INTERRUPT(regs);
}
/*-------------------------------------------------------------------*/
/* Put all the CPUs in the configuration in check-stop state */
/*-------------------------------------------------------------------*/
void ARCH_DEP(checkstop_config)(void)
{
int i;
for(i=0;i<sysblk.maxcpu;i++)
{
if(IS_CPU_ONLINE(i))
{
ARCH_DEP(checkstop_cpu)(sysblk.regs[i]);
}
}
WAKEUP_CPUS_MASK(sysblk.waiting_mask);
}
/*-------------------------------------------------------------------*/
/* Store current PSW at a specified address in main storage */
/*-------------------------------------------------------------------*/
void ARCH_DEP(store_psw) (REGS *regs, BYTE *addr)
{
/* Ensure psw.IA is set */
if (!regs->psw.zeroilc)
SET_PSW_IA(regs);
#if defined(FEATURE_BCMODE)
if ( ECMODE(®s->psw) ) {
#endif /*defined(FEATURE_BCMODE)*/
#if !defined(FEATURE_ESAME)
STORE_FW ( addr,
( (regs->psw.sysmask << 24)
| ((regs->psw.pkey | regs->psw.states) << 16)
| ( ( (regs->psw.asc)
| (regs->psw.cc << 4)
| (regs->psw.progmask)
) << 8
)
| regs->psw.zerobyte
)
);
if(unlikely(regs->psw.zeroilc))
STORE_FW ( addr + 4, regs->psw.IA | (regs->psw.amode ? 0x80000000 : 0) );
else
STORE_FW ( addr + 4,
( (regs->psw.IA & ADDRESS_MAXWRAP(regs)) | (regs->psw.amode ? 0x80000000 : 0) )
);
#endif /*!defined(FEATURE_ESAME)*/
#if defined(FEATURE_BCMODE)
} else {
STORE_FW ( addr,
( (regs->psw.sysmask << 24)
| ((regs->psw.pkey | regs->psw.states) << 16)
| (regs->psw.intcode)
)
);
if(unlikely(regs->psw.zeroilc))
STORE_FW ( addr + 4,
( ( (REAL_ILC(regs) << 5)
| (regs->psw.cc << 4)
| regs->psw.progmask
) << 24
) | regs->psw.IA
);
else
STORE_FW ( addr + 4,
( ( (REAL_ILC(regs) << 5)
| (regs->psw.cc << 4)
| regs->psw.progmask
) << 24
) | (regs->psw.IA & ADDRESS_MAXWRAP(regs))
);
}
#elif defined(FEATURE_ESAME)
STORE_FW ( addr,
( (regs->psw.sysmask << 24)
| ((regs->psw.pkey | regs->psw.states) << 16)
| ( ( (regs->psw.asc)
| (regs->psw.cc << 4)
| (regs->psw.progmask)
) << 8
)
| (regs->psw.amode64 ? 0x01 : 0)
| regs->psw.zerobyte
)
);
STORE_FW ( addr + 4,
( (regs->psw.amode ? 0x80000000 : 0 )
| regs->psw.zeroword
)
);
STORE_DW ( addr + 8, regs->psw.IA_G );
#endif /*defined(FEATURE_ESAME)*/
} /* end function ARCH_DEP(store_psw) */
/*-------------------------------------------------------------------*/
/* Load current PSW from a specified address in main storage */
/* Returns 0 if valid, 0x0006 if specification exception */
/*-------------------------------------------------------------------*/
int ARCH_DEP(load_psw) (REGS *regs, BYTE *addr)
{
INVALIDATE_AIA(regs);
regs->psw.zeroilc = 1;
regs->psw.sysmask = addr[0];
regs->psw.pkey = (addr[1] & 0xF0);
regs->psw.states = (addr[1] & 0x0F);
#if defined(FEATURE_BCMODE)
if ( ECMODE(®s->psw) ) {
#endif /*defined(FEATURE_BCMODE)*/
SET_IC_ECMODE_MASK(regs);
/* Processing for EC mode PSW */
regs->psw.intcode = 0;
regs->psw.asc = (addr[2] & 0xC0);
regs->psw.cc = (addr[2] & 0x30) >> 4;
regs->psw.progmask = (addr[2] & 0x0F);
regs->psw.amode = (addr[4] & 0x80) ? 1 : 0;
#if defined(FEATURE_ESAME)
regs->psw.zerobyte = addr[3] & 0xFE;
regs->psw.amode64 = addr[3] & 0x01;
regs->psw.zeroword = fetch_fw(addr+4) & 0x7FFFFFFF;
regs->psw.IA = fetch_dw (addr + 8);
regs->psw.AMASK = regs->psw.amode64 ? AMASK64
: regs->psw.amode ? AMASK31 : AMASK24;
#else /*!defined(FEATURE_ESAME)*/
regs->psw.zerobyte = addr[3];
regs->psw.amode64 = 0;
regs->psw.IA = fetch_fw(addr + 4) & 0x7FFFFFFF;
regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
#endif /*!defined(FEATURE_ESAME)*/
/* Bits 0 and 2-4 of system mask must be zero */
if ((addr[0] & 0xB8) != 0)
return PGM_SPECIFICATION_EXCEPTION;
#if defined(FEATURE_ESAME)
/* For ESAME, bit 12 must be zero */
if (NOTESAME(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
/* Bits 24-30 must be zero */
if (regs->psw.zerobyte)
return PGM_SPECIFICATION_EXCEPTION;
/* Bits 33-63 must be zero */
if ( regs->psw.zeroword )
return PGM_SPECIFICATION_EXCEPTION;
#else /*!defined(FEATURE_ESAME)*/
/* Bits 24-31 must be zero */
if ( regs->psw.zerobyte )
return PGM_SPECIFICATION_EXCEPTION;
/* For ESA/390, bit 12 must be one */
if (!ECMODE(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif /*!defined(FEATURE_ESAME)*/
#ifndef FEATURE_DUAL_ADDRESS_SPACE
/* If DAS feature not installed then bit 16 must be zero */
if (SPACE_BIT(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif /*!FEATURE_DUAL_ADDRESS_SPACE*/
#ifndef FEATURE_ACCESS_REGISTERS
/* If not ESA/370 or ESA/390 then bit 17 must be zero */
if (AR_BIT(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif /*!FEATURE_ACCESS_REGISTERS*/
/* Check validity of amode and instruction address */
#if defined(FEATURE_ESAME)
/* For ESAME, bit 32 cannot be zero if bit 31 is one */
if (regs->psw.amode64 && !regs->psw.amode)
return PGM_SPECIFICATION_EXCEPTION;
/* If bit 32 is zero then IA cannot exceed 24 bits */
if (!regs->psw.amode && regs->psw.IA > 0x00FFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
/* If bit 31 is zero then IA cannot exceed 31 bits */
if (!regs->psw.amode64 && regs->psw.IA > 0x7FFFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
#else /*!defined(FEATURE_ESAME)*/
#ifdef FEATURE_BIMODAL_ADDRESSING
/* For 370-XA, ESA/370, and ESA/390,
if amode=24, bits 33-39 must be zero */
if (!regs->psw.amode && regs->psw.IA > 0x00FFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
#else /*!FEATURE_BIMODAL_ADDRESSING*/
/* For S/370, bits 32-39 must be zero */
if (addr[4] != 0x00)
return PGM_SPECIFICATION_EXCEPTION;
#endif /*!FEATURE_BIMODAL_ADDRESSING*/
#endif /*!defined(FEATURE_ESAME)*/
#if defined(FEATURE_BCMODE)
} else {
SET_IC_BCMODE_MASK(regs);
/* Processing for S/370 BC mode PSW */
regs->psw.intcode = fetch_hw (addr + 2);
regs->psw.cc = (addr[4] & 0x30) >> 4;
regs->psw.progmask = (addr[4] & 0x0F);
FETCH_FW(regs->psw.IA, addr + 4);
regs->psw.IA &= 0x00FFFFFF;
regs->psw.AMASK = AMASK24;
regs->psw.zerobyte = 0;
regs->psw.asc = 0;
regs->psw.amode64 = regs->psw.amode = 0;
}
#endif /*defined(FEATURE_BCMODE)*/
#if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
/* Bits 5 and 16 must be zero in XC mode */
if( SIE_STATB(regs, MX, XC)
&& ( (regs->psw.sysmask & PSW_DATMODE) || SPACE_BIT(®s->psw)) )
return PGM_SPECIFICATION_EXCEPTION;
#endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
regs->psw.zeroilc = 0;
/* Check for wait state PSW */
if (WAITSTATE(®s->psw) && CPU_STEPPING_OR_TRACING_ALL)
{
char buf[40];
WRMSG(HHC00800, "I", PTYPSTR(regs->cpuad), regs->cpuad, str_psw(regs, buf));
}
TEST_SET_AEA_MODE(regs);
return 0;
} /* end function ARCH_DEP(load_psw) */
/*-------------------------------------------------------------------*/
/* Load program interrupt new PSW */
/*-------------------------------------------------------------------*/
void (ATTR_REGPARM(2) ARCH_DEP(program_interrupt)) (REGS *regs, int pcode)
{
PSA *psa; /* -> Prefixed storage area */
REGS *realregs; /* True regs structure */
RADR px; /* host real address of pfx */
int code; /* pcode without PER ind. */
int ilc; /* instruction length */
#if defined(FEATURE_ESAME)
/** FIXME : SEE ISW20090110-1 */
void *zmoncode=NULL; /* special reloc for z/Arch */
/* FIXME : zmoncode not being initialized here raises
a potentially non-initialized warning in GCC..
can't find why. ISW 2009/02/04 */
/* mon call SIE intercept */
#endif
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
int sie_ilc=0; /* SIE instruction length */
#endif
#if defined(_FEATURE_SIE)
int nointercept; /* True for virtual pgmint */
#endif /*defined(_FEATURE_SIE)*/
#if defined(OPTION_FOOTPRINT_BUFFER)
U32 n;
#endif /*defined(OPTION_FOOTPRINT_BUFFER)*/
char dxcstr[8]={0}; /* " DXC=xx" if data excptn */
static char *pgmintname[] = {
/* 01 */ "Operation exception",
/* 02 */ "Privileged-operation exception",
/* 03 */ "Execute exception",
/* 04 */ "Protection exception",
/* 05 */ "Addressing exception",
/* 06 */ "Specification exception",
/* 07 */ "Data exception",
/* 08 */ "Fixed-point-overflow exception",
/* 09 */ "Fixed-point-divide exception",
/* 0A */ "Decimal-overflow exception",
/* 0B */ "Decimal-divide exception",
/* 0C */ "HFP-exponent-overflow exception",
/* 0D */ "HFP-exponent-underflow exception",
/* 0E */ "HFP-significance exception",
/* 0F */ "HFP-floating-point-divide exception",
/* 10 */ "Segment-translation exception",
/* 11 */ "Page-translation exception",
/* 12 */ "Translation-specification exception",
/* 13 */ "Special-operation exception",
/* 14 */ "Pseudo-page-fault exception",
/* 15 */ "Operand exception",
/* 16 */ "Trace-table exception",
/* 17 */ "ASN-translation exception",
/* 18 */ "Page access exception",
/* 19 */ "Vector/Crypto operation exception",
/* 1A */ "Page state exception",
/* 1B */ "Page transition exception",
/* 1C */ "Space-switch event",
/* 1D */ "Square-root exception",
/* 1E */ "Unnormalized-operand exception",
/* 1F */ "PC-translation specification exception",
/* 20 */ "AFX-translation exception",
/* 21 */ "ASX-translation exception",
/* 22 */ "LX-translation exception",
/* 23 */ "EX-translation exception",
/* 24 */ "Primary-authority exception",
/* 25 */ "Secondary-authority exception",
/* 26 */ "LFX-translation exception", /*@ALR*/
/* 27 */ "LSX-translation exception", /*@ALR*/
/* 28 */ "ALET-specification exception",
/* 29 */ "ALEN-translation exception",
/* 2A */ "ALE-sequence exception",
/* 2B */ "ASTE-validity exception",
/* 2C */ "ASTE-sequence exception",
/* 2D */ "Extended-authority exception",
/* 2E */ "LSTE-sequence exception", /*@ALR*/
/* 2F */ "ASTE-instance exception", /*@ALR*/
/* 30 */ "Stack-full exception",
/* 31 */ "Stack-empty exception",
/* 32 */ "Stack-specification exception",
/* 33 */ "Stack-type exception",
/* 34 */ "Stack-operation exception",
/* 35 */ "Unassigned exception",
/* 36 */ "Unassigned exception",
/* 37 */ "Unassigned exception",
/* 38 */ "ASCE-type exception",
/* 39 */ "Region-first-translation exception",
/* 3A */ "Region-second-translation exception",
/* 3B */ "Region-third-translation exception",
/* 3C */ "Unassigned exception",
/* 3D */ "Unassigned exception",
/* 3E */ "Unassigned exception",
/* 3F */ "Unassigned exception",
/* 40 */ "Monitor event" };
/* 26 */ /* was "Page-fault-assist exception", */
/* 27 */ /* was "Control-switch exception", */
/* If called with ghost registers (ie from hercules command
then ignore all interrupt handling and report the error
to the caller */
if(regs->ghostregs)
longjmp(regs->progjmp, pcode);
PTT_PGM("*PROG",pcode,(U32)(regs->TEA & 0xffffffff),regs->psw.IA_L);
/* program_interrupt() may be called with a shadow copy of the
regs structure, realregs is the pointer to the real structure
which must be used when loading/storing the psw, or backing up
the instruction address in case of nullification */
#if defined(_FEATURE_SIE)
realregs = SIE_MODE(regs)
? sysblk.regs[regs->cpuad]->guestregs
: sysblk.regs[regs->cpuad];
#else /*!defined(_FEATURE_SIE)*/
realregs = sysblk.regs[regs->cpuad];
#endif /*!defined(_FEATURE_SIE)*/
/* Prevent machine check when in (almost) interrupt loop */
realregs->instcount++;
/* Release any locks */
if (sysblk.intowner == realregs->cpuad)
RELEASE_INTLOCK(realregs);
if (sysblk.mainowner == realregs->cpuad)
RELEASE_MAINLOCK(realregs);
/* Ensure psw.IA is set and aia invalidated */
INVALIDATE_AIA(realregs);
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
if(realregs->sie_active)
INVALIDATE_AIA(realregs->guestregs);
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
/* Set instruction length (ilc) */
ilc = realregs->psw.zeroilc ? 0 : REAL_ILC(realregs);
if (realregs->psw.ilc == 0 && !realregs->psw.zeroilc)
{
/* This can happen if BALR, BASR, BASSM or BSM
program checks during trace */
ilc = likely(!realregs->execflag) ? 2 : realregs->exrl ? 6 : 4;
realregs->ip += ilc;
realregs->psw.IA += ilc;
realregs->psw.ilc = ilc;
}
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
if(realregs->sie_active)
{
sie_ilc = realregs->guestregs->psw.zeroilc ? 0 :
REAL_ILC(realregs->guestregs);
if (realregs->guestregs->psw.ilc == 0
&& !realregs->guestregs->psw.zeroilc)
{
sie_ilc = likely(!realregs->guestregs->execflag) ? 2 :
realregs->guestregs->exrl ? 6 : 4;
realregs->guestregs->psw.IA += sie_ilc; /* IanWorthington regression restored from 20081205 */
realregs->guestregs->psw.ilc = sie_ilc;
}
}
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
/* Set `execflag' to 0 in case EXecuted instruction program-checked */
realregs->execflag = 0;
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
if(realregs->sie_active)
realregs->guestregs->execflag = 0;
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
/* Unlock the main storage lock if held */
if (realregs->cpuad == sysblk.mainowner)
RELEASE_MAINLOCK(realregs);
/* Remove PER indication from program interrupt code
such that interrupt code specific tests may be done.
The PER indication will be stored in the PER handling
code */
code = pcode & ~PGM_PER_EVENT;
/* If this is a concurrent PER event then we must add the PER
bit to the interrupts code */
if( OPEN_IC_PER(realregs) )
pcode |= PGM_PER_EVENT;
/* Perform serialization and checkpoint synchronization */
PERFORM_SERIALIZATION (realregs);
PERFORM_CHKPT_SYNC (realregs);
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
/* Host protection and addressing exceptions must be
reflected to the guest */
if(realregs->sie_active &&
(code == PGM_PROTECTION_EXCEPTION
|| code == PGM_ADDRESSING_EXCEPTION
#if defined(_FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
|| code == PGM_ALET_SPECIFICATION_EXCEPTION
|| code == PGM_ALEN_TRANSLATION_EXCEPTION
|| code == PGM_ALE_SEQUENCE_EXCEPTION
|| code == PGM_EXTENDED_AUTHORITY_EXCEPTION
#endif /*defined(_FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
) )
{
#if defined(SIE_DEBUG)
logmsg(_("program_int() passing to guest code=%4.4X\n"),pcode);
#endif /*defined(SIE_DEBUG)*/
realregs->guestregs->TEA = realregs->TEA;
realregs->guestregs->excarid = realregs->excarid;
realregs->guestregs->opndrid = realregs->opndrid;
#if defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)
realregs->guestregs->hostint = 1;
#endif /*defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)*/
(realregs->guestregs->program_interrupt) (realregs->guestregs, pcode);
}
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
/* Back up the PSW for exceptions which cause nullification,
unless the exception occurred during instruction fetch */
if ((code == PGM_PAGE_TRANSLATION_EXCEPTION
|| code == PGM_SEGMENT_TRANSLATION_EXCEPTION
#if defined(FEATURE_ESAME)
|| code == PGM_ASCE_TYPE_EXCEPTION
|| code == PGM_REGION_FIRST_TRANSLATION_EXCEPTION
|| code == PGM_REGION_SECOND_TRANSLATION_EXCEPTION
|| code == PGM_REGION_THIRD_TRANSLATION_EXCEPTION
#endif /*defined(FEATURE_ESAME)*/
|| code == PGM_TRACE_TABLE_EXCEPTION
|| code == PGM_AFX_TRANSLATION_EXCEPTION
|| code == PGM_ASX_TRANSLATION_EXCEPTION
|| code == PGM_LX_TRANSLATION_EXCEPTION
|| code == PGM_LFX_TRANSLATION_EXCEPTION /*@ALR*/
|| code == PGM_LSX_TRANSLATION_EXCEPTION /*@ALR*/
|| code == PGM_LSTE_SEQUENCE_EXCEPTION /*@ALR*/
|| code == PGM_EX_TRANSLATION_EXCEPTION
|| code == PGM_PRIMARY_AUTHORITY_EXCEPTION
|| code == PGM_SECONDARY_AUTHORITY_EXCEPTION
|| code == PGM_ALEN_TRANSLATION_EXCEPTION
|| code == PGM_ALE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_VALIDITY_EXCEPTION
|| code == PGM_ASTE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_INSTANCE_EXCEPTION /*@ALR*/
|| code == PGM_EXTENDED_AUTHORITY_EXCEPTION
|| code == PGM_STACK_FULL_EXCEPTION
|| code == PGM_STACK_EMPTY_EXCEPTION
|| code == PGM_STACK_SPECIFICATION_EXCEPTION
|| code == PGM_STACK_TYPE_EXCEPTION
|| code == PGM_STACK_OPERATION_EXCEPTION
|| code == PGM_VECTOR_OPERATION_EXCEPTION)
&& !realregs->instinvalid)
{
realregs->psw.IA -= ilc;
realregs->psw.IA &= ADDRESS_MAXWRAP(realregs);
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
/* When in SIE mode the guest instruction causing this
host exception must also be nullified */
if(realregs->sie_active && !realregs->guestregs->instinvalid)
{
realregs->guestregs->psw.IA -= sie_ilc;
realregs->guestregs->psw.IA &= ADDRESS_MAXWRAP(realregs->guestregs);
}
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
}
/* The OLD PSW must be incremented on the following
exceptions during instfetch */
if(realregs->instinvalid &&
( code == PGM_PROTECTION_EXCEPTION
|| code == PGM_ADDRESSING_EXCEPTION
|| code == PGM_SPECIFICATION_EXCEPTION
|| code == PGM_TRANSLATION_SPECIFICATION_EXCEPTION ))
{
realregs->psw.IA += ilc;
realregs->psw.IA &= ADDRESS_MAXWRAP(realregs);
}
/* Store the interrupt code in the PSW */
realregs->psw.intcode = pcode;
/* Call debugger if active */
HDC2(debug_program_interrupt, regs, pcode);
/* Trace program checks other then PER event */
if(code && (CPU_STEPPING_OR_TRACING(realregs, ilc)
|| sysblk.pgminttr & ((U64)1 << ((code - 1) & 0x3F))))
{
BYTE *ip;
char buf1[10] = "";
char buf2[32] = "";
#if defined(OPTION_FOOTPRINT_BUFFER)
if(!(sysblk.insttrace || sysblk.inststep))
for(n = sysblk.footprptr[realregs->cpuad] + 1 ;
n != sysblk.footprptr[realregs->cpuad];
n++, n &= OPTION_FOOTPRINT_BUFFER - 1)
ARCH_DEP(display_inst)
(&sysblk.footprregs[realregs->cpuad][n],
sysblk.footprregs[realregs->cpuad][n].inst);
#endif /*defined(OPTION_FOOTPRINT_BUFFER)*/
#if defined(_FEATURE_SIE)
if (SIE_MODE(realregs))
strlcpy(buf1, "SIE: ", sizeof(buf1) );
#endif /*defined(_FEATURE_SIE)*/
#if defined(SIE_DEBUG)
strlcpy(buf2, QSTR(_GEN_ARCH), sizeof(buf2) );
strlcat(buf2, " ", sizeof(buf2) );
#endif /*defined(SIE_DEBUG)*/
if (code == PGM_DATA_EXCEPTION)
snprintf(dxcstr, sizeof(dxcstr), " DXC=%2.2X", regs->dxc);
dxcstr[sizeof(dxcstr)-1] = '\0';
/* Calculate instruction pointer */
ip = realregs->instinvalid ? NULL
: (realregs->ip - ilc < realregs->aip)
? realregs->inst : realregs->ip - ilc;
/* Trace pgm interrupt if not being specially suppressed */
if (0
|| !ip
|| ip[0] != 0xB1 /* LRA */
|| code != PGM_SPECIAL_OPERATION_EXCEPTION
|| !sysblk.nolrasoe /* suppression not requested */
)
{
// "Processor %s%02X: %s%s %s code %4.4X ilc %d%s"
WRMSG(HHC00801, "I",
PTYPSTR(realregs->cpuad), realregs->cpuad, buf1, buf2,
pgmintname[ (code - 1) & 0x3F], pcode, ilc, dxcstr);
ARCH_DEP(display_inst) (realregs, ip);
}
}
realregs->instinvalid = 0;
#if defined(FEATURE_INTERPRETIVE_EXECUTION)
/* If this is a host exception in SIE state then leave SIE */
if(realregs->sie_active)
ARCH_DEP(sie_exit) (realregs, SIE_HOST_PGMINT);
#endif /*defined(FEATURE_INTERPRETIVE_EXECUTION)*/
/* Absolute address of prefix page */
px = realregs->PX;
/* If under SIE use translated to host absolute prefix */
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs))
px = regs->sie_px;
#endif
#if defined(_FEATURE_SIE)
if(!SIE_MODE(regs) ||
/* Interception is mandatory for the following exceptions */
(
#if defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)
!(code == PGM_PROTECTION_EXCEPTION
&& (!SIE_FEATB(regs, EC2, PROTEX)
|| realregs->hostint))
#else /*!defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)*/
code != PGM_PROTECTION_EXCEPTION
#endif /*!defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)*/
#if defined (_FEATURE_PER2)
&& !((pcode & PGM_PER_EVENT) && SIE_FEATB(regs, M, GPE))
#endif /* defined (_FEATURE_PER2) */
&& code != PGM_ADDRESSING_EXCEPTION
&& code != PGM_SPECIFICATION_EXCEPTION
&& code != PGM_SPECIAL_OPERATION_EXCEPTION
#ifdef FEATURE_VECTOR_FACILITY
&& code != PGM_VECTOR_OPERATION_EXCEPTION
#endif /*FEATURE_VECTOR_FACILITY*/
#if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
&& !(code == PGM_ALEN_TRANSLATION_EXCEPTION
&& SIE_FEATB(regs, MX, XC))
&& !(code == PGM_ALE_SEQUENCE_EXCEPTION
&& SIE_FEATB(regs, MX, XC))
&& !(code == PGM_EXTENDED_AUTHORITY_EXCEPTION
&& SIE_FEATB(regs, MX, XC))
#endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
/* And conditional for the following exceptions */
&& !(code == PGM_OPERATION_EXCEPTION
&& SIE_FEATB(regs, IC0, OPEREX))
&& !(code == PGM_PRIVILEGED_OPERATION_EXCEPTION
&& SIE_FEATB(regs, IC0, PRIVOP))
#ifdef FEATURE_BASIC_FP_EXTENSIONS
&& !(code == PGM_DATA_EXCEPTION
&& (regs->dxc == 1 || regs->dxc == 2)
&& (regs->CR(0) & CR0_AFP)
&& !(regs->hostregs->CR(0) & CR0_AFP))
#endif /*FEATURE_BASIC_FP_EXTENSIONS*/
/* Or all exceptions if requested as such */
&& !SIE_FEATB(regs, IC0, PGMALL) )
)
{
#endif /*defined(_FEATURE_SIE)*/
/* Set the main storage reference and change bits */
STORAGE_KEY(px, regs) |= (STORKEY_REF | STORKEY_CHANGE);
/* Point to PSA in main storage */
psa = (void*)(regs->mainstor + px);
#if defined(_FEATURE_SIE)
#if defined(FEATURE_ESAME)
/** FIXME : SEE ISW20090110-1 */
if(code == PGM_MONITOR_EVENT)
{
zmoncode=psa->moncode;
}
#endif
nointercept = 1;
}
else
{
/* This is a guest interruption interception so point to
the interruption parm area in the state descriptor
rather then the PSA, except for the operation exception */
if(code != PGM_OPERATION_EXCEPTION)
{
psa = (void*)(regs->hostregs->mainstor + SIE_STATE(regs) + SIE_IP_PSA_OFFSET);
/* Set the main storage reference and change bits */
STORAGE_KEY(SIE_STATE(regs), regs->hostregs) |= (STORKEY_REF | STORKEY_CHANGE);
#if defined(FEATURE_ESAME)
/** FIXME : SEE ISW20090110-1 */
if(code == PGM_MONITOR_EVENT)
{
PSA *_psa;
_psa=(void *)(regs->hostregs->mainstor + SIE_STATE(regs) + SIE_II_PSA_OFFSET);
zmoncode=_psa->ioid;
}
#endif
}
else
{
/* Point to PSA in main storage */
psa = (void*)(regs->mainstor + px);
/* Set the main storage reference and change bits */
STORAGE_KEY(px, regs) |= (STORKEY_REF | STORKEY_CHANGE);
}
nointercept = 0;
}
#endif /*defined(_FEATURE_SIE)*/
#if defined(_FEATURE_PER)
/* Handle PER or concurrent PER event */
/* Throw out Stor Alter PER if merged with nullified/suppressed rupt */
if ( IS_IC_PER_SA(realregs) && !IS_IC_PER_STURA(realregs) &&
(realregs->ip[0] != 0x0E) &&
!(code == 0x00 || code == 0x06 || code == 0x08 || code == 0x0A ||
code == 0x0C || code == 0x0D || code == 0x0E || code == 0x1C ||
code == 0x40) )
OFF_IC_PER_SA(realregs);
if( OPEN_IC_PER(realregs) )
{
if( CPU_STEPPING_OR_TRACING(realregs, ilc) )
WRMSG(HHC00802, "I", PTYPSTR(regs->cpuad), regs->cpuad,
pcode, IS_IC_PER(realregs) >> 16,
(realregs->psw.IA - ilc) & ADDRESS_MAXWRAP(realregs) );
realregs->perc |= OPEN_IC_PER(realregs) >> ((32 - IC_CR9_SHIFT) - 16);
/* Positions 14 and 15 contain zeros if a storage alteration
event was not indicated */
//FIXME: is this right??
if( !(OPEN_IC_PER_SA(realregs))
|| (OPEN_IC_PER_STURA(realregs)) )
realregs->perc &= 0xFFFC;
STORE_HW(psa->perint, realregs->perc);
STORE_W(psa->peradr, realregs->peradr);
if( IS_IC_PER_SA(realregs) && ACCESS_REGISTER_MODE(&realregs->psw) )
psa->perarid = realregs->peraid;
#if defined(_FEATURE_SIE)
/* Reset PER pending indication */
if(nointercept)
OFF_IC_PER(realregs);
#endif
}
else
{
pcode &= 0xFF7F;
}
#endif /*defined(_FEATURE_PER)*/
#if defined(FEATURE_BCMODE)
/* For ECMODE, store extended interrupt information in PSA */
if ( ECMODE(&realregs->psw) )
#endif /*defined(FEATURE_BCMODE)*/
{
/* Store the program interrupt code at PSA+X'8C' */
psa->pgmint[0] = 0;
psa->pgmint[1] = ilc;
STORE_HW(psa->pgmint + 2, pcode);
/* Store the exception access identification at PSA+160 */
if ( code == PGM_PAGE_TRANSLATION_EXCEPTION
|| code == PGM_SEGMENT_TRANSLATION_EXCEPTION
#if defined(FEATURE_ESAME)
|| code == PGM_ASCE_TYPE_EXCEPTION
|| code == PGM_REGION_FIRST_TRANSLATION_EXCEPTION
|| code == PGM_REGION_SECOND_TRANSLATION_EXCEPTION
|| code == PGM_REGION_THIRD_TRANSLATION_EXCEPTION
#endif /*defined(FEATURE_ESAME)*/
|| code == PGM_ALEN_TRANSLATION_EXCEPTION
|| code == PGM_ALE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_VALIDITY_EXCEPTION
|| code == PGM_ASTE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_INSTANCE_EXCEPTION /*@ALR*/
|| code == PGM_EXTENDED_AUTHORITY_EXCEPTION
#ifdef FEATURE_SUPPRESSION_ON_PROTECTION
|| code == PGM_PROTECTION_EXCEPTION
#endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
)
{
psa->excarid = regs->excarid;
if(regs->TEA | TEA_MVPG)
psa->opndrid = regs->opndrid;
realregs->opndrid = 0;
}
#if defined(FEATURE_ESAME)
/* Store the translation exception address at PSA+168 */
if ( code == PGM_PAGE_TRANSLATION_EXCEPTION
|| code == PGM_SEGMENT_TRANSLATION_EXCEPTION
|| code == PGM_ASCE_TYPE_EXCEPTION
|| code == PGM_REGION_FIRST_TRANSLATION_EXCEPTION
|| code == PGM_REGION_SECOND_TRANSLATION_EXCEPTION
|| code == PGM_REGION_THIRD_TRANSLATION_EXCEPTION
#ifdef FEATURE_SUPPRESSION_ON_PROTECTION
|| code == PGM_PROTECTION_EXCEPTION
#endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
)
{
STORE_DW(psa->TEA_G, regs->TEA);
}
/* Store the translation exception address at PSA+172 */
if ( code == PGM_AFX_TRANSLATION_EXCEPTION
|| code == PGM_ASX_TRANSLATION_EXCEPTION
|| code == PGM_PRIMARY_AUTHORITY_EXCEPTION
|| code == PGM_SECONDARY_AUTHORITY_EXCEPTION
|| code == PGM_SPACE_SWITCH_EVENT
|| code == PGM_LX_TRANSLATION_EXCEPTION
|| code == PGM_LFX_TRANSLATION_EXCEPTION /*@ALR*/
|| code == PGM_LSX_TRANSLATION_EXCEPTION /*@ALR*/
|| code == PGM_LSTE_SEQUENCE_EXCEPTION /*@ALR*/
|| code == PGM_EX_TRANSLATION_EXCEPTION)
{
STORE_FW(psa->TEA_L, regs->TEA);
}
#else /*!defined(FEATURE_ESAME)*/
/* Store the translation exception address at PSA+144 */
if ( code == PGM_PAGE_TRANSLATION_EXCEPTION
|| code == PGM_SEGMENT_TRANSLATION_EXCEPTION
|| code == PGM_AFX_TRANSLATION_EXCEPTION
|| code == PGM_ASX_TRANSLATION_EXCEPTION
|| code == PGM_PRIMARY_AUTHORITY_EXCEPTION
|| code == PGM_SECONDARY_AUTHORITY_EXCEPTION
|| code == PGM_SPACE_SWITCH_EVENT
|| code == PGM_LX_TRANSLATION_EXCEPTION
|| code == PGM_EX_TRANSLATION_EXCEPTION
#ifdef FEATURE_SUPPRESSION_ON_PROTECTION
|| code == PGM_PROTECTION_EXCEPTION
#endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
)
{
STORE_FW(psa->tea, regs->TEA);
}
#endif /*!defined(FEATURE_ESAME)*/
realregs->TEA = 0;
/* Store Data exception code in PSA */
if (code == PGM_DATA_EXCEPTION)
{
STORE_FW(psa->DXC, regs->dxc);
#ifdef FEATURE_BASIC_FP_EXTENSIONS
/* Load data exception code into FPC register byte 2 */
if(regs->CR(0) & CR0_AFP)
{
regs->fpc &= ~(FPC_DXC);
regs->fpc |= ((regs->dxc << 8)) & FPC_DXC;
}
#endif /*FEATURE_BASIC_FP_EXTENSIONS*/
}
/* Store the monitor class and event code */
if (code == PGM_MONITOR_EVENT)
{
STORE_HW(psa->monclass, regs->monclass);
/* Store the monitor code word at PSA+156 */
/* or doubleword at PSA+176 */
/* ISW20090110-1 ZSIEMCFIX */
/* In the event of a z/Arch guest being */
/* intercepted during a succesful Monitor */
/* call, the monitor code is not stored */
/* at psa->moncode (which is beyond sie2bk->ip */
/* but rather at the same location as an */
/* I/O interrupt would store the SSID */
/* zmoncode points to this location */
/* **** FIXME **** FIXME *** FIXME *** */
/* ---- The determination of the location */
/* of the z/Sie Intercept moncode */
/* should be made more flexible */
/* and should be put somewhere in */
/* esa390.h */
/* **** FIXME **** FIXME *** FIXME *** */
#if defined(FEATURE_ESAME)
STORE_DW(zmoncode, regs->MONCODE);
#else
STORE_W(psa->moncode, regs->MONCODE);
#endif
}
#if defined(FEATURE_PER3)
/* Store the breaking event address register in the PSA */
SET_BEAR_REG(regs, regs->bear_ip);
STORE_W(psa->bea, regs->bear);
#endif /*defined(FEATURE_PER3)*/
} /* end if(ECMODE) */
#if defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)
realregs->hostint = 0;
#endif /*defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)*/
#if defined(_FEATURE_SIE)
if(nointercept)
#endif /*defined(_FEATURE_SIE)*/
{
PSW pgmold, pgmnew;
int pgmintloop = 0;
int detect_pgmintloop = FACILITY_ENABLED( DETECT_PGMINTLOOP, realregs );
/* Store current PSW at PSA+X'28' or PSA+X'150' for ESAME */
ARCH_DEP(store_psw) (realregs, psa->pgmold);
/* Save program old psw */
if (detect_pgmintloop)
{
memcpy( &pgmold, &realregs->psw, sizeof( PSW ));
pgmold.cc = 0;
pgmold.intcode = 0;
pgmold.ilc = 0;
pgmold.unused = 0;
}
/* Load new PSW from PSA+X'68' or PSA+X'1D0' for ESAME */
if ( (code = ARCH_DEP(load_psw) (realregs, psa->pgmnew)) )
{
#if defined(_FEATURE_SIE)
if(SIE_MODE(realregs))
{
longjmp(realregs->progjmp, pcode);
}
else
#endif /*defined(_FEATURE_SIE)*/
/* Invalid pgmnew ==> program interrupt loop */
pgmintloop = detect_pgmintloop;
}
else if (detect_pgmintloop)
{
/* Save program new psw */
memcpy( &pgmnew, &realregs->psw, sizeof( PSW ));
pgmnew.cc = 0;
pgmnew.intcode = 0;
pgmnew.ilc = 0;
pgmnew.unused = 0;
/* Adjust pgmold instruction address */
pgmold.ia.D -= ilc;
/* Check for program interrupt loop (old==new) */
if (memcmp( &pgmold, &pgmnew, sizeof( PSW )) == 0)
pgmintloop = 1;
}
if (pgmintloop)
{
char buf[64];
// "Processor %s%02X: program interrupt loop PSW %s"
WRMSG(HHC00803, "I", PTYPSTR(realregs->cpuad), realregs->cpuad,
str_psw (realregs, buf));
OBTAIN_INTLOCK(realregs);
realregs->cpustate = CPUSTATE_STOPPING;
ON_IC_INTERRUPT(realregs);
RELEASE_INTLOCK(realregs);
}
longjmp(realregs->progjmp, SIE_NO_INTERCEPT);
}
#if defined(_FEATURE_SIE)
longjmp (realregs->progjmp, pcode);
#endif /*defined(_FEATURE_SIE)*/
} /* end function ARCH_DEP(program_interrupt) */