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torvaldstorvalds
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Merge tag 'loongarch-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch updates from Huacai Chen: - Migrate to the generic rule for built-in DTB - Disable FIX_EARLYCON_MEM when ARCH_IOREMAP is enabled - Derive timer max_delta from PRCFG1's timer_bits - Correct the cacheinfo sharing information - Add pgprot_nx() implementation - Add debugfs entries to switch SFB/TSO state - Change the maximum number of watchpoints - Some bug fixes and other small changes * tag 'loongarch-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: LoongArch: Extend the maximum number of watchpoints LoongArch: Change 8 to 14 for LOONGARCH_MAX_{BRP,WRP} LoongArch: Add debugfs entries to switch SFB/TSO state LoongArch: Fix warnings during S3 suspend LoongArch: Adjust SETUP_SLEEP and SETUP_WAKEUP LoongArch: Refactor bug_handler() implementation LoongArch: Add pgprot_nx() implementation LoongArch: Correct the __switch_to() prototype in comments LoongArch: Correct the cacheinfo sharing information LoongArch: Derive timer max_delta from PRCFG1's timer_bits LoongArch: Disable FIX_EARLYCON_MEM when ARCH_IOREMAP is enabled LoongArch: Migrate to the generic rule for built-in DTB
2 parents a37eea9 + 531936d commit 9ff28f2

22 files changed

+312
-31
lines changed

‎arch/loongarch/Kbuild

-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@ obj-y += net/
44
obj-y += vdso/
55

66
obj-$(CONFIG_KVM) += kvm/
7-
obj-$(CONFIG_BUILTIN_DTB) += boot/dts/
87

98
# for cleaning
109
subdir- += boot

‎arch/loongarch/Kconfig

+2-1
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ config MACH_LOONGSON64
249249
def_bool 64BIT
250250

251251
config FIX_EARLYCON_MEM
252-
def_bool y
252+
def_bool !ARCH_IOREMAP
253253

254254
config PGTABLE_2LEVEL
255255
bool
@@ -400,6 +400,7 @@ endchoice
400400
config BUILTIN_DTB
401401
bool "Enable built-in dtb in kernel"
402402
depends on OF
403+
select GENERIC_BUILTIN_DTB
403404
help
404405
Some existing systems do not provide a canonical device tree to
405406
the kernel at boot time. Let's provide a device tree table in the

‎arch/loongarch/boot/dts/Makefile

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
11
# SPDX-License-Identifier: GPL-2.0-only
22

33
dtb-y = loongson-2k0500-ref.dtb loongson-2k1000-ref.dtb loongson-2k2000-ref.dtb
4-
5-
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))

‎arch/loongarch/include/asm/cpu-info.h

+1
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ struct cpuinfo_loongarch {
5757
int global_id; /* physical global thread number */
5858
int vabits; /* Virtual Address size in bits */
5959
int pabits; /* Physical Address size in bits */
60+
int timerbits; /* Width of arch timer in bits */
6061
unsigned int ksave_mask; /* Usable KSave mask. */
6162
unsigned int watch_dreg_count; /* Number data breakpoints */
6263
unsigned int watch_ireg_count; /* Number instruction breakpoints */

‎arch/loongarch/include/asm/hw_breakpoint.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ struct arch_hw_breakpoint {
3838
* Limits.
3939
* Changing these will require modifications to the register accessors.
4040
*/
41-
#define LOONGARCH_MAX_BRP 8
42-
#define LOONGARCH_MAX_WRP 8
41+
#define LOONGARCH_MAX_BRP 14
42+
#define LOONGARCH_MAX_WRP 14
4343

4444
/* Virtual debug register bases. */
4545
#define CSR_CFG_ADDR 0

‎arch/loongarch/include/asm/loongarch.h

+75-1
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,12 @@
108108
#define CPUCFG3_SPW_HG_HF BIT(11)
109109
#define CPUCFG3_RVA BIT(12)
110110
#define CPUCFG3_RVAMAX GENMASK(16, 13)
111+
#define CPUCFG3_ALDORDER_CAP BIT(18) /* All address load ordered, capability */
112+
#define CPUCFG3_ASTORDER_CAP BIT(19) /* All address store ordered, capability */
113+
#define CPUCFG3_ALDORDER_STA BIT(20) /* All address load ordered, status */
114+
#define CPUCFG3_ASTORDER_STA BIT(21) /* All address store ordered, status */
115+
#define CPUCFG3_SLDORDER_CAP BIT(22) /* Same address load ordered, capability */
116+
#define CPUCFG3_SLDORDER_STA BIT(23) /* Same address load ordered, status */
111117

112118
#define LOONGARCH_CPUCFG4 0x4
113119
#define CPUCFG4_CCFREQ GENMASK(31, 0)
@@ -466,7 +472,6 @@
466472

467473
#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
468474
#define CSR_TCFG_VAL_SHIFT 2
469-
#define CSR_TCFG_VAL_WIDTH 48
470475
#define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
471476
#define CSR_TCFG_PERIOD_SHIFT 1
472477
#define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
@@ -566,6 +571,15 @@
566571

567572
/* Implement dependent */
568573
#define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
574+
#define CSR_LDSTORDER_SHIFT 28
575+
#define CSR_LDSTORDER_WIDTH 3
576+
#define CSR_LDSTORDER_MASK (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT)
577+
#define CSR_LDSTORDER_NLD_NST (_ULCAST_(0x0) << CSR_LDSTORDER_SHIFT) /* 000 = No Load No Store */
578+
#define CSR_LDSTORDER_ALD_NST (_ULCAST_(0x1) << CSR_LDSTORDER_SHIFT) /* 001 = All Load No Store */
579+
#define CSR_LDSTORDER_SLD_NST (_ULCAST_(0x3) << CSR_LDSTORDER_SHIFT) /* 011 = Same Load No Store */
580+
#define CSR_LDSTORDER_NLD_AST (_ULCAST_(0x4) << CSR_LDSTORDER_SHIFT) /* 100 = No Load All Store */
581+
#define CSR_LDSTORDER_ALD_AST (_ULCAST_(0x5) << CSR_LDSTORDER_SHIFT) /* 101 = All Load All Store */
582+
#define CSR_LDSTORDER_SLD_AST (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT) /* 111 = Same Load All Store */
569583
#define CSR_MISPEC_SHIFT 20
570584
#define CSR_MISPEC_WIDTH 8
571585
#define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
@@ -959,6 +973,36 @@
959973
#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
960974
#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
961975

976+
#define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
977+
#define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
978+
#define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
979+
#define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */
980+
981+
#define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
982+
#define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
983+
#define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
984+
#define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */
985+
986+
#define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
987+
#define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
988+
#define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
989+
#define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */
990+
991+
#define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
992+
#define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
993+
#define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
994+
#define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */
995+
996+
#define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
997+
#define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
998+
#define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
999+
#define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */
1000+
1001+
#define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
1002+
#define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
1003+
#define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
1004+
#define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */
1005+
9621006
#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
9631007
#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
9641008

@@ -1002,6 +1046,36 @@
10021046
#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
10031047
#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
10041048

1049+
#define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
1050+
#define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
1051+
#define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
1052+
#define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */
1053+
1054+
#define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
1055+
#define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
1056+
#define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
1057+
#define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */
1058+
1059+
#define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
1060+
#define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
1061+
#define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
1062+
#define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */
1063+
1064+
#define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
1065+
#define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
1066+
#define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
1067+
#define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */
1068+
1069+
#define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
1070+
#define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
1071+
#define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
1072+
#define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */
1073+
1074+
#define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
1075+
#define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
1076+
#define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
1077+
#define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
1078+
10051079
#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
10061080
#define LOONGARCH_CSR_DERA 0x501 /* debug era */
10071081
#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */

‎arch/loongarch/include/asm/pgtable-bits.h

+7
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,13 @@
9696

9797
#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_SUC)
9898

99+
#define pgprot_nx pgprot_nx
100+
101+
static inline pgprot_t pgprot_nx(pgprot_t _prot)
102+
{
103+
return __pgprot(pgprot_val(_prot) | _PAGE_NO_EXEC);
104+
}
105+
99106
#define pgprot_noncached pgprot_noncached
100107

101108
static inline pgprot_t pgprot_noncached(pgprot_t _prot)

‎arch/loongarch/include/uapi/asm/ptrace.h

+10
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,16 @@ struct user_watch_state {
7272
} dbg_regs[8];
7373
};
7474

75+
struct user_watch_state_v2 {
76+
uint64_t dbg_info;
77+
struct {
78+
uint64_t addr;
79+
uint64_t mask;
80+
uint32_t ctrl;
81+
uint32_t pad;
82+
} dbg_regs[14];
83+
};
84+
7585
#define PTRACE_SYSEMU 0x1f
7686
#define PTRACE_SYSEMU_SINGLESTEP 0x20
7787

‎arch/loongarch/kernel/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ extra-y := vmlinux.lds
1010
obj-y += head.o cpu-probe.o cacheinfo.o env.o setup.o entry.o genex.o \
1111
traps.o irq.o idle.o process.o dma.o mem.o reset.o switch.o \
1212
elf.o syscall.o signal.o time.o topology.o inst.o ptrace.o vdso.o \
13-
alternative.o unwind.o
13+
alternative.o kdebugfs.o unwind.o
1414

1515
obj-$(CONFIG_ACPI) += acpi.o
1616
obj-$(CONFIG_EFI) += efi.o

‎arch/loongarch/kernel/cacheinfo.c

+6
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,12 @@ static void cache_cpumap_setup(unsigned int cpu)
5151
continue;
5252

5353
sib_leaf = sib_cpu_ci->info_list + index;
54+
/* SMT cores share all caches */
55+
if (cpus_are_siblings(i, cpu)) {
56+
cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
57+
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
58+
}
59+
/* Node's cores share shared caches */
5460
if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
5561
cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
5662
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);

‎arch/loongarch/kernel/cpu-probe.c

+1
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
190190
set_cpu_asid_mask(c, asid_mask);
191191

192192
config = read_csr_prcfg1();
193+
c->timerbits = (config & CSR_CONF1_TMRBITS) >> CSR_CONF1_TMRBITS_SHIFT;
193194
c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
194195
c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
195196

‎arch/loongarch/kernel/hw_breakpoint.c

+14-2
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type)
5151
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
5252
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
5353
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
54-
READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
54+
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
55+
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
56+
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
57+
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
58+
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
59+
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
60+
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);
5561

5662
#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
5763
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
@@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type)
6167
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
6268
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
6369
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
64-
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
70+
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
71+
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
72+
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
73+
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
74+
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
75+
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
76+
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);
6577

6678
static u64 read_wb_reg(int reg, int n, int t)
6779
{

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