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org_theopenroadproject_asap7_pdk_r1p7 Expand file tree Collapse file tree 3 files changed +7
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lines changed Original file line number Diff line number Diff line change @@ -54,6 +54,7 @@ def _skywater_corner_impl(ctx):
5454 inputs = ctx .files .srcs ,
5555 arguments = [args ],
5656 executable = ctx .executable ._liberty_tool ,
57+ use_default_shell_env = True ,
5758 )
5859
5960 return [
Original file line number Diff line number Diff line change @@ -247,6 +247,7 @@ def _asap7_cell_library_impl(ctx):
247247 inputs = default_corner_libraries ,
248248 arguments = [args ],
249249 executable = ctx .executable ._combine_liberty ,
250+ use_default_shell_env = True ,
250251 )
251252
252253 open_road_configuration = None
Original file line number Diff line number Diff line change @@ -363,6 +363,11 @@ synthesize_rtl = rule(
363363 "deps" : attr .label_list (
364364 providers = [[VerilogInfo ], [UhdmInfo ]],
365365 ),
366+ "early_techmap" : attr .label (
367+ allow_single_file = True ,
368+ doc = "verilog/system verilog file for early techmap process" ,
369+ mandatory = False ,
370+ ),
366371 "extra_tcl_command" : attr .string (
367372 default = "" ,
368373 ),
@@ -399,11 +404,6 @@ synthesize_rtl = rule(
399404 executable = True ,
400405 cfg = "exec" ,
401406 ),
402- "early_techmap" : attr .label (
403- allow_single_file = True ,
404- mandatory = False ,
405- doc = "verilog/system verilog file for early techmap process"
406- ),
407407 },
408408)
409409
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