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kimchi_ulid.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# GG_LOGO
#
DEF GG_LOGO L 0 40 Y Y 1 F N
F0 "L" 0 0 50 H V C CNN
F1 "GG_LOGO" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 0 50 0 0 0 G Normal 0 C C
ENDDRAW
ENDDEF
#
# JST-GH-6
#
DEF JST-GH-6 J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "JST-GH-6" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 50 -350 1 1 10 f
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 -200 -300 150 R 50 50 1 1 P
X GND MP 150 -50 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# KIMCHI_MICRO
#
DEF KIMCHI_MICRO K 0 40 Y Y 1 F N
F0 "K" 0 0 50 H V C CNN
F1 "KIMCHI_MICRO" 0 0 50 H V C CNN
F2 "kimchi_ulid:KIMCHI_MICRO" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
ENDDRAW
ENDDEF
#
# NVCC_1V8
#
DEF NVCC_1V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_1V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_1V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# NVCC_3V3
#
DEF NVCC_3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# NVCC_DRAM_1V1
#
DEF NVCC_DRAM_1V1 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_DRAM_1V1" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_DRAM_1V1 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# NVCC_ENET
#
DEF NVCC_ENET #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_ENET" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_ENET 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# NVCC_SD2
#
DEF NVCC_SD2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_SD2" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_SD2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# NVCC_SNVS_1V8
#
DEF NVCC_SNVS_1V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "NVCC_SNVS_1V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X NVCC_SNVS_1V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# PTN5110NHQZ
#
DEF PTN5110NHQZ U 0 40 Y Y 1 F N
F0 "U" -50 -950 50 H V C CNN
F1 "PTN5110NHQZ" -50 -950 50 H V C CNN
F2 "" -50 -950 50 H I C CNN
F3 "" -50 -950 50 H I C CNN
DRAW
S -750 750 750 -900 0 1 0 N
X FRS_EN 1 950 350 200 L 50 50 1 1 O
X ~ALERT 10 950 -450 200 L 50 50 1 1 O
X ~FAULT 11 950 600 200 L 50 50 1 1 C
X VCONN_IN 12 -950 -550 200 R 50 50 1 1 I
X CC1 13 -950 -200 200 R 50 50 1 1 B
X CC2 14 -950 -300 200 R 50 50 1 1 B
X VBUS 15 -950 650 200 R 50 50 1 1 W
X EN_SRC 16 100 950 200 D 50 50 1 1 O
X GND 17 -950 -750 200 R 50 50 1 1 P
X EN_SINK 2 200 950 200 D 50 50 1 1 O
X VDD 3 -950 400 200 R 50 50 1 1 W
X BYPASS 4 -950 150 200 R 50 50 1 1 P
X SLV_ADDR 5 950 -200 200 L 50 50 1 1 P
X ILIM_5V_VBUS 6 950 -100 200 L 50 50 1 1 P
X I2C_SDA 7 950 -750 200 L 50 50 1 1 B
X I2C_SCL 8 950 -650 200 L 50 50 1 1 I
X DBG_ACC 9 950 250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# SN65DSI86ZQER
#
DEF SN65DSI86ZQER U 0 40 Y Y 1 L N
F0 "U" -628 1752 50 H V L BNN
F1 "SN65DSI86ZQER" -596 -2192 50 H V L BNN
F2 "BGA64C50P9X9_500X500X100" 0 0 50 H I L BNN
F3 "Texas Instruments" 0 0 50 H I L BNN
F4 "Dual-Channel MIPI® DSI to Embedded DisplayPort™ _eDP _ Bridge 64-BGA MICROSTAR JUNIOR -40 to 85" 0 0 50 H I L BNN
F5 "BGA-64 Texas Instruments" 0 0 50 H I L BNN
F6 "None" 0 0 50 H I L BNN
F7 "SN65DSI86ZQER" 0 0 50 H I L BNN
F8 "Unavailable" 0 0 50 H I L BNN
DRAW
P 2 0 0 10 -600 -2100 -600 1700 N
P 2 0 0 10 -600 1700 600 1700 N
P 2 0 0 10 600 -2100 -600 -2100 N
P 2 0 0 10 600 1700 600 -2100 N
X ADDR A1 -700 -1100 100 R 40 40 0 0 I
X VCCIO A2 700 1200 100 L 40 40 0 0 W
X IRQ A3 700 -800 100 L 40 40 0 0 O
X GPIO1 A4 700 -300 100 L 40 40 0 0 I
X GPIO2 A5 700 -400 100 L 40 40 0 0 I
X GPIO3 A6 700 -500 100 L 40 40 0 0 I
X REFCLK A7 -700 300 100 R 40 40 0 0 I C
X GND A8 700 -2000 100 L 40 40 0 0 W
X VCCA A9 700 1300 100 L 40 40 0 0 W
X EN B1 -700 500 100 R 40 40 0 0 I
X VCCA B2 700 1300 100 L 40 40 0 0 W
X TEST1 B3 -700 -1800 100 R 40 40 0 0 I
X GPIO4 B4 700 -600 100 L 40 40 0 0 I
X TEST2 B5 -700 -1900 100 R 40 40 0 0 B
X VCCIO B6 700 1200 100 L 40 40 0 0 W
X TEST3 B7 -700 -2000 100 R 40 40 0 0 B
X ML3P B8 700 500 100 L 40 40 0 0 O
X ML3N B9 700 100 100 L 40 40 0 0 O
X DB0N C1 -700 -400 100 R 40 40 0 0 I
X DB0P C2 -700 1100 100 R 40 40 0 0 I
X ML2P C8 700 600 100 L 40 40 0 0 O
X ML2N C9 700 200 100 L 40 40 0 0 O
X DB1N D1 -700 -500 100 R 40 40 0 0 I
X DB1P D2 -700 1000 100 R 40 40 0 0 I
X VCC D5 700 1400 100 L 40 40 0 0 W
X VCC D6 700 1400 100 L 40 40 0 0 W
X GND D8 700 -2000 100 L 40 40 0 0 W
X VPLL D9 700 1100 100 L 40 40 0 0 W
X DBCN E1 -700 -800 100 R 40 40 0 0 I
X DBCP E2 -700 700 100 R 40 40 0 0 I
X GND E4 700 -2000 100 L 40 40 0 0 W
X GND E5 700 -2000 100 L 40 40 0 0 W
X VCCA E6 700 1300 100 L 40 40 0 0 W
X ML1P E8 700 700 100 L 40 40 0 0 O
X ML1N E9 700 300 100 L 40 40 0 0 O
X DB2N F1 -700 -600 100 R 40 40 0 0 I
X DB2P F2 -700 900 100 R 40 40 0 0 I
X GND F4 700 -2000 100 L 40 40 0 0 W
X GND F5 700 -2000 100 L 40 40 0 0 W
X GND F6 700 -2000 100 L 40 40 0 0 W
X ML0P F8 700 800 100 L 40 40 0 0 O
X ML0N F9 700 400 100 L 40 40 0 0 O
X DB3N G1 -700 -700 100 R 40 40 0 0 I
X DB3P G2 -700 800 100 R 40 40 0 0 I
X GND G8 700 -2000 100 L 40 40 0 0 W
X VCCA G9 700 1300 100 L 40 40 0 0 W
X SCL H1 -700 -1500 100 R 40 40 0 0 B C
X VCCA H2 700 1300 100 L 40 40 0 0 W
X DA0P H3 -700 1600 100 R 40 40 0 0 I
X DA1P H4 -700 1500 100 R 40 40 0 0 I
X DACP H5 -700 1200 100 R 40 40 0 0 I
X DA2P H6 -700 1400 100 R 40 40 0 0 I
X DA3P H7 -700 1300 100 R 40 40 0 0 I
X AUXP H8 -700 -1200 100 R 40 40 0 0 B
X AUXN H9 -700 -1300 100 R 40 40 0 0 B
X SDA J1 -700 -1600 100 R 40 40 0 0 B
X VCC J2 700 1400 100 L 40 40 0 0 W
X DA0N J3 -700 100 100 R 40 40 0 0 B
X DA1N J4 -700 0 100 R 40 40 0 0 I
X DACN J5 -700 -300 100 R 40 40 0 0 I
X DA2N J6 -700 -100 100 R 40 40 0 0 I
X DA3N J7 -700 -200 100 R 40 40 0 0 I
X HPD J8 -700 400 100 R 40 40 0 0 I
X VCC J9 700 1400 100 L 40 40 0 0 W
ENDDRAW
ENDDEF
#
# TS30013-M033QFNR
#
DEF TS30013-M033QFNR U 0 40 Y Y 1 F N
F0 "U" -400 650 50 H V C CNN
F1 "TS30013-M033QFNR" 0 -200 50 H V C CNN
F2 "Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias" 100 -1150 50 H I C CNN
F3 "" 0 -100 50 H I C CNN
DRAW
S -450 600 450 -600 0 1 0 N
X VSW 1 650 300 200 L 50 50 1 1 w
X BST 10 650 500 200 L 50 50 1 1 P
X VCC 11 -650 300 200 R 50 50 1 1 W
X VSW 12 650 200 200 L 50 50 1 1 w
X VSW 13 650 100 200 L 50 50 1 1 w
X PGND 14 50 -800 200 U 50 50 1 1 P
X PGND 15 150 -800 200 U 50 50 1 1 P
X VSW 16 650 0 200 L 50 50 1 1 w
X PAD 17 -50 -800 200 U 50 50 1 1 P
X VCC 2 -650 500 200 R 50 50 1 1 W
X VCC 3 -650 400 200 R 50 50 1 1 W
X GND 4 -150 -800 200 U 50 50 1 1 P
X FB 5 650 -300 200 L 50 50 1 1 w
X NC 6 -650 50 200 R 50 50 1 1 N
X NC 7 -650 -50 200 R 50 50 1 1 N
X PG 8 650 -500 200 L 50 50 1 1 C
X EN 9 -650 -500 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# VBUS_IN
#
DEF VBUS_IN #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VBUS_IN" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBUS_IN 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDDA_1V8
#
DEF VDDA_1V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDDA_1V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDDA_1V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDDEXT_3V3
#
DEF VDDEXT_3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDDEXT_3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDDEXT_3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_1V8
#
DEF VDD_1V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_1V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_1V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_3V3
#
DEF VDD_3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_5V
#
DEF VDD_5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_ARM_0V9
#
DEF VDD_ARM_0V9 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_ARM_0V9" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_ARM_0V9 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_DRAM&PU_0V9
#
DEF VDD_DRAM&PU_0V9 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_DRAM&PU_0V9" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_DRAM&PU_0V9 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_PCIE_1V5
#
DEF VDD_PCIE_1V5 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_PCIE_1V5" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_PCIE_1V5 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_PHY_0V9
#
DEF VDD_PHY_0V9 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_PHY_0V9" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_PHY_0V9 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_PHY_1V2
#
DEF VDD_PHY_1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_PHY_1V2" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_PHY_1V2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_SNVS_0V8
#
DEF VDD_SNVS_0V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_SNVS_0V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_SNVS_0V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VDD_SOC_0V8
#
DEF VDD_SOC_0V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VDD_SOC_0V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD_SOC_0V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VSYS_5V
#
DEF VSYS_5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VSYS_5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VSYS_5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library