diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 07a898465fe873..025edbfd5846ed 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -195,6 +195,9 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
+	// 10.1: Zihintpause Extension for Pause Hint
+	PAUSE						// 0f000001
+
 	// 12.3: Integer Conditional Operations (Zicond)
 	CZEROEQZ	X5, X6, X7			// b353530e
 	CZEROEQZ	X5, X7				// b3d3530e
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index a8807fc7a847f2..52efb45640823e 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -940,6 +940,7 @@ var Anames = []string{
 	"NEG",
 	"NEGW",
 	"NOT",
+	"PAUSE",
 	"RDCYCLE",
 	"RDINSTRET",
 	"RDTIME",
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 305ef061e3d8e9..045d847bb0f372 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -1504,6 +1504,7 @@ const (
 	ANEG
 	ANEGW
 	ANOT
+	APAUSE
 	ARDCYCLE
 	ARDINSTRET
 	ARDTIME
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index 9d595f301c4bfa..069b10537c2ea5 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -3732,6 +3732,10 @@ func instructionsForProg(p *obj.Prog) []*instruction {
 		}
 		ins.imm = -1
 
+	case APAUSE:
+		ins.as, ins.rd, ins.rs1, ins.rs2 = AFENCE, REG_ZERO, REG_ZERO, obj.REG_NONE
+		ins.imm = 0x010
+
 	case ASEQZ:
 		// SEQZ rs, rd -> SLTIU $1, rs, rd
 		ins.as = ASLTIU