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| 1 | +# CPU Registers |
| 2 | + |
| 3 | +Major types of computer registers in the microprocessor are: |
| 4 | + |
| 5 | +- `Memory Address Register` (MAR) |
| 6 | +- `Stack Control Register` (ACR) |
| 7 | +- `Memory Data Register` (MDR) |
| 8 | +- `Flag Register` (FR) |
| 9 | +- `Accumulator Register` (AC) |
| 10 | +- `Instruction Pointer Register` (IPR) |
| 11 | +- `Data Register` (DR) |
| 12 | +- `Address Register` or `Segment Register` (AR or SR) |
| 13 | +- `Memory Buffer Register` (MBR) |
| 14 | +- `Index Register` (IR) |
| 15 | +- `Program Counter` (PC) |
| 16 | + |
| 17 | +### Memory Address Register or `MAR` |
| 18 | + |
| 19 | +This Register is used to hold memory addresses from data and instructions. |
| 20 | +The purpose of this Register is to access data and instructions from RAM during |
| 21 | +the execution process of instructions. For example, the CPU needs to store some data in RAM, |
| 22 | +or vice versa. When it wants to retrieve data from RAM. |
| 23 | +MAR stores that data temporarily. Because if MAR did not do this, |
| 24 | +the CPU won’t know where the instructions should be stored in RAM. |
| 25 | +So logically, there is a registry called MAR. |
| 26 | + |
| 27 | +### Stack Control Register or `SCR` |
| 28 | + |
| 29 | +A stack is a set of a memory location in which data is stored and retrieved in order. |
| 30 | +This order is called Last-In-First-Out (LIFO). The data item stored at the top of the stack |
| 31 | +is retrieved before retrieving the item below it. Furthermore, stack control registers are used |
| 32 | +to manage the stack inside the computer. |
| 33 | + |
| 34 | +Two special registers SP and BP are used for this purpose. |
| 35 | +DI, SI, SP, and BP can either be used as 2-byte registers or 4-byte registers. |
| 36 | +The names of 4-byte stack control registers are EDI, ESI, ESP, and EBP. |
| 37 | + |
| 38 | +### Memory Data Register or `MDR` |
| 39 | + |
| 40 | +This type of Register is considered to be the most important CPU registers. |
| 41 | +The MDR register is like the CU unit register of the processor and stores information |
| 42 | +that must be stored in the system RAM or other memory. MDR also contains data that can be fetched |
| 43 | +or already fetched from a storage device. |
| 44 | + |
| 45 | +The MDR register works like a buffer and holds a copy of information shifted from RAM to the register |
| 46 | +during the `Fetch` operations being processed by the CPU. |
| 47 | + |
| 48 | +### Flag Register or `FR` |
| 49 | + |
| 50 | +Flag registers are used to indicate a particular condition. The size of the flag register |
| 51 | +is one or two bytes. Each byte of flag registers is further divided into eight bits. |
| 52 | +Each bit of the flag register indicates a flag or condition. |
| 53 | + |
| 54 | +In addition, the data in the flag register is stored in 8 distinct bits. |
| 55 | +Some flag registers are Zero flags, Carry flag, Parity flag, Sign flag, and Overflow flag. |
| 56 | + |
| 57 | +### Accumulator Register or `AC` |
| 58 | + |
| 59 | +The function of accumulative registers is to handle mathematical and logical operations. |
| 60 | +These registers are part of ALU. Almost, there are four types of |
| 61 | +accumulative registers called EAX, EBX, ECX, and EDX. |
| 62 | +The size of these registers can be 1 to 4 bytes. |
| 63 | + |
| 64 | +The two-byte data registers (AX, BX, CX, DX) contain two parts of an 8-bit size. |
| 65 | +Furthermore, these parts are separately accessible. |
| 66 | +The lower order bytes are designated as AL, BL, CL, and DL. |
| 67 | +The high-order bytes are designated as AH, BH, CH, and DH. |
| 68 | + |
| 69 | +### Instruction Pointer Register or `IPR` |
| 70 | + |
| 71 | +The instruction pointer register is used to store the memory location of the next instruction |
| 72 | +to be executed. It is a special register that holds a sequence of instructions to be performed. |
| 73 | +It almost works along with the segment registers. |
| 74 | + |
| 75 | +### Data Register or `DX` |
| 76 | + |
| 77 | +This type of CPU register is used to store data read or written from storage devices temporarily. |
| 78 | +In technical terms, The Data Register is also known as DX. |
| 79 | + |
| 80 | +### Address or Segment Register or `AR` / `SR` |
| 81 | + |
| 82 | +The address or segment register is used to store the memory location of the instruction that |
| 83 | +is being executed. This is a group of 4 or 6 registers of two bytes named CS, DS, ES, and SS, FG, GS. |
| 84 | +These registers are used with either the IP register or 2 `index` registers DI and SI. |
| 85 | + |
| 86 | +### Memory Buffer Register or `MBR` |
| 87 | + |
| 88 | +This Register stores the contents of data or commands that are read from memory or written to it. |
| 89 | +In other words, the function of this register is to store data or instructions that are called |
| 90 | +from memory or loaded on it. The MBR register is similar to the MDR register, |
| 91 | +and they are no different at all. |
| 92 | + |
| 93 | +### Index Register or `BX` |
| 94 | + |
| 95 | +The purpose of this register is to store numbers or values in the processor that can be minus from |
| 96 | +or included as a part of the address of an instruction to transform it into an effective and |
| 97 | +efficient address. The Index Register is sometimes called the Base Register. |
| 98 | + |
| 99 | +Index Register is generally a registry within a computer processor which functions |
| 100 | +to change operand addresses during the execution of a program. |
| 101 | +In technical terms, Index Register is also called BX. |
| 102 | + |
| 103 | +### Program Counter or `PC` |
| 104 | + |
| 105 | +The Program Counter called PC for short is also known as the Instruction Pointer or IP. |
| 106 | +This register is often pronounced as the Instruction Address Register. |
| 107 | +This register stores the address memory path of the instruction which is going |
| 108 | +to be processed after the current instruction is finished successfully. |
| 109 | + |
| 110 | +In other words, the function of this Register is to contain the memory address of |
| 111 | +the next instruction until the current instruction processed successfully. |
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