Merge tag 'v1.4.18' into dev

Author: abejgonzalez

.gitignore

@@ -39,7 +39,7 @@ fio
 !SDAccel/aws_platform/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/sw/lib/x86_64/libxilinxopencl.so
 !SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/sw/lib/x86_64/libxilinxopencl.so
 !SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr-debug_4_0/sw/lib/x86_64/libxilinxopencl.so
-!SDAccel/aws_platform/xilinx_aws-vu9p-f1_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so 
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so
 !SDAccel/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so
 
 nohup.out
@@ -106,6 +106,13 @@ vivado*.log
 # Patches
 patches/*
 
+# Temporary files
+.batch
+.temp
+
+.python-version
+
+# FireSim specific
 awsver.txt
 
 sdk/linux_kernel_drivers/xdma/.libxdma.o.d

.gitmodules

@@ -1,12 +1,13 @@
-[submodule "SDAccel/examples/xilinx_2017.4"]
-	path = SDAccel/examples/xilinx_2017.4
+[submodule "SDAccel/examples/xilinx_2019.1"]
+	path = SDAccel/examples/xilinx_2019.1
 	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = aws_2017.4
-[submodule "SDAccel/examples/xilinx_2018.2"]
-	path = SDAccel/examples/xilinx_2018.2
-	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = 2018.2
-[submodule "SDAccel/examples/xilinx_2018.3"]
-	path = SDAccel/examples/xilinx_2018.3
-	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = master	
+[submodule "Vitis/examples/xilinx_2019.2"]
+	path = Vitis/examples/xilinx_2019.2
+	branch = master
+	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2020.1"]
+	path = Vitis/examples/xilinx_2020.1
+	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2020.2"]
+	path = Vitis/examples/xilinx_2020.2
+	url = https://github.com/Xilinx/Vitis_Accel_Examples

ERRATA.md

@@ -5,14 +5,35 @@
 [Shell\_04261818_Errata](./hdk/docs/AWS_Shell_ERRATA.md)
 
 ## HDK
-* Multiple SDE instances per CL is not supported in this release.  Support planned for future release.
+* Multiple SDE instances per CL is not supported in this release. Support is planned for a future release.
 * DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
-* Combinatorial loops in CL designs are not supported.
-* Shell Model (sh_bfm) provided with testbench for design simulations, continues to drive read data on PCIM AXI rdata channel even when rready is de-asserted. Will be fixed in future release.
+* Combinatorial loops in CL designs are not supported.  
+* Connecting one of the clocks provided from the shell (clk_main_a0, clk_extra_a1, etc...) directly to a BUFG in the CL is not supported by the Xilinx tools and may result in a non-functional clock. To workaround this limitation, it is recommended to use an MMCM to feed the BUFG (clk_from_shell -> MMCM -> BUFG). Please refer to [Xilinx AR# 73360](https://www.xilinx.com/support/answers/73360.html) for further details.
+
+### Xilinx Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions (AR# 73068)
+AWS EC2 F1 customers using the DDR4 IP in customer logic (HDK or SDAccel/Vitis designs) may be impacted by a recent design advisory from Xilinx.
+
+AWS customers may experience hardware failures including: post calibration data errors and DQS gate tracking issues. The error condition is build dependent and errors would need to be detected on the first write/read access after a successful calibration to prevent further data corruption.
+
+To detect if your build is impacted by this bug, AWS recommends all EC2 F1 customers utilizing the DDR4 IP in their designs should run a TCL script on the design checkpoint point (DCP) to check to determine if the design is susceptible to this issue. If the check passes, your design is safe to use as the hardware will function properly. 
+If the check fails, the design is susceptible to the issue and will need to be regenerated using the same tool version with the AR 73068 patch. 
+For designs under development, we recommend applying the patch to your on-premises tools or update to developer kit v1.4.15. 
+For additional details, please refer to the [Xilinx Answer Record #73068](https://www.xilinx.com/support/answers/73068.html)
+
+We recommend using [Developer Kit Release v1.4.15a](https://github.com/aws/aws-fpga/releases/tag/v1.4.15a) or newer to allow for patching and fixing the DDR4 IP timing exception by re-generating the IP.
+
+### 2019.1 
+* Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators.
+* Please refer to the Xilinx Answer record for details.
+
+| Library(verilog) | Simulator | Xilinx Answer Record | 
+|---|---|---|
+| `sync_ip` | Cadence IES | [AR72795](https://www.xilinx.com/support/answers/72795.html) |
+| `hdmi_gt_controller_v1_0_0` | Synopsys VCS | [AR72601](https://www.xilinx.com/support/answers/72601.html) |
 
 ## SDK
 
 ## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md))
 * Virtual Ethernet is not supported when using SDAccel
 * DRAM Data retention is not supported for kernels that provision less than 4 DDRs
-* Combinatorial loops in CL designs are not supported.
+* Combinatorial loops in CL designs are not supported.