Module 'myproject_fpext_32ns_64_4_no_dsp_1_ip' not found

[chiutamarcel]

I am trying to run the part6 tutorial for my zedboard, but after running

vitis_hls -f build_prj.tcl

in the project directory with the following options in build_prj.tcl:

array set opt {
    reset      0
    csim       0
    synth      1
    cosim      0
    validation 0
    export     1
    vsynth     1
    fifo_opt   1
}

I get:

synth_design failed
INFO: [Common 17-206] Exiting Vivado at Sun Mar 16 19:09:21 2025...
ERROR: [Synth 8-439] module 'myproject_fpext_32ns_64_4_no_dsp_1_ip' not found [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject_fpext_32ns_64_4_no_dsp_1.v:34]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_fpext_32ns_64_4_no_dsp_1' [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject_fpext_32ns_64_4_no_dsp_1.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_init_exp_table_ap_fixed_29_13_5_3_0_softmax_config25_s' [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject_init_exp_table_ap_fixed_29_13_5_3_0_softmax_config25_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_softmax_stable_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config25_s' [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject_softmax_stable_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config25_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_softmax_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config25_s' [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject_softmax_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config25_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject' [/home/mihai/Documents/Licenta/hls4ml-tutorial/quantized_pruned_cnn/myproject_prj/solution1/syn/verilog/myproject.v:9]
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
    while executing
"exec vivado -mode batch -source vivado_synth.tcl >@ stdout"
    invoked from within
"if {$opt(vsynth)} {
    puts "***** VIVADO SYNTHESIS *****"
    if {[file exist ${project_name}_prj/solution1/syn/verilog]} {
        set time_start [..."
    (file "build_prj.tcl" line 237)
    invoked from within
"source build_prj.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $tclfile] "

This is the fpga part: xc7z020clg484-1
I used the Vitis backend.

[jmitrevs]

What step is the failure in? If you just do csim only (i.e. all others 0) does it work? If that works, can you try synth only? Otherwise, I would suggest trying to go back to the python GUI and try going through all the steps from there.