Partial reconfiguration done on Image Processing was implemeted using the ZedBoard Zynq Evaluation and Development Kit FPGA board.
The board shown below is the ZedBoard Zynq Evaluation and Development Kit(xc7z020clg484-1).
The documentation on the same can be obtained using the link given:
https://digilent.com/reference/programmable-logic/zedboard/reference-manual?redirect=1
Here Dynamic Partial reconguration is done with different kinds of Image processing techniques made as different reconfigurable modules.
The image is loaded into the RTL as a .coe file via a Block memory.The RTL codes process the data from the COE file and processes the image as per our needs and displays the same on a monitior Through the VGA port on our board.
Below given is the post implementation schematic.It has been done of 3 Partial reconfigurations.
