Implemented beqimm and bneimm

Author: Pasquale Davide Schiavone

alu.sv

@@ -396,10 +396,6 @@ module riscv_alu
     endcase
   end
 
-  logic cmp_eqall;
-
-  assign cmp_eqall = (operand_a_i == 32'hFFFF_FFFF);
-
   // generate comparison result
   logic [3:0] cmp_result;
 
@@ -417,7 +413,6 @@ module riscv_alu
       ALU_SLETS,
       ALU_SLETU,
       ALU_LES, ALU_LEU:  cmp_result = ~is_greater;
-      ALU_EQALL:         cmp_result = {4{cmp_eqall}};
 
       default: ;
     endcase

decoder.sv

@@ -239,8 +239,18 @@ module riscv_decoder
           3'b101: alu_operator_o = ALU_GES;
           3'b110: alu_operator_o = ALU_LTU;
           3'b111: alu_operator_o = ALU_GEU;
-          3'b010: alu_operator_o = ALU_EQALL;
-
+          3'b010: begin
+            alu_operator_o      = ALU_EQ;
+            regb_used_o         = 1'b0;
+            alu_op_b_mux_sel_o  = OP_B_IMM;
+            imm_b_mux_sel_o     = IMMB_BI;
+          end
+          3'b011: begin
+            alu_operator_o      = ALU_NE;
+            regb_used_o         = 1'b0;
+            alu_op_b_mux_sel_o  = OP_B_IMM;
+            imm_b_mux_sel_o     = IMMB_BI;
+          end
           default: begin
             illegal_insn_o = 1'b1;
           end

id_stage.sv

@@ -235,6 +235,7 @@ module riscv_id_stage
   logic [31:0] imm_uj_type;
   logic [31:0] imm_z_type;
   logic [31:0] imm_s2_type;
+  logic [31:0] imm_bi_type;
   logic [31:0] imm_s3_type;
   logic [31:0] imm_vs_type;
   logic [31:0] imm_vu_type;
@@ -371,6 +372,7 @@ module riscv_id_stage
   assign imm_z_type  = { 27'b0, instr[`REG_S1] };
 
   assign imm_s2_type = { 27'b0, instr[24:20] };
+  assign imm_bi_type = { {27{instr[24]}}, instr[24:20] };
   assign imm_s3_type = { 27'b0, instr[29:25] };
   assign imm_vs_type = { {26 {instr[24]}}, instr[24:20], instr[25] };
   assign imm_vu_type = { 26'b0, instr[24:20], instr[25] };
@@ -567,6 +569,7 @@ module riscv_id_stage
       IMMB_U:      imm_b = imm_u_type;
       IMMB_PCINCR: imm_b = (is_compressed_i && (~data_misaligned_i)) ? 32'h2 : 32'h4;
       IMMB_S2:     imm_b = imm_s2_type;
+      IMMB_BI:     imm_b = imm_bi_type;
       IMMB_S3:     imm_b = imm_s3_type;
       IMMB_VS:     imm_b = imm_vs_type;
       IMMB_VU:     imm_b = imm_vu_type;

include/riscv_defines.sv

@@ -120,7 +120,6 @@ parameter ALU_GES   = 6'b001010;
 parameter ALU_GEU   = 6'b001011;
 parameter ALU_EQ    = 6'b001100;
 parameter ALU_NE    = 6'b001101;
-parameter ALU_EQALL = 6'b001110;
 
 // Set Lower Than operations
 parameter ALU_SLTS  = 6'b000010;
@@ -236,6 +235,7 @@ parameter IMMB_VS     = 4'b0110;
 parameter IMMB_VU     = 4'b0111;
 parameter IMMB_SHUF   = 4'b1000;
 parameter IMMB_CLIP   = 4'b1001;
+parameter IMMB_BI     = 4'b1011;
 
 // bit mask selection
 parameter BMASK_A_ZERO = 1'b0;