From 6b2c7282d682f0edc6b31f589bbf55a003f1bf34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kevin=20L=C3=A4ufer?= <laeufer@cs.berkeley.edu>
Date: Thu, 9 Nov 2023 20:46:42 -0500
Subject: [PATCH] more tests

---
 tests/diff_tests.rs | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/tests/diff_tests.rs b/tests/diff_tests.rs
index 343a7af..ffc3bbe 100644
--- a/tests/diff_tests.rs
+++ b/tests/diff_tests.rs
@@ -7,7 +7,7 @@ use waveform::{Hierarchy, HierarchyItem, ScopeType, SignalRef, TimescaleUnit, Va
 
 fn run_diff_test(vcd_filename: &str, fst_filename: &str) {
     {
-        let wave = waveform::vcd::read(vcd_filename).expect("Failed to load VCD");
+        let wave = waveform::vcd::read_single_thread(vcd_filename).expect("Failed to load VCD");
         diff_test_one(vcd_filename, wave);
     }
     {
@@ -362,6 +362,29 @@ fn diff_my_hdl_sigmoid_tb() {
     );
 }
 
+#[test]
+fn diff_my_hdl_simple_memory() {
+    run_diff_test(
+        "inputs/my-hdl/Simple_Memory.vcd",
+        "inputs/my-hdl/Simple_Memory.vcd.fst",
+    );
+}
+
+#[test]
+#[ignore] // TODO: this file has a delta cycle, i.e. the same signal (`@`) changes several times in the same cycle (20)
+fn diff_my_hdl_top() {
+    run_diff_test("inputs/my-hdl/top.vcd", "inputs/my-hdl/top.vcd.fst");
+}
+
+#[test]
+#[ignore] // TODO: add full real support
+fn diff_ncsim_ffdiv_32bit_tb() {
+    run_diff_test(
+        "inputs/ncsim/ffdiv_32bit_tb.vcd",
+        "inputs/ncsim/ffdiv_32bit_tb.vcd.fst",
+    );
+}
+
 #[test]
 fn diff_treadle_gcd() {
     run_diff_test("inputs/treadle/GCD.vcd", "inputs/treadle/GCD.vcd.fst");