From 5055bc975ae4e7ee3a2f528c1830ca1259b1a5b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kevin=20L=C3=A4ufer?= <laeufer@cs.berkeley.edu>
Date: Thu, 9 Nov 2023 19:57:21 -0500
Subject: [PATCH] add more variable types and better error messages for diff
 test

---
 src/hierarchy.rs    | 19 ++++++++++++++---
 src/vcd.rs          | 13 ++++++++++++
 tests/diff_tests.rs | 52 +++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 79 insertions(+), 5 deletions(-)

diff --git a/src/hierarchy.rs b/src/hierarchy.rs
index 49d3a25..2627f0e 100644
--- a/src/hierarchy.rs
+++ b/src/hierarchy.rs
@@ -124,10 +124,23 @@ pub enum ScopeType {
 
 #[derive(Debug, Clone, Copy)]
 pub enum VarType {
-    Wire,
-    Reg,
-    Parameter,
+    Event,
     Integer,
+    Parameter,
+    Real,
+    Reg,
+    Supply0,
+    Supply1,
+    Time,
+    Tri,
+    TriAnd,
+    TriOr,
+    TriReg,
+    Tri0,
+    Tri1,
+    WAnd,
+    Wire,
+    WOr,
     String,
 }
 
diff --git a/src/vcd.rs b/src/vcd.rs
index 27ecfc7..c22cf02 100644
--- a/src/vcd.rs
+++ b/src/vcd.rs
@@ -173,6 +173,19 @@ fn convert_var_tpe(tpe: &[u8]) -> VarType {
         b"parameter" => VarType::Parameter,
         b"integer" => VarType::Integer,
         b"string" => VarType::String,
+        b"event" => VarType::Event,
+        b"real" => VarType::Real,
+        b"supply0" => VarType::Supply0,
+        b"supply1" => VarType::Supply1,
+        b"time" => VarType::Time,
+        b"tri" => VarType::Tri,
+        b"triand" => VarType::TriAnd,
+        b"trior" => VarType::TriOr,
+        b"trireg" => VarType::TriReg,
+        b"tri0" => VarType::Tri0,
+        b"tri1" => VarType::Tri1,
+        b"wand" => VarType::WAnd,
+        b"wor" => VarType::WOr,
         _ => panic!("TODO: convert {}", String::from_utf8_lossy(tpe)),
     }
 }
diff --git a/tests/diff_tests.rs b/tests/diff_tests.rs
index 5561754..fe341e0 100644
--- a/tests/diff_tests.rs
+++ b/tests/diff_tests.rs
@@ -86,6 +86,19 @@ fn waveform_var_type_to_string(tpe: VarType) -> &'static str {
         VarType::Parameter => "parameter",
         VarType::Integer => "integer",
         VarType::String => "string",
+        VarType::Event => "event",
+        VarType::Real => "real",
+        VarType::Supply0 => "supply0",
+        VarType::Supply1 => "supply1",
+        VarType::Time => "time",
+        VarType::Tri => "tri",
+        VarType::TriAnd => "triand",
+        VarType::TriOr => "trior",
+        VarType::TriReg => "trireg",
+        VarType::Tri0 => "tri0",
+        VarType::Tri1 => "tri1",
+        VarType::WAnd => "wand",
+        VarType::WOr => "wor",
     }
 }
 
@@ -165,7 +178,16 @@ fn diff_signals<R: BufRead>(ref_reader: &mut vcd::Parser<R>, our: &mut Waveform)
                 let signal_ref = vcd_lib_id_to_signal_ref(id);
                 let our_value = our.get_signal_value_at(signal_ref, time_table_idx as u32);
                 let our_value_str = our_value.to_bit_string().unwrap();
-                assert_eq!(our_value_str, value.to_string());
+                assert_eq!(
+                    our_value_str,
+                    value.to_string(),
+                    "{} ({:?}) = {} @ {} ({})",
+                    id,
+                    signal_ref,
+                    value,
+                    current_time,
+                    our_value_str
+                );
             }
             vcd::Command::ChangeVector(id, value) => {
                 let signal_ref = vcd_lib_id_to_signal_ref(id);
@@ -197,7 +219,16 @@ fn diff_signals<R: BufRead>(ref_reader: &mut vcd::Parser<R>, our: &mut Waveform)
                         }
                     }
                 } else {
-                    assert_eq!(our_value_str, value.to_string());
+                    assert_eq!(
+                        our_value_str,
+                        value.to_string(),
+                        "{} ({:?}) = {} @ {} ({})",
+                        id,
+                        signal_ref,
+                        value,
+                        current_time,
+                        our_value_str
+                    );
                 }
             }
             vcd::Command::ChangeReal(_, _) => {
@@ -307,6 +338,23 @@ fn diff_icarus_test1() {
     run_diff_test("inputs/icarus/test1.vcd", "inputs/icarus/test1.vcd.fst");
 }
 
+#[test]
+fn diff_model_sim_clkdiv2n_tb() {
+    run_diff_test(
+        "inputs/model-sim/clkdiv2n_tb.vcd",
+        "inputs/model-sim/clkdiv2n_tb.vcd.fst",
+    );
+}
+
+#[test]
+#[ignore] // TODO: this file has a delta cycle, i.e. the same signal (`p`) changes twice in the same cycle (20000)
+fn diff_model_sim_cpu_design() {
+    run_diff_test(
+        "inputs/model-sim/CPU_Design.msim.vcd",
+        "inputs/model-sim/CPU_Design.msim.vcd.fst",
+    );
+}
+
 #[test]
 fn diff_treadle_gcd() {
     run_diff_test("inputs/treadle/GCD.vcd", "inputs/treadle/GCD.vcd.fst");