From 1336eebbce8800b84fb71cf7da4ef739b69be855 Mon Sep 17 00:00:00 2001
From: Kareem Farid <kareefardi@users.noreply.github.com>
Date: Wed, 26 Jun 2024 11:24:19 +0300
Subject: [PATCH] Remove default_nettype statements at the end of the RTL

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
---
 verilog/rtl/user_proj_example.v    | 1 -
 verilog/rtl/user_project_wrapper.v | 2 --
 2 files changed, 3 deletions(-)

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 7704be8d5..3657d7a6a 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -153,4 +153,3 @@ module counter #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 14e4dee2a..383dfe358 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -119,5 +119,3 @@ user_proj_example mprj (
 );
 
 endmodule	// user_project_wrapper
-
-`default_nettype wire