add pass-thru signals

jeffdi · jeffdi · commit 1321c51aeedc · 2022-10-14T13:02:19.000-07:00
diff --git a/litex/caravel.py b/litex/caravel.py
@@ -286,6 +286,34 @@ def __init__(self, sys_clk_freq=int(10e6), **kwargs ):
         self.comb += clk_out.eq(clk_in)
         self.comb += resetn_out.eq(resetn_in)
 
+        serial_load_in = platform.request("serial_load_in")
+        serial_load_out = platform.request("serial_load_out")
+        self.comb += serial_load_out.eq(serial_load_in)
+
+        serial_data_2_in = platform.request("serial_data_2_in")
+        serial_data_2_out = platform.request("serial_data_2_out")
+        self.comb += serial_data_2_out.eq(serial_data_2_in)
+
+        serial_resetn_in = platform.request("serial_resetn_in")
+        serial_resetn_out = platform.request("serial_resetn_out")
+        self.comb += serial_resetn_out.eq(serial_resetn_in)
+
+        serial_clock_in = platform.request("serial_clock_in")
+        serial_clock_out = platform.request("serial_clock_out")
+        self.comb += serial_clock_out.eq(serial_clock_in)
+
+        rstb_l_in = platform.request("rstb_l_in")
+        rstb_l_out = platform.request("rstb_l_out")
+        self.comb += rstb_l_out.eq(rstb_l_in)
+
+        por_l_in = platform.request("por_l_in")
+        por_l_out = platform.request("por_l_out")
+        self.comb += por_l_out.eq(por_l_in)
+
+        porb_h_in = platform.request("porb_h_in")
+        porb_h_out = platform.request("porb_h_out")
+        self.comb += porb_h_out.eq(porb_h_in)
+
     #####################
 
     def new_add_spi_flash(self, name="flash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):
diff --git a/litex/caravel_platform.py b/litex/caravel_platform.py
@@ -20,6 +20,21 @@
     ("resetn_in", 0, Pins(1)),
     ("resetn_out", 0, Pins(1)),
 
+    ("serial_load_in", 0, Pins(1)),
+    ("serial_load_out", 0, Pins(1)),
+    ("serial_data_2_in", 0, Pins(1)),
+    ("serial_data_2_out", 0, Pins(1)),
+    ("serial_resetn_in", 0, Pins(1)),
+    ("serial_resetn_out", 0, Pins(1)),
+    ("serial_clock_in", 0, Pins(1)),
+    ("serial_clock_out", 0, Pins(1)),
+    ("rstb_l_in", 0, Pins(1)),
+    ("rstb_l_out", 0, Pins(1)),
+    ("por_l_in", 0, Pins(1)),
+    ("por_l_out", 0, Pins(1)),
+    ("porb_h_in", 0, Pins(1)),
+    ("porb_h_out", 0, Pins(1)),
+
     # GPIO mgmt
     ("gpio", 0,
      Subsignal("out_pad", Pins(1)),
diff --git a/verilog/dv/generated/csr.h b/verilog/dv/generated/csr.h
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (9a0be7a) & LiteX (c17d028) on 2022-10-11 07:59:57
+// Auto-generated by Migen (9a0be7a) & LiteX (470fc6f) on 2022-10-14 12:53:54
 //--------------------------------------------------------------------------------
 #include <generated/soc.h>
 #ifndef __GENERATED_CSR_H
diff --git a/verilog/dv/generated/git.h b/verilog/dv/generated/git.h
@@ -1,9 +1,9 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (9a0be7a) & LiteX (c17d028) on 2022-10-11 07:59:57
+// Auto-generated by Migen (9a0be7a) & LiteX (470fc6f) on 2022-10-14 12:53:55
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_GIT_H
 #define __GENERATED_GIT_H
 
 #define MIGEN_GIT_SHA1 "9a0be7a"
-#define LITEX_GIT_SHA1 "c17d028"
+#define LITEX_GIT_SHA1 "470fc6f"
 #endif
diff --git a/verilog/dv/generated/mem.h b/verilog/dv/generated/mem.h
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (9a0be7a) & LiteX (c17d028) on 2022-10-11 07:59:57
+// Auto-generated by Migen (9a0be7a) & LiteX (470fc6f) on 2022-10-14 12:53:54
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_MEM_H
 #define __GENERATED_MEM_H
diff --git a/verilog/dv/generated/soc.h b/verilog/dv/generated/soc.h
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (9a0be7a) & LiteX (c17d028) on 2022-10-11 07:59:57
+// Auto-generated by Migen (9a0be7a) & LiteX (470fc6f) on 2022-10-14 12:53:54
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_SOC_H
 #define __GENERATED_SOC_H
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
