microcode.txt

Storage

Name     Index    Size    Purpose
---------------------------------------------------------------------------
r0-r31 | [0:31] | 32bit | CPU registers
c0-c31 |[32:63] | 32bit | CSR registers
PC     |   [64] | 32bit | Current program counter
immd   |   [65] | 32bit | Immediate value calculated from instruction encoding
offt   |   [66] | 32bit | Address offset register
stat   |   [67] | 32bit | Status register, [0]branchready, [1]compare true, [31:2]unused
cval   |   [68] | 32bit | Current register value loaded
lval   |   [69] | 32bit | Result of the load operation
sval   |   [70] | 32bit | Value for the pending store operation
lflg   |   [71] | 32bit | Flags for each register to mark 'busy for load'
sflg   |   [72] | 32bit | Flags for each register to mark 'busy for store'
dadr   |   [73] | 32bit | Address register for load/store
badr   |   [74] | 32bit | Calculated branch address
---------------------------------------------------------------------------

Opcodes

cmp[.op] target, [source]: Compare source to target and set 
csel regA, regB: Depending on the result of previous compare, either keep regA's contents (true) or replace them with regB's contents (false)
move[.op] target, source: Copy target register to source register, and run ALU op on result (branch writes to PC with op equal to nothing or a compare)
  ops: adi(transient add immediate to source), ado(transient add offset to source), if(conditional move depending on last compare result)
load target [daddr]: Start a load request from implied daddr register into target register, set corresponding lflg bit to one
lwait target: Wait for target register's lflg bit to become zero (only inserted if a lflg register is being read)
unblock.unit: Execute unit will unblock the given unit
  unit: 0(fetchunit) others(none)
waitfor.unit: Execute unit will wait for the given unit to unblock it
  unit: 0(fetchunit) others(none)

Example

00000000 <_start>:
   0:	0000b197          	auipc	gp,0xb
                        move.imm immd, 0xb
                        move.adi gp, PC
   4:	03c1a183          	lw	gp,60(gp) # b03c <_GLOBAL_OFFSET_TABLE_+0x4>
                        move.imm offt, 60
                        move.ado daddr, gp // daddr = gp+60
                        load gp // lflg[gp]=1
   8:	f14024f3          	csrr	s1,mhartid
                        move s1, csr_mhartid
   c:	00849493          	slli	s1,s1,0x8
                        move.imm immd, 0x8
                        move.sll s1, immd
  10:	00020937          	lui	s2,0x20
                        move.imm s2, 0x20
  14:	f0090913          	addi	s2,s2,-256 # 1ff00 <__global_pointer$+0x14680>
                        move.imm immd, -256
                        move s2, immd
  18:	40990933          	sub	s2,s2,s1
                        move.sub s2, s1
  1c:	00090113          	mv	sp,s2
                        move sp, s2
  20:	00010413          	mv	s0,sp
                        move s0, sp
  24:	04049a63          	bnez	s1,78 <workerhartstart>
                        move.imm badr, 78
                        move.imm offt, 4
                        move.ado cval, PC // cval = PC+4
                        cmp.ne s1, r0     // !=0?, exec unit will always do the compare and signal Fetch with the result bit + resume strobe
                        csel badr, cval   // Either keep badr (true) or replace with cval (PC+4, false)
                        unblock.fetchunit // Branch address is already output, just unblock fetch unit which sets PC to either bradr(true) or PC+4(false)
  28:	0000b517          	auipc	a0,0xb
  
  2c:	02c52503          	lw	a0,44(a0) # b054 <_GLOBAL_OFFSET_TABLE_+0x1c>
                        move.imm offt, 44
                        move.ado daddr, a0 // daddr = a0+44
                        load a0, 0 // lflg[a0]=1, load into lval[0]
  30:	0000b617          	auipc	a2,0xb
                        // Other operations here
  34:	03862603          	lw	a2,56(a2) # b068 <_GLOBAL_OFFSET_TABLE_+0x30>
                        move.imm offt, 56
                        move.ado daddr, a2
                        load a2, 1 // lflg[a2]=1, load into lval[1]
  38:	40a60633          	sub	a2,a2,a0
                        // lflg[a0]==1 and lflg[a2]==1, and we read both, therefore insert lwait here
                        lwait a0 // wait for lflg[a0]==0
                        move a0, lval[0]
                        lwait a2 // wait for lflg[a2]==0
                        move a2, lval[1]
                        move.sub a2, a0

  3c:	00000593          	li	a1,0
  40:	050000ef          	jal	ra,90 <memset>
                        move.imm badr, 90
                        move ra, PC
                        // Fetch changes PC to badr here
  44:	0000b517          	auipc	a0,0xb
  48:	01852503          	lw	a0,24(a0) # b05c <_GLOBAL_OFFSET_TABLE_+0x24>
  4c:	00050a63          	beqz	a0,60 <noatexitfound>
  50:	00001517          	auipc	a0,0x1
  54:	0000b517          	auipc	a0,0xb
  58:	ff452503          	lw	a0,-12(a0) # b048 <_GLOBAL_OFFSET_TABLE_+0x10>
  5c:	4e5060ef          	jal	ra,6d40 <atexit>

00000060 <noatexitfound>:
  60:	55d060ef          	jal	ra,6dbc <__libc_init_array>
  64:	00012503          	lw	a0,0(sp)
  68:	00410593          	addi	a1,sp,4
  6c:	00000613          	li	a2,0
  70:	14d0606f          	j	69bc <main>
  74:	00100073          	ebreak

00000078 <workerhartstart>:
  78:	00012503          	lw	a0,0(sp)
  7c:	00410593          	addi	a1,sp,4
  80:	00000613          	li	a2,0
  84:	1310606f          	j	69b4 <_Z10workermainv>
  88:	00100073          	ebreak