From 19467dccf4e6786296eecd8007f90e6dafe01818 Mon Sep 17 00:00:00 2001 From: Xu Liangyu Date: Wed, 15 May 2024 23:50:52 +0800 Subject: [PATCH] [LoongArch64] Fix the register conflict of the `REG_GSCOOKIE_TMP` and the `FastTailCall target register`. (#102192) --- src/coreclr/jit/lsraloongarch64.cpp | 4 ++-- src/coreclr/jit/targetloongarch64.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/lsraloongarch64.cpp b/src/coreclr/jit/lsraloongarch64.cpp index 1ceb61e536255d..5fda31befc69fa 100644 --- a/src/coreclr/jit/lsraloongarch64.cpp +++ b/src/coreclr/jit/lsraloongarch64.cpp @@ -723,7 +723,7 @@ int LinearScan::BuildCall(GenTreeCall* call) { // Fast tail call - make sure that call target is always computed in volatile registers // that will not be overridden by epilog sequence. - ctrlExprCandidates = allRegs(TYP_INT) & RBM_INT_CALLEE_TRASH; + ctrlExprCandidates = (allRegs(TYP_INT) & (RBM_INT_CALLEE_TRASH & ~RBM_GSCOOKIE_TMP)); assert(ctrlExprCandidates != RBM_NONE); } } @@ -734,7 +734,7 @@ int LinearScan::BuildCall(GenTreeCall* call) regMaskTP candidates = RBM_NONE; if (call->IsFastTailCall()) { - candidates = allRegs(TYP_INT) & RBM_INT_CALLEE_TRASH; + candidates = (allRegs(TYP_INT) & (RBM_INT_CALLEE_TRASH & ~RBM_GSCOOKIE_TMP)); assert(candidates != RBM_NONE); } diff --git a/src/coreclr/jit/targetloongarch64.h b/src/coreclr/jit/targetloongarch64.h index dcc87944beb163..2382eaa767cc5c 100644 --- a/src/coreclr/jit/targetloongarch64.h +++ b/src/coreclr/jit/targetloongarch64.h @@ -110,6 +110,7 @@ // Temporary registers used for the GS cookie check. #define REG_GSCOOKIE_TMP_0 REG_T0 #define REG_GSCOOKIE_TMP_1 REG_T1 + #define RBM_GSCOOKIE_TMP (RBM_T0|RBM_T1) // register to hold shift amount; no special register is required on LOONGARCH64. #define REG_SHIFT REG_NA