From e13ef2f584d94c05975f968a5e1cf4bdff43fc55 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Thu, 21 Mar 2024 15:34:08 -0700 Subject: [PATCH] Verilog: fix for indexed part select --- src/verilog/verilog_typecheck_expr.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp index 325c62206..271e95cfd 100644 --- a/src/verilog/verilog_typecheck_expr.cpp +++ b/src/verilog/verilog_typecheck_expr.cpp @@ -2411,7 +2411,6 @@ exprt verilog_typecheck_exprt::convert_trinary_expr(ternary_exprt expr) // The index need not be a constant. exprt &op1 = expr.op1(); - convert_expr(op1); // The width of the indexed part select must be an // elaboration-time constant. @@ -2455,6 +2454,8 @@ exprt verilog_typecheck_exprt::convert_trinary_expr(ternary_exprt expr) else { // Index not constant. + convert_expr(op1); + // Use logical right-shift followed by (constant) extractbits. auto op1_adjusted = minus_exprt{op1, from_integer(op0_offset, op1.type())};