Skip to content

Commit f687a26

Browse files
committed
docs/news: add fragments for VUnit#559, VUnit#764 and VUnit#777
1 parent 6698e01 commit f687a26

File tree

4 files changed

+13
-0
lines changed

4 files changed

+13
-0
lines changed

docs/news.d/559.breaking.rst

+4
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
HDL builtins are not compiled by default.
2+
To preserve the functionality, the run script is now required to explicitly use methods
3+
:meth:`add_vhdl_builtins() <vunit.ui.VUnit.add_vhdl_builtins>` or
4+
:meth:`add_verilog_builtins() <vunit.ui.VUnit.add_verilog_builtins>`.

docs/news.d/764.breaking.rst

+4
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
HDL builtins are not compiled by default.
2+
To preserve the functionality, the run script is now required to explicitly use methods
3+
:meth:`add_vhdl_builtins() <vunit.ui.VUnit.add_vhdl_builtins>` or
4+
:meth:`add_verilog_builtins() <vunit.ui.VUnit.add_verilog_builtins>`.

docs/news.d/764.doc.rst

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Rename 'VHDL Libraries' to :ref:`hdl_libraries`. Add section :ref:`Guides <user_guide>`.

docs/news.d/777.breaking.rst

+4
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
HDL builtins are not compiled by default.
2+
To preserve the functionality, the run script is now required to explicitly use methods
3+
:meth:`add_vhdl_builtins() <vunit.ui.VUnit.add_vhdl_builtins>` or
4+
:meth:`add_verilog_builtins() <vunit.ui.VUnit.add_verilog_builtins>`.

0 commit comments

Comments
 (0)