diff --git a/.clang-format b/.clang-format index 940f22994b8f..11054457bc36 100644 --- a/.clang-format +++ b/.clang-format @@ -99,6 +99,7 @@ IndentCaseLabels: false IndentGotoLabels: false IndentWidth: 8 InsertBraces: true +InsertNewlineAtEOF: true SpaceBeforeInheritanceColon: False SpaceBeforeParens: ControlStatementsExceptControlMacros SortIncludes: Never diff --git a/.github/ISSUE_TEMPLATE/001_bug_report.md b/.github/ISSUE_TEMPLATE/001_bug_report.md deleted file mode 100644 index a3d0677184b3..000000000000 --- a/.github/ISSUE_TEMPLATE/001_bug_report.md +++ /dev/null @@ -1,71 +0,0 @@ ---- -name: Bug report -about: Create a report to help us improve Zephyr -title: '' -labels: bug -assignees: '' - ---- - - -**Describe the bug** - - -**To Reproduce** - - -**Expected behavior** - - -**Impact** - - -**Logs and console output** - - -**Environment (please complete the following information):** - - - OS: (e.g. Linux, MacOS, Windows) - - Toolchain (e.g Zephyr SDK, ...) - - Commit SHA or Version used - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/001_bug_report.yml b/.github/ISSUE_TEMPLATE/001_bug_report.yml new file mode 100644 index 000000000000..38e7107524c7 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/001_bug_report.yml @@ -0,0 +1,85 @@ +name: Bug Report +description: File a bug report. +labels: ["bug"] +type: "Bug" +assignees: [] +body: + - type: markdown + attributes: + value: | + Thanks for taking the time to fill out this bug report! + - type: textarea + id: what-happened + attributes: + label: Describe the bug + description: | + A clear and concise description of what the bug is. + + placeholder: | + Please also mention any information which could help others to understand + the problem you're facing: + - What target platform are you using? + - What have you tried to diagnose or workaround this issue? + - Is this a regression? If yes, have you been able to "git bisect" it to a + specific commit? + validations: + required: true + - type: checkboxes + id: regression + attributes: + label: Regression + description: | + Check this box if this is a regression and provide a SHA if you were able to "git bisect" to a specific commit. + options: + - label: This is a regression. + required: false + - type: textarea + id: reproduce + attributes: + label: Steps to reproduce + description: | + Steps to reproduce the behavior. + + placeholder: | + Steps to reproduce the behavior: + 1. mkdir build; cd build + 2. cmake -DBOARD=board\_xyz + 3. make + 4. See error + validations: + required: false + - type: textarea + id: logs + attributes: + label: Relevant log output + description: Please copy and paste any relevant log output. This will be automatically formatted into code, so no need for backticks. + render: shell + - type: dropdown + attributes: + label: Impact + description: Impact of this bug + multiple: false + options: + - Showstopper – Prevents release or major functionality; system unusable. + - Major – Severely degrades functionality; workaround is difficult or unavailable. + - Functional Limitation – Some features not working as expected, but system usable. + - Annoyance – Minor irritation; no significant impact on usability or functionality. + - Intermittent – Occurs occasionally; hard to reproduce. + - Not sure + default: 3 + validations: + required: true + - type: textarea + id: env + attributes: + label: Environment + description: please complete the following information + placeholder: | + - OS: (e.g. Linux, MacOS, Windows) + - Toolchain (e.g Zephyr SDK, ...) + - Commit SHA or Version used + - type: textarea + id: context + attributes: + label: Additional Context + description: Provide other context that could be relevant to the bug, such as pin setting, target configuration,etc. diff --git a/.github/ISSUE_TEMPLATE/002_enhancement.md b/.github/ISSUE_TEMPLATE/002_enhancement.md deleted file mode 100644 index 36dd018047d1..000000000000 --- a/.github/ISSUE_TEMPLATE/002_enhancement.md +++ /dev/null @@ -1,28 +0,0 @@ ---- -name: Enhancement -about: Suggest enhancements to existing features -title: '' -labels: Enhancement -assignees: '' - ---- - -**Is your enhancement proposal related to a problem? Please describe.** - - -**Describe the solution you'd like** - - -**Describe alternatives you've considered** - - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/002_enhancement.yml b/.github/ISSUE_TEMPLATE/002_enhancement.yml new file mode 100644 index 000000000000..3c2c12b8dce4 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/002_enhancement.yml @@ -0,0 +1,42 @@ +name: Enhancement +description: Submit an Enhancement +labels: ["Enhancement"] +type: "Enhancement" +assignees: [] +body: + - type: markdown + attributes: + value: | + Thanks for taking the time to fill out this enhancement proposal. + - type: textarea + id: description + attributes: + label: Summary + description: | + Is your enhancement proposal related to a problem? Please describe. + placeholder: | + A clear and concise description of what the problem is. + validations: + required: true + - type: textarea + id: solution + attributes: + label: Describe the solution you'd like + description: | + Describe the solution you'd like + placeholder: | + A clear and concise description of what you want to happen. + validations: + required: true + - type: textarea + id: alternatives + attributes: + label: Alternatives + description: Describe alternatives you've considered + placeholder: | + A clear and concise description of any alternative solutions or features you've considered. + - type: textarea + id: context + attributes: + label: Additional Context + description: Add any other context or graphics (drag-and-drop an image) about the enhancement here. diff --git a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md b/.github/ISSUE_TEMPLATE/003_rfc-proposal.md deleted file mode 100644 index 9cea2d2dac21..000000000000 --- a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md +++ /dev/null @@ -1,60 +0,0 @@ ---- -name: RFC / Proposal -about: Submit an RFC / Proposal -title: '' -labels: RFC -assignees: '' - ---- - -## Introduction - - - -### Problem description - - -### Proposed change - - -## Detailed RFC - - -### Proposed change (Detailed) - - -### Dependencies - - -### Concerns and Unresolved Questions - - -## Alternatives - diff --git a/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml b/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml new file mode 100644 index 000000000000..7ef0ca16e14a --- /dev/null +++ b/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml @@ -0,0 +1,75 @@ +name: RFC / Proposal +description: Submit a Proposal (RFC) +labels: ["RFC"] +type: RFC +assignees: [] +body: + - type: markdown + attributes: + value: | + ## Introduction + + This section targets end users, TSC members, maintainers and anyone else + that might need a quick explanation of your proposed change. + + - type: textarea + id: problem-description + attributes: + label: Problem Description + description: Why do we want this change and what problem are we trying to address? + placeholder: Explain the problem or limitation this RFC is meant to resolve. + validations: + required: true + + - type: textarea + id: proposed-change-summary + attributes: + label: Proposed Change (Summary) + description: A high-level summary of the proposed change. + placeholder: Brief summary of what will change if this RFC is implemented. + validations: + required: true + + - type: markdown + attributes: + value: | + ## Detailed RFC + + This section targets the development team. Upon reading it, each engineer + should understand what must be done to implement the proposed feature. + + - type: textarea + id: detailed-change + attributes: + label: Proposed Change (Detailed) + description: Describe the change in as much detail as possible. Include context or background info, and reuse of existing components if applicable. + placeholder: Explain exactly what you’re planning to change and how. + validations: + required: true + + - type: textarea + id: dependencies + attributes: + label: Dependencies + description: Highlight how this change may affect the rest of the project or other teams/components. + placeholder: List components, modules, or teams affected. + validations: + required: false + + - type: textarea + id: concerns + attributes: + label: Concerns and Unresolved Questions + description: List any concerns, unknowns, or unresolved questions related to this proposal. + placeholder: Any areas of uncertainty? + validations: + required: false + + - type: textarea + id: alternatives + attributes: + label: Alternatives Considered + description: What alternative solutions were considered? Why was this proposal chosen? + placeholder: List alternatives and explain the rationale behind your choice. + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/004_feature_request.md b/.github/ISSUE_TEMPLATE/004_feature_request.md deleted file mode 100644 index 63aa536c8f5d..000000000000 --- a/.github/ISSUE_TEMPLATE/004_feature_request.md +++ /dev/null @@ -1,28 +0,0 @@ ---- -name: Feature request -about: Suggest an idea for this project -title: '' -labels: Feature Request -assignees: '' - ---- - -**Is your feature request related to a problem? Please describe.** - - -**Describe the solution you'd like** - - -**Describe alternatives you've considered** - - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/004_feature_request.yml b/.github/ISSUE_TEMPLATE/004_feature_request.yml new file mode 100644 index 000000000000..e085f08ed775 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/004_feature_request.yml @@ -0,0 +1,29 @@ +name: Feature Request +description: Suggest a new feature or enhancement +labels: ["Feature Request"] +type: Feature +assignees: [] +body: + - type: textarea + id: problem + attributes: + label: Is your feature request related to a problem? Please describe. + description: A clear and concise description of what the problem is. + placeholder: e.g., I'm frustrated when I need to do X manually because Y is missing. + validations: + required: true + + - type: textarea + id: solution + attributes: + label: Describe the solution you'd like + description: A clear and concise description of what you want to happen. + placeholder: e.g., It would be great if the system could automatically handle X by doing Y. + validations: + required: true + + - type: textarea + id: alternatives + attributes: + label: Describe alternatives you've considered + description: Include any alternative solutions or features diff --git a/.github/ISSUE_TEMPLATE/006_nomination.md b/.github/ISSUE_TEMPLATE/006_nomination.md deleted file mode 100644 index 832fb7b82962..000000000000 --- a/.github/ISSUE_TEMPLATE/006_nomination.md +++ /dev/null @@ -1,42 +0,0 @@ ---- -name: Contributor Nomination -about: Nominate a GitHub user for additional rights on the Zephyr Project -title: '' -labels: Role Nomination -assignees: '' - ---- - -# Background - -The [TSC Project Roles] defines the main roles for the Zephyr Project, including -Maintainer, Collaborator, and Contributor. - -By default anyone that contributes code or documentation is a Contributor, but -with the lowest [GitHub Permission Level] of Read. For example, Contributors -with Read permission do not have the permission to add reviewers to a pull -request. - -Use this template to nominate a GitHub user for the Contributor role with -Triage permission level, which allows the user to add reviewers to a pull -request and be added as a reviewer by other users. - -# Nomination - -## GitHub User - -Provide the following information about the GitHub user: - -1. Full Name -1. GitHub username -1. Organization (optional) - -## Supporting Documents - -Add links to 3-5 GitHub pull requests, in the Zephyr project, authored or -reviewed by the GitHub user that demonstrate the user's dedication to the -Zephyr project. - - -[TSC Project Roles]: -[GitHub Permission Level]: diff --git a/.github/ISSUE_TEMPLATE/006_nomination.yml b/.github/ISSUE_TEMPLATE/006_nomination.yml new file mode 100644 index 000000000000..fd2914cf2f4f --- /dev/null +++ b/.github/ISSUE_TEMPLATE/006_nomination.yml @@ -0,0 +1,57 @@ +name: Contributor Nomination +description: Nominate a GitHub user for the Contributor role with triage permissions +labels: [Role Nomination] +assignees: ['nashif'] +body: + - type: markdown + attributes: + value: | + ## Background + + The [TSC Project Roles](https://docs.zephyrproject.org/latest/project/project_roles.html) defines the main roles for the Zephyr Project, including Maintainer, Collaborator, and Contributor. + + By default, anyone who contributes code or documentation is a Contributor, but with the lowest [GitHub Permission Level](https://docs.github.com/en/organizations/managing-access-to-your-organizations-repositories/repository-roles-for-an-organization) of **Read**. + + Use this form to nominate a user for the **Contributor** role with **Triage** permission, which allows the user to: + - Add reviewers to pull requests + - Be added as a reviewer by others + + - type: input + id: full-name + attributes: + label: Full Name + description: Full name of the nominated contributor. + placeholder: e.g., Jane Doe + validations: + required: true + + - type: input + id: github-username + attributes: + label: GitHub Username + description: GitHub handle of the nominated contributor. + placeholder: e.g., @janedoe + validations: + required: true + + - type: input + id: organization + attributes: + label: Organization + description: Organization the nominee is affiliated with (optional). + placeholder: e.g., Acme Corp + validations: + required: false + + - type: textarea + id: supporting-documents + attributes: + label: Supporting Documents + description: Provide links to 3–5 pull requests authored or reviewed by the nominee that demonstrate their dedication to the Zephyr project. + placeholder: | + e.g., + - https://github.com/zephyrproject-rtos/zephyr/pull/12345 + - https://github.com/zephyrproject-rtos/zephyr/pull/23456 + - https://github.com/zephyrproject-rtos/zephyr/pull/34567 + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/007_ext-source.md b/.github/ISSUE_TEMPLATE/007_ext-source.md deleted file mode 100644 index 835450cd507e..000000000000 --- a/.github/ISSUE_TEMPLATE/007_ext-source.md +++ /dev/null @@ -1,68 +0,0 @@ ---- -name: External Source Code -about: Submit a proposal to integrate external source code -title: '' -labels: TSC -assignees: '' - ---- - -## Origin - -Name of project hosting the original open source code -Provide a link to the source - -## Purpose - -Brief description of what this software does - -## Mode of integration - -Describe whether you'd like to integrate this external component in the main tree -or as a module, and why. If the mode of integration is a module, suggest a -repository name for the module - -## Maintainership - -List the person(s) that will be maintaining the integration of this external code -for the foreseeable future. Please use GitHub IDs to identify them. You can -choose to identify a single maintainer only or add collaborators as well - -## Pull Request - -Pull request (if any) with the actual implementation of the integration, be it -in the main tree or as a module (pointing to your own fork for now). Make sure -the PR is correctly labeled as "DNM" - -## Description - -Long description that will help reviewers discuss suitability of the -component to solve the problem at hand (there may be a better options -available.) - -What is its primary functionality (e.g., SQLLite is a lightweight -database)? - -What problem are you trying to solve? (e.g., a state store is -required to maintain ...) - -Why is this the right component to solve it (e.g., SQLite is small, -easy to use, and has a very liberal license.) - -## Dependencies - -What other components does this package depend on? - -Will the Zephyr project have a direct dependency on the component, or -will it be included via an abstraction layer with this component as a -replaceable implementation? - -## Revision - -Version or SHA you would like to integrate initially - -## License - -Please use an SPDX identifier (https://spdx.org/licenses/), such as -``BSD-3-Clause`` - diff --git a/.github/ISSUE_TEMPLATE/007_ext-source.yml b/.github/ISSUE_TEMPLATE/007_ext-source.yml new file mode 100644 index 000000000000..741be93e1844 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/007_ext-source.yml @@ -0,0 +1,106 @@ +name: External Component Integration +description: Propose integration of an external open source component +labels: ["TSC"] +assignees: [] +body: + - type: textarea + id: origin + attributes: + label: Origin + description: Name of project hosting the original open source code. Provide a link to the source. + placeholder: e.g., SQLite - https://sqlite.org + validations: + required: true + + - type: textarea + id: purpose + attributes: + label: Purpose + description: Brief description of what this software does. + placeholder: | + e.g., A small, fast, self-contained SQL database engine. + validations: + required: true + + - type: textarea + id: integration-mode + attributes: + label: Mode of Integration + description: Should this be integrated in the main tree or as a module? Explain your choice and suggest a module repo name if applicable. + placeholder: | + e.g., As a module - proposed repo name: zephyr-sqlite + validations: + required: true + + - type: textarea + id: maintainership + attributes: + label: Maintainership + description: List maintainers (GitHub IDs) for this integration. Include at least one primary maintainer. + placeholder: | + e.g., @username1 (primary), @username2 (collaborator) + validations: + required: true + + - type: input + id: pull-request + attributes: + label: Pull Request + description: Link to the pull request (if any) for this integration. Must be labeled "DNM" (Do Not Merge). + placeholder: | + e.g., https://github.com/zephyrproject-rtos/zephyr/pull/12345 + validations: + required: false + + - type: textarea + id: description + attributes: + label: Description + description: Long-form description to justify suitability of this component. + placeholder: | + - What is its primary functionality? + - What problem does it solve? + - Why is this the right component? + validations: + required: true + + - type: textarea + id: security + attributes: + label: Security + description: Security-related aspects of this component, including cryptographic functions and known vulnerabilities. + placeholder: | + - Does it use cryptography? + - How are vulnerabilities handled? + - Any known CVEs? + validations: + required: false + + - type: textarea + id: dependencies + attributes: + label: Dependencies + description: What does this component depend on, and how will it be integrated (directly or via abstraction)? + placeholder: | + - Other external packages? + - Direct or abstracted use in Zephyr? + validations: + required: false + + - type: input + id: revision + attributes: + label: Version or SHA + description: Which version or specific commit should be initially integrated? + placeholder: e.g., v3.45.0 or 79cc94d + validations: + required: true + + - type: input + id: license + attributes: + label: License (SPDX) + description: Provide the license using a valid SPDX identifier (e.g., BSD-3-Clause). + placeholder: e.g., MIT or BSD-3-Clause + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/008_bin-blobs.md b/.github/ISSUE_TEMPLATE/008_bin-blobs.md deleted file mode 100644 index cde55e03bef9..000000000000 --- a/.github/ISSUE_TEMPLATE/008_bin-blobs.md +++ /dev/null @@ -1,41 +0,0 @@ ---- -name: Binary blobs -about: Submit a proposal to integrate binary blob(s) -title: '' -labels: TSC -assignees: '' - ---- - -## Origin - -Describe where the binary blob(s) originate from - -## Type - -- [ ] Precompiled library -- [ ] Firmware image - -## Module - -The Zephyr module that this blob(s) will be referenced from - -## Purpose - -Brief description of what the blob(s) do. It is especially important to describe -the functionality that the blob(s) provide, to the largest extent possible - -## Pull Request - -Link to the Pull request with the actual implementation of the integration. If -you are submitting this as part of a new module you may link to the same Pull -Request that introduced the new module. - -## Dependencies - -What other components do the blob(s) depend on, if any? - -## License - -Document the license the blob(s) are distributed under - diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 000000000000..b9ea2c585a49 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,5 @@ +blank_issues_enabled: false +contact_links: + - name: Zephyr Community Support + url: https://github.com/zephyrproject-rtos/zephyr/discussions + about: Please ask and answer questions here. diff --git a/.github/SECURITY.md b/.github/SECURITY.md index ba2dedb99e49..ffbaf1a6b622 100644 --- a/.github/SECURITY.md +++ b/.github/SECURITY.md @@ -11,9 +11,9 @@ updates: At this time, with the latest release of v4.0, the supported versions are: - - v4.0: Current release - - v3.7: Prior release and Current LTS - - v2.7: Prior LTS + - v4.1: Current release + - v4.0: Prior release + - v3.7: Current LTS ## Reporting process diff --git a/.github/codeql/codeql-actions-config.yml b/.github/codeql/codeql-actions-config.yml new file mode 100644 index 000000000000..4076bfd99c5a --- /dev/null +++ b/.github/codeql/codeql-actions-config.yml @@ -0,0 +1,2 @@ +paths: + - .github diff --git a/.github/codeql/codeql-js-config.yml b/.github/codeql/codeql-js-config.yml new file mode 100644 index 000000000000..6503a1fa80c9 --- /dev/null +++ b/.github/codeql/codeql-js-config.yml @@ -0,0 +1,2 @@ +paths: + - doc diff --git a/.github/dependabot.yml b/.github/dependabot.yml index a880296ea6d5..fc85287baa7a 100644 --- a/.github/dependabot.yml +++ b/.github/dependabot.yml @@ -1,4 +1,5 @@ version: 2 +enable-beta-ecosystems: true updates: - package-ecosystem: "github-actions" directory: "/" @@ -11,3 +12,15 @@ updates: actions-deps: patterns: - "*" + + - package-ecosystem: "uv" + directory: "/doc" + schedule: + interval: "weekly" + commit-message: + prefix: "ci: doc: " + labels: [] + groups: + doc-deps: + patterns: + - "*" diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index be3696c4d305..b4edf9c02a69 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -15,23 +15,36 @@ on: types: - labeled +permissions: + contents: read + jobs: assignment: name: Pull Request Assignment if: github.event.pull_request.draft == false - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + pull-requests: write # to add assignees to pull requests + issues: write # to add assignees to issues steps: - - name: Install Python dependencies - run: | - pip install -U PyGithub>=1.55 west - - name: Check out source code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes - name: Run assignment script env: - GITHUB_TOKEN: ${{ secrets.ZB_GITHUB_TOKEN }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | FLAGS="-v" FLAGS+=" -o ${{ github.event.repository.owner.login }}" diff --git a/.github/workflows/backport.yml b/.github/workflows/backport.yml index 5e28332c2a2d..3ecf66b17da9 100644 --- a/.github/workflows/backport.yml +++ b/.github/workflows/backport.yml @@ -7,10 +7,17 @@ on: branches: - main +permissions: + contents: read + jobs: backport: name: Backport - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + contents: write # to create/push backport branches + pull-requests: write # to create backport PRs + issues: write # to add labels to issue created if backport fails # Only react to merged PRs for security reasons. # See https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target. if: > @@ -24,8 +31,8 @@ jobs: ) steps: - name: Backport - uses: zephyrproject-rtos/action-backport@v2.0.3-3 + uses: zephyrproject-rtos/action-backport@7e74f601d11eaca577742445e87775b5651a965f # v2.0.3-3 with: - github_token: ${{ secrets.ZB_GITHUB_TOKEN }} + github_token: ${{ secrets.GITHUB_TOKEN }} issue_labels: Backport labels_template: '["Backport"]' diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index 2d2c4fda6a8b..29ec47852468 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -10,29 +10,41 @@ on: branches: - v*-branch +permissions: + contents: read + jobs: backport: name: Backport Issue Check concurrency: group: backport-issue-check-${{ github.ref }} cancel-in-progress: true - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository == 'zephyrproject-rtos/zephyr' + permissions: + issues: read # to check if associated issue exists for backport steps: - name: Check out source code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: Install Python dependencies + - name: Install Python packages run: | - pip install -U pygithub + pip install -r scripts/requirements-actions.txt --require-hashes - name: Run backport issue checker env: - GITHUB_TOKEN: ${{ secrets.ZB_GITHUB_TOKEN }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | ./scripts/release/list_backports.py \ - -o ${{ github.event.repository.owner.login }} \ - -r ${{ github.event.repository.name }} \ - -b ${{ github.event.pull_request.base.ref }} \ - -p ${{ github.event.pull_request.number }} + -o ${{ github.event.repository.owner.login }} \ + -r ${{ github.event.repository.name }} \ + -b ${{ github.event.pull_request.base.ref }} \ + -p ${{ github.event.pull_request.number }} diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index 5a4fbc0b39ff..4e9ed86b082f 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -5,20 +5,26 @@ on: workflows: ["BabbleSim Tests"] types: - completed + +permissions: + contents: read + jobs: bsim-test-results: name: "Publish BabbleSim Test Results" - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.event.workflow_run.conclusion != 'skipped' + permissions: + checks: write # to create the check run entry with test results steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@v8 + uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 with: run_id: ${{ github.event.workflow_run.id }} - name: Publish BabbleSim Test Results - uses: EnricoMi/publish-unit-test-result-action@v2 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: BabbleSim Test Results comment_mode: off diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 66d47c68a1c2..81473f734e7c 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -27,6 +27,10 @@ on: - "include/zephyr/net/ieee802154*" - "drivers/serial/*nrfx*" - "tests/drivers/uart/**" + - '!**.rst' + +permissions: + contents: read concurrency: group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} @@ -38,13 +42,16 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components EDTT_PATH: ../tools/edtt + permissions: + checks: write # to create the check run entry with test results + steps: - name: Apply container owner mismatch workaround run: | @@ -67,7 +74,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 @@ -91,7 +98,7 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Check common triggering files - uses: tj-actions/changed-files@v45 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-common-files with: files: | @@ -110,16 +117,17 @@ jobs: modules/hal_nordic/** - name: Check if Bluethooth files changed - uses: tj-actions/changed-files@v45 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-bluetooth-files with: files: | - tests/bsim/bluetooth/ samples/bluetooth/ subsys/bluetooth/ + tests/bluetooth/common/testlib/ + tests/bsim/bluetooth/ - name: Check if Networking files changed - uses: tj-actions/changed-files@v45 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-networking-files with: files: | @@ -132,7 +140,7 @@ jobs: include/zephyr/net/ieee802154* - name: Check if UART files changed - uses: tj-actions/changed-files@v45 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-uart-files with: files: | @@ -172,13 +180,12 @@ jobs: - name: Merge Test Results run: | - pip install junitparser junit2html junitparser merge --glob "./bsim_*/*bsim_results.*.xml" "./twister-out/twister.xml" junit.xml junit2html junit.xml junit.html - name: Upload Unit Test Results in HTML if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: HTML Unit Test Results if-no-files-found: ignore @@ -186,7 +193,7 @@ jobs: junit.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@v2 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: Bsim Test Results files: "junit.xml" @@ -194,7 +201,7 @@ jobs: - name: Upload Event Details if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: event path: | diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index f10dc718b6eb..befa8cdb8bf1 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -13,19 +13,30 @@ on: # Run daily at 14:05 - cron: '5 14 * * *' +permissions: + contents: read + jobs: make_bugs_pickle: name: Make bugs pickle - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository_owner == 'zephyrproject-rtos' steps: - name: Checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: Install Python dependencies + - name: Install Python packages run: | - pip install -U pygithub + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Snapshot bugs env: @@ -41,7 +52,7 @@ jobs: echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml new file mode 100644 index 000000000000..04bc190fd137 --- /dev/null +++ b/.github/workflows/clang.yaml @@ -0,0 +1,180 @@ +name: Build with Clang/LLVM +on: + push: + branches: + - main + - v*-branch + - collab-* +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} + cancel-in-progress: true + +jobs: + clang-build: + if: github.repository_owner == 'zephyrproject-rtos' + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge + container: + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + options: '--entrypoint /bin/bash' + strategy: + fail-fast: false + matrix: + subset: [1, 2] + env: + CCACHE_DIR: /node-cache/ccache-zephyr + CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + CCACHE_REMOTE_ONLY: "true" + CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' + LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-20 + BASE_REF: ${{ github.base_ref }} + steps: + - name: Apply container owner mismatch workaround + run: | + # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not + # match the container user UID because of the way GitHub + # Actions runner is implemented. Remove this workaround when + # GitHub comes up with a fundamental fix for this problem. + git config --global --add safe.directory ${GITHUB_WORKSPACE} + + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + + - name: Clone cached Zephyr repository + continue-on-error: true + run: | + git clone --shared /repo-cache/zephyrproject/zephyr . + git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} + + - name: Checkout + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + persist-credentials: false + + - name: Environment Setup + run: | + echo "$HOME/.local/bin" >> $GITHUB_PATH + git config --global user.email "bot@zephyrproject.org" + git config --global user.name "Zephyr Bot" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" + git clean -f -d + git log --pretty=oneline | head -n 10 + west init -l . || true + west config --global update.narrow true + west config manifest.group-filter -- +ci,+optional + # In some cases modules are left in a state where they can't be + # updated (i.e. when we cancel a job and the builder is killed), + # So first retry to update, if that does not work, remove all modules + # and start over. (Workaround until we implement more robust module + # west caching). + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west2.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) + + echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV + + - name: Check Environment + run: | + cmake --version + ${LLVM_TOOLCHAIN_PATH}/bin/clang --version + gcc --version + ls -la + + - name: Set up ccache + run: | + mkdir -p ${CCACHE_DIR} + ccache -M 10G + ccache -p + ccache -z -s -vv + + - name: Update BabbleSim to manifest revision + run: | + export BSIM_VERSION=$( west list bsim -f {revision} ) + echo "Manifest points to bsim sha $BSIM_VERSION" + cd /opt/bsim_west/bsim + git fetch -n origin ${BSIM_VERSION} + git -c advice.detachedHead=false checkout ${BSIM_VERSION} + west update + make everything -s -j 8 + + - name: Run Tests with Twister + id: twister + run: | + export ZEPHYR_BASE=${PWD} + export ZEPHYR_TOOLCHAIN_VARIANT=llvm + + ./scripts/twister -p native_sim --no-detailed-test-id --force-color --inline-logs -M -N -v --retry-failed 2 \ + -T tests --subset ${{matrix.subset}}/2 -j 16 + + - name: Print ccache stats + if: always() + run: | + ccache -s -vv + + - name: Upload Unit Test Results + if: always() + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 + with: + name: Unit Test Results (Subset ${{ matrix.subset }}) + path: | + twister-out/twister.xml + twister-out/twister.json + if-no-files-found: ignore + + clang-build-results: + name: "Publish Unit Tests Results" + needs: clang-build + runs-on: ubuntu-24.04 + permissions: + checks: write # to create GitHub annotations + if: (success() || failure()) + steps: + - name: Checkout + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + persist-credentials: false + + - name: Download Artifacts + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + with: + path: artifacts + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + + - name: Merge Test Results + run: | + junitparser merge artifacts/*/twister.xml junit.xml + junit2html junit.xml junit-clang.html + + - name: Upload Unit Test Results in HTML + if: always() + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 + with: + name: HTML Unit Test Results + if-no-files-found: ignore + path: | + junit-clang.html + + - name: Publish Unit Test Results + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + if: always() + with: + check_name: Unit Test Results + files: "**/twister.xml" + comment_mode: off diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 5707610ae87b..0a048b95f283 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -4,6 +4,9 @@ on: schedule: - cron: '25 06,18 * * *' +permissions: + contents: read + concurrency: group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} cancel-in-progress: true @@ -14,7 +17,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -61,10 +64,21 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: west setup run: | west init -l . || true @@ -85,24 +99,13 @@ jobs: ccache -p ccache -z -s -vv - - name: Update BabbleSim to manifest revision - run: | - export BSIM_VERSION=$( west list bsim -f {revision} ) - echo "Manifest points to bsim sha $BSIM_VERSION" - cd /opt/bsim_west/bsim - git fetch -n origin ${BSIM_VERSION} - git -c advice.detachedHead=false checkout ${BSIM_VERSION} - west update - make everything -s -j 8 - - name: Run Tests with Twister (Push) continue-on-error: true run: | export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr mkdir -p coverage/reports - pip install gcovr==6.0 - ./scripts/twister -E ${{matrix.normalized}}-testplan.json + ./scripts/twister --save-tests ${{matrix.normalized}}-testplan.json ls -la ./scripts/twister \ -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage \ @@ -121,7 +124,7 @@ jobs: - name: Upload Coverage Results if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: Coverage Data (Subset ${{ matrix.normalized }}) path: | @@ -131,18 +134,29 @@ jobs: codecov-results: name: "Publish Coverage Results" needs: codecov - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 # the codecov job might be skipped, we don't need to run this job then if: success() || failure() steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Download Artifacts - uses: actions/download-artifact@v4 + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 with: path: coverage/reports @@ -182,7 +196,6 @@ jobs: - name: Merge coverage files run: | pushd ./coverage/reports - pip install gcovr==6.0 gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --json merged.json gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --cobertura merged.xml popd @@ -198,7 +211,6 @@ jobs: - name: Generate Coverage Report if: always() run: | - pip install xlsxwriter ijson python3 ./scripts/ci/coverage/coverage_analysis.py \ -t native_sim-testplan.json \ -m MAINTAINERS.yml \ @@ -209,7 +221,7 @@ jobs: - name: Upload Merged Coverage Results and Report if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: Coverage Data and report path: | @@ -220,7 +232,7 @@ jobs: - name: Upload coverage to Codecov if: always() - uses: codecov/codecov-action@v5 + uses: codecov/codecov-action@ad3126e916f78f00edff4ed0317cf185271ccc2d # v5.4.2 with: env_vars: OS,PYTHON fail_ci_if_error: false diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml new file mode 100644 index 000000000000..869467e030a8 --- /dev/null +++ b/.github/workflows/codeql.yml @@ -0,0 +1,58 @@ +name: "CodeQL" + +on: + push: + branches: + - main + - v*-branch + - collab-* + schedule: + - cron: '34 16 * * 3' + pull_request: + branches: + - main + - v*-branch + - collab-* + +permissions: + contents: read +jobs: + analyze: + name: Analyze (${{ matrix.language }}) + runs-on: ubuntu-24.04 + permissions: + security-events: write + strategy: + fail-fast: false + matrix: + include: + - language: python + build-mode: none + - language: actions + build-mode: none + config: ./.github/codeql/codeql-actions-config.yml + - language: javascript-typescript + build-mode: none + config: ./.github/codeql/codeql-js-config.yml + steps: + - name: Checkout + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Initialize CodeQL + uses: github/codeql-action/init@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + with: + languages: ${{ matrix.language }} + build-mode: ${{ matrix.build-mode }} + queries: security-extended + config-file: ${{ matrix.config }} + + - if: matrix.build-mode == 'manual' + shell: bash + run: | + echo "nothing yet" + exit 0 + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + with: + category: "/language:${{matrix.language}}" diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index 81c20b372d9a..b574199cff16 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -2,27 +2,30 @@ name: Coding Guidelines on: pull_request +permissions: + contents: read + jobs: compliance_job: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 name: Run coding guidelines checks on patch series (PR) steps: - name: Checkout the code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - - name: cache-pip - uses: actions/cache@v4 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ hashFiles('.github/workflows/coding_guidelines.yml') }} + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: Install python dependencies + - name: Install Python packages run: | - pip install unidiff - pip install sh + pip install -r scripts/requirements-actions.txt --require-hashes - name: Install Packages run: | diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 1875de7cb7e8..9d1621cc4d3a 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -8,9 +8,12 @@ on: - reopened - synchronize +permissions: + contents: read + jobs: check_compliance: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 name: Run compliance checks on patch series (PR) steps: - name: Update PATH for west @@ -18,7 +21,7 @@ jobs: echo "$HOME/.local/bin" >> $GITHUB_PATH - name: Checkout the code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -41,20 +44,15 @@ jobs: git log --pretty=oneline | head -n 10 - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: 3.11 - - - name: cache-pip - uses: actions/cache@v4 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ hashFiles('.github/workflows/compliance.yml') }} + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: Install python dependencies + - name: Install Python packages run: | - pip install -r scripts/requirements-compliance.txt - pip install west + pip install -r scripts/requirements-actions.txt --require-hashes - name: west setup run: | @@ -62,14 +60,6 @@ jobs: west config manifest.group-filter -- +ci,-optional west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log - - name: Check for PR description - if: ${{ github.event.pull_request.body == '' }} - continue-on-error: true - id: pr_description - run: | - echo "Pull request description cannot be empty." - exit 1 - - name: Run Compliance Tests continue-on-error: true id: compliance @@ -82,11 +72,15 @@ jobs: git log --pretty=oneline | head -n 10 # Increase rename limit to allow for large PRs git config diff.renameLimit 10000 - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e SysbuildKconfigBasic -e ClangFormat \ - -c origin/${BASE_REF}.. + excludes="-e KconfigBasic -e SysbuildKconfigBasic -e ClangFormat" + # The signed-off-by check for dependabot should be skipped + if [ "${{ github.actor }}" == "dependabot[bot]" ]; then + excludes="$excludes -e Identity" + fi + ./scripts/ci/check_compliance.py --annotate $excludes -c origin/${BASE_REF}.. - name: upload-results - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 continue-on-error: true with: name: compliance.xml diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 3a43ac643008..4b89661a8afe 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -10,28 +10,38 @@ on: branches: - refs/tags/* +permissions: + contents: read + jobs: get_version: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository == 'zephyrproject-rtos/zephyr' steps: - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} aws-region: us-east-1 - - name: install-pip - run: | - pip install gitpython - - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Upload to AWS S3 run: | python3 scripts/ci/version_mgr.py --update . diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index 345eb5b7db08..bf61725c2600 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -20,6 +20,9 @@ on: - 'scripts/dts/**' - '.github/workflows/devicetree_checks.yml' +permissions: + contents: read + jobs: devicetree-checks: name: Devicetree script tests @@ -30,39 +33,19 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} - - name: cache-pip-linux - if: startsWith(runner.os, 'Linux') - uses: actions/cache@v4 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: cache-pip-mac - if: startsWith(runner.os, 'macOS') - uses: actions/cache@v4 - with: - path: ~/Library/Caches/pip - # Trailing '-' was just to get a different cache name - key: ${{ runner.os }}-pip-${{ matrix.python-version }}- - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }}- - - name: cache-pip-win - if: startsWith(runner.os, 'Windows') - uses: actions/cache@v4 - with: - path: ~\AppData\Local\pip\Cache - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: install python dependencies + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages run: | - pip install pytest pyyaml tox + pip install -r scripts/requirements-actions.txt --require-hashes + - name: run tox working-directory: scripts/dts/python-devicetree run: | diff --git a/.github/workflows/do_not_merge.yml b/.github/workflows/do_not_merge.yml deleted file mode 100644 index 8d90efa981de..000000000000 --- a/.github/workflows/do_not_merge.yml +++ /dev/null @@ -1,21 +0,0 @@ -name: Do Not Merge - -on: - pull_request: - types: [synchronize, opened, reopened, labeled, unlabeled] - -jobs: - do-not-merge: - name: Prevent Merging - runs-on: ubuntu-22.04 - steps: - - name: Check for label - if: ${{ contains(github.event.*.labels.*.name, 'DNM') || - contains(github.event.*.labels.*.name, 'DNM (manifest)') || - contains(github.event.*.labels.*.name, 'TSC') || - contains(github.event.*.labels.*.name, 'Architecture Review') || - contains(github.event.*.labels.*.name, 'dev-review') }} - run: | - echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'." - echo "This workflow fails so that the pull request cannot be merged." - exit 1 diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index d263c1c80b6e..bc147ee38179 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -11,33 +11,28 @@ on: - v* pull_request: +permissions: + contents: read + env: - # NOTE: west docstrings will be extracted from the version listed here - WEST_VERSION: 1.2.0 - # The latest CMake available directly with apt is 3.18, but we need >=3.20 - # so we fetch that through pip. - CMAKE_VERSION: 3.20.5 DOXYGEN_VERSION: 1.12.0 - # Job count is set to 2 less than the vCPU count of 16 because the total available RAM is 32GiB - # and each sphinx-build process may use more than 2GiB of RAM. - JOB_COUNT: 14 + DOXYGEN_MD5SUM: fd96a5defa535dfe2e987b46540844a4 + JOB_COUNT: 4 jobs: doc-file-check: name: Check for doc changes - runs-on: ubuntu-22.04 - if: > - github.repository_owner == 'zephyrproject-rtos' + runs-on: ubuntu-24.04 outputs: file_check: ${{ steps.check-doc-files.outputs.any_modified }} steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Check if Documentation related files changed - uses: tj-actions/changed-files@v45 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-doc-files with: files: | @@ -48,7 +43,6 @@ jobs: kernel/include/kernel_arch_interface.h lib/libc/** subsys/testsuite/ztest/include/** - tests/ **/Kconfig* west.yml scripts/dts/ @@ -61,9 +55,8 @@ jobs: name: "Documentation Build (HTML)" needs: [doc-file-check] if: > - github.repository_owner == 'zephyrproject-rtos' && - ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) - runs-on: ubuntu-22.04 + needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' + runs-on: ubuntu-24.04 timeout-minutes: 90 concurrency: group: doc-build-html-${{ github.ref }} @@ -75,15 +68,21 @@ jobs: sudo apt-get update sudo apt-get install -y wget python3-pip git ninja-build graphviz lcov wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" + echo "${DOXYGEN_MD5SUM} doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | md5sum -c + if [ $? -ne 0 ]; then + echo "Failed to verify doxygen tarball" + exit 1 + fi sudo tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz -C /opt echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH echo "${HOME}/.local/bin" >> $GITHUB_PATH - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 + path: zephyr - name: Rebase if: github.event_name == 'pull_request' @@ -91,6 +90,7 @@ jobs: env: BASE_REF: ${{ github.base_ref }} PR_HEAD: ${{ github.event.pull_request.head.sha }} + working-directory: zephyr run: | git config --global user.email "actions@zephyrproject.org" git config --global user.name "Github Actions" @@ -100,25 +100,27 @@ jobs: git clean -f -d git log --graph --oneline HEAD...${PR_HEAD} - - name: cache-pip - uses: actions/cache@v4 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: - path: ~/.cache/pip - key: pip-${{ hashFiles('doc/requirements.txt') }} + python-version: 3.12 + cache: pip + cache-dependency-path: doc/requirements.txt - - name: install-pip - run: | - pip install -r doc/requirements.txt - pip install west==${WEST_VERSION} - pip install cmake==${CMAKE_VERSION} - pip install coverxygen + - name: Setup Zephyr project + uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + with: + app-path: zephyr + toolchains: 'all' - - name: west setup + - name: install-pip + working-directory: zephyr run: | - west init -l . + pip install -r doc/requirements.txt --require-hashes - name: build-docs shell: bash + working-directory: zephyr run: | if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then DOC_TAG="release" @@ -144,22 +146,23 @@ jobs: genhtml --no-function-coverage --no-branch-coverage new.info -o coverage-report - name: compress-docs + working-directory: zephyr run: | tar --use-compress-program="xz -T0" -cf html-output.tar.xz --exclude html/_sources --exclude html/doxygen/xml --directory=doc/_build html tar --use-compress-program="xz -T0" -cf api-output.tar.xz --directory=doc/_build html/doxygen/html tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report - name: upload-build - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: html-output - path: html-output.tar.xz + path: zephyr/html-output.tar.xz - name: upload-api-coverage - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: api-coverage - path: api-coverage.tar.xz + path: zephyr/api-coverage.tar.xz - name: process-pr if: github.event_name == 'pull_request' @@ -176,7 +179,7 @@ jobs: echo "API Coverage Report will be available shortly at: ${API_COVERAGE_URL}" >> $GITHUB_STEP_SUMMARY - name: upload-pr-number - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 if: github.event_name == 'pull_request' with: name: pr_num @@ -186,52 +189,56 @@ jobs: name: "Documentation Build (PDF)" needs: [doc-file-check] if: | - github.event_name != 'pull_request' && - github.repository_owner == 'zephyrproject-rtos' - runs-on: ubuntu-22.04 - container: texlive/texlive:latest + github.event_name != 'pull_request' + runs-on: ubuntu-24.04 timeout-minutes: 120 concurrency: group: doc-build-pdf-${{ github.ref }} cancel-in-progress: true steps: - - name: Apply container owner mismatch workaround - run: | - git config --global --add safe.directory ${GITHUB_WORKSPACE} - - name: checkout - uses: actions/checkout@v4 - - - name: install-pkgs - run: | - apt-get update - apt-get install -y python3-pip python3-venv ninja-build doxygen graphviz librsvg2-bin imagemagick + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + path: zephyr - - name: cache-pip - uses: actions/cache@v4 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: - path: ~/.cache/pip - key: pip-${{ hashFiles('doc/requirements.txt') }} + python-version: 3.12 + cache: pip + cache-dependency-path: doc/requirements.txt - - name: setup-venv + - name: install-pkgs run: | - python3 -m venv .venv - . .venv/bin/activate - echo PATH=$PATH >> $GITHUB_ENV + sudo apt-get update + sudo apt-get install --no-install-recommends graphviz librsvg2-bin \ + texlive-latex-base texlive-latex-extra latexmk \ + texlive-fonts-recommended texlive-fonts-extra texlive-xetex \ + imagemagick fonts-noto xindy + wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" + echo "${DOXYGEN_MD5SUM} doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | md5sum -c + if [ $? -ne 0 ]; then + echo "Failed to verify doxygen tarball" + exit 1 + fi + sudo tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz -C /opt + echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH - - name: install-pip - run: | - pip install -r doc/requirements.txt - pip install west==${WEST_VERSION} - pip install cmake==${CMAKE_VERSION} + - name: Setup Zephyr project + uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + with: + app-path: zephyr + toolchains: 'arm-zephyr-eabi' - - name: west setup + - name: install-pip-pkgs + working-directory: zephyr run: | - west init -l . + pip install -r doc/requirements.txt --require-hashes - name: build-docs shell: bash + working-directory: zephyr continue-on-error: true run: | if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then @@ -247,13 +254,13 @@ jobs: - name: upload-build if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: pdf-output if-no-files-found: ignore path: | - doc/_build/latex/zephyr.pdf - doc/_build/latex/zephyr.log + zephyr/doc/_build/latex/zephyr.pdf + zephyr/doc/_build/latex/zephyr.log doc-build-status-check: if: always() diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index d75bcad78561..9552d72b3d9f 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -10,10 +10,13 @@ on: types: - completed +permissions: + contents: read + jobs: doc-publish: name: Publish Documentation - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: | github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' && @@ -22,7 +25,7 @@ jobs: steps: - name: Download artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@v8 + uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -30,7 +33,7 @@ jobs: - name: Load PR number if: steps.download-artifacts.outputs.found_artifact == 'true' - uses: actions/github-script@v7 + uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1 with: script: | let fs = require("fs"); @@ -40,7 +43,7 @@ jobs: - name: Check PR number if: steps.download-artifacts.outputs.found_artifact == 'true' id: check-pr - uses: carpentries/actions/check-valid-pr@v0.14.0 + uses: carpentries/actions/check-valid-pr@2e20fd5ee53b691e27455ce7ca3b16ea885140e8 # v0.15.0 with: pr: ${{ env.PR_NUM }} sha: ${{ github.event.workflow_run.head_sha }} @@ -63,7 +66,7 @@ jobs: - name: Configure AWS Credentials if: steps.download-artifacts.outputs.found_artifact == 'true' - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index 89349ed66973..89afeb4ed1b9 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -13,10 +13,13 @@ on: types: - completed +permissions: + contents: read + jobs: doc-publish: name: Publish Documentation - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: | github.event.workflow_run.event != 'pull_request' && github.event.workflow_run.conclusion == 'success' && @@ -24,7 +27,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@v8 + uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -37,7 +40,7 @@ jobs: fi - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index d3fe1b0dcae4..d41d97b9d427 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -6,11 +6,14 @@ on: - 'lib/libc/minimal/include/errno.h' - 'scripts/ci/errno.py' +permissions: + contents: read + jobs: check-errno: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.27.4 + image: ghcr.io/zephyrproject-rtos/ci:v0.28.0 steps: - name: Apply container owner mismatch workaround @@ -22,7 +25,7 @@ jobs: git config --global --add safe.directory ${GITHUB_WORKSPACE} - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Environment Setup run: | diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index 78f761cb545c..1e4eeaa76b46 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -16,6 +16,9 @@ on: # same commit - 'v*' +permissions: + contents: read + concurrency: group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} cancel-in-progress: true @@ -26,7 +29,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' defaults: run: @@ -58,14 +61,24 @@ jobs: run: | sudo apt-get update sudo apt-get install -y python3-venv - pip install -U gitpython - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Environment Setup run: | echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV @@ -77,7 +90,7 @@ jobs: west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} @@ -94,7 +107,6 @@ jobs: run: | python3 -m venv .venv . .venv/bin/activate - pip install awscli aws s3 sync --quiet footprint_data/ s3://testing.zephyrproject.org/footprint_data/ - name: Transform Footprint data to Twister JSON reports @@ -113,7 +125,6 @@ jobs: ELASTICSEARCH_INDEX: ${{ vars.FOOTPRINT_TRACKING_INDEX }} run: | shopt -s globstar - pip install -U elasticsearch run_date=`date --iso-8601=minutes` python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ --flatten footprint \ diff --git a/.github/workflows/greet_first_time_contributor.yml b/.github/workflows/greet_first_time_contributor.yml index 5f62c03d6def..ae69fd5cc012 100644 --- a/.github/workflows/greet_first_time_contributor.yml +++ b/.github/workflows/greet_first_time_contributor.yml @@ -6,14 +6,20 @@ on: pull_request_target: types: [opened, closed] +permissions: + contents: read + jobs: check_for_first_interaction: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository == 'zephyrproject-rtos/zephyr' + permissions: + pull-requests: write # to comment on pull requests + issues: write # to comment on issues steps: - - uses: actions/checkout@v4 - - uses: zephyrproject-rtos/action-first-interaction@v1.1.1-zephyr-5 + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - uses: zephyrproject-rtos/action-first-interaction@58853996b1ac504b8e0f6964301f369d2bb22e5c # v1.1.1+zephyr.6 with: repo-token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index f267688b1f0a..27166aa993a3 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -16,6 +16,9 @@ on: - '.github/workflows/hello_world_multiplatform.yaml' - 'SDK_VERSION' +permissions: + contents: read + concurrency: group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} cancel-in-progress: true @@ -29,7 +32,7 @@ jobs: runs-on: ${{ matrix.os }} steps: - name: Checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: path: zephyr fetch-depth: 0 @@ -51,15 +54,15 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.11 - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@v1 + uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 with: app-path: zephyr - toolchains: all + toolchains: aarch64-zephyr-elf:arc-zephyr-elf:arc64-zephyr-elf:arm-zephyr-eabi:mips-zephyr-elf:riscv64-zephyr-elf:sparc-zephyr-elf:x86_64-zephyr-elf:xtensa-dc233c_zephyr-elf:xtensa-sample_controller32_zephyr-elf - name: Build firmware working-directory: zephyr @@ -74,7 +77,7 @@ jobs: - name: Upload artifacts if: failure() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: if-no-files-found: ignore path: diff --git a/.github/workflows/issue_count.yml b/.github/workflows/issue_count.yml index 7d6ed6dfc3e2..0ab24ef5f647 100644 --- a/.github/workflows/issue_count.yml +++ b/.github/workflows/issue_count.yml @@ -4,6 +4,9 @@ on: schedule: - cron: '*/10 * * * *' +permissions: + contents: read + env: OUTPUT_FILE_NAME: IssuesReport.md COMMITTER_EMAIL: actions@github.com @@ -14,7 +17,7 @@ env: jobs: track-issues: name: "Collect Issue Stats" - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository == 'zephyrproject-rtos/zephyr' steps: @@ -27,7 +30,7 @@ jobs: sudo apt-get update sudo apt-get install discount - - uses: brcrista/summarize-issues@v4 + - uses: brcrista/summarize-issues@54c549b7d38b7db39e5c6e06fd9617e12e5c3491 # v4 with: title: 'Issues Report for ${{ github.repository }}' configPath: 'issues-report-config.json' @@ -35,14 +38,14 @@ jobs: token: ${{ secrets.GITHUB_TOKEN }} - name: upload-stats - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 continue-on-error: true with: name: ${{ env.OUTPUT_FILE_NAME }} path: ${{ env.OUTPUT_FILE_NAME }} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@v4 + uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/license_check.yml b/.github/workflows/license_check.yml index 7d2d083faae0..212c76366598 100644 --- a/.github/workflows/license_check.yml +++ b/.github/workflows/license_check.yml @@ -2,22 +2,25 @@ name: Scancode on: [pull_request] +permissions: + contents: read + jobs: scancode_job: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 name: Scan code for licenses steps: - name: Checkout the code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 - name: Scan the code id: scancode - uses: zephyrproject-rtos/action_scancode@v4 + uses: zephyrproject-rtos/action_scancode@23ef91ce31cd4b954366a7b71eea47520da9b380 # v4 with: directory-to-scan: 'scan/' - name: Artifact Upload - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: scancode path: ./artifacts diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index 8cfd17695afc..c0ab05502fd6 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -2,33 +2,49 @@ name: Manifest on: pull_request_target: +permissions: + contents: read + jobs: contribs: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + pull-requests: write # to create/update pull request comments name: Manifest steps: - name: Checkout the code - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: path: zephyrproject/zephyr ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 persist-credentials: false + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + cd zephyrproject/zephyr + pip install -r scripts/requirements-actions.txt --require-hashes + - name: west setup env: BASE_REF: ${{ github.base_ref }} working-directory: zephyrproject/zephyr run: | - pip install west git config --global user.email "you@example.com" git config --global user.name "Your Name" west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@v1.7.0 + uses: zephyrproject-rtos/action-manifest@1729cded3fc798cf0de4a789c596dcb9c40eb14c # v1.9.1 with: - github-token: ${{ secrets.ZB_GITHUB_TOKEN }} + github-token: ${{ secrets.GITHUB_TOKEN }} manifest-path: 'west.yml' checkout-path: 'zephyrproject/zephyr' use-tree-checkout: 'true' @@ -37,3 +53,5 @@ jobs: verbosity-level: '1' labels: 'manifest' dnm-labels: 'DNM (manifest)' + blobs-added-labels: 'Binary Blobs Added' + blobs-modified-labels: 'Binary Blobs Modified' diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml new file mode 100644 index 000000000000..c89eb7464f76 --- /dev/null +++ b/.github/workflows/pinned-gh-actions.yml @@ -0,0 +1,19 @@ +name: Check SHA-pinned GitHub Actions + +on: + pull_request: + paths: + - '.github/workflows/**' + +permissions: + contents: read + +jobs: + check-sha-pinned-actions: + name: Verify GitHub Actions + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Ensure SHA pinned actions + uses: zgosalvez/github-actions-ensure-sha-pinned-actions@2d6823da4039243036c86d76f503c84e2ded2517 # v3.0.24 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml new file mode 100644 index 000000000000..91c997279df8 --- /dev/null +++ b/.github/workflows/pr_metadata_check.yml @@ -0,0 +1,47 @@ +name: PR Metadata Check + +on: + pull_request: + types: + - synchronize + - opened + - reopened + - labeled + - unlabeled + - edited + +permissions: + contents: read + +jobs: + do-not-merge: + name: Prevent Merging + runs-on: ubuntu-24.04 + steps: + - name: Checkout + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python dependencies + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + + - name: Run the check script + run: | + ./scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" + + empty_pr_description: + if: ${{ github.event.pull_request.body == '' }} + name: PR Description + runs-on: ubuntu-24.04 + steps: + - name: Check for PR description + run: | + echo "Pull request description cannot be empty." + exit 1 diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index bf9d82892122..edf38bad2b9c 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -19,6 +19,9 @@ on: - 'scripts/pylib/build_helpers/**' - '.github/workflows/pylib_tests.yml' +permissions: + contents: read + jobs: pylib-tests: name: Misc. Pylib Unit Tests @@ -26,25 +29,21 @@ jobs: strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-22.04] + os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} - - name: cache-pip-linux - if: startsWith(runner.os, 'Linux') - uses: actions/cache@v4 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: install-packages + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages run: | - pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt + pip install -r scripts/requirements-actions.txt --require-hashes - name: Run pytest for build_helpers env: ZEPHYR_BASE: ./ diff --git a/.github/workflows/ready-to-merge.yml b/.github/workflows/ready-to-merge.yml index 897a60445221..01f08e8a4b67 100644 --- a/.github/workflows/ready-to-merge.yml +++ b/.github/workflows/ready-to-merge.yml @@ -7,6 +7,9 @@ on: type: string required: true +permissions: + contents: read + jobs: all_jobs_passed: name: all jobs passed diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index c7e71324c1d2..91f4037a2e2c 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -6,11 +6,16 @@ on: - 'v*' - '!v*rc*' +permissions: + contents: read + jobs: release: - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + contents: write # to create GitHub release entry steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 @@ -21,12 +26,12 @@ jobs: echo "TRIMMED_VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT - name: REUSE Compliance Check - uses: fsfe/reuse-action@v5 + uses: fsfe/reuse-action@bb774aa972c2a89ff34781233d275075cbddf542 # v5.0.0 with: args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx - name: upload-results - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 continue-on-error: true with: name: zephyr-${{ steps.get_version.outputs.VERSION }}.spdx @@ -38,7 +43,7 @@ jobs: - name: Create Release id: create_release - uses: actions/create-release@v1 + uses: actions/create-release@0cb9c9b65d5d1901c1f53e5e66eaf4afd303e70e # v1.1.4 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} with: @@ -50,7 +55,7 @@ jobs: - name: Upload Release Assets id: upload-release-asset - uses: actions/upload-release-asset@v1 + uses: actions/upload-release-asset@e8f9f06c4b078e705bd2ea027f0926603fc9b4d5 # v1.0.2 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} with: diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index e2325da0a4ac..3d4471e70a58 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -29,12 +29,12 @@ jobs: steps: - name: "Checkout code" - uses: actions/checkout@692973e3d937129bcbf40652eb9f2f61becf3332 # v4.1.7 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: persist-credentials: false - name: "Run analysis" - uses: ossf/scorecard-action@62b2cac7ed8198b15735ed49ab1e5cf35480ba46 # v2.4.0 + uses: ossf/scorecard-action@f49aabe0b5af0936a0987cfb85d86b75731b0186 # v2.4.1 with: results_file: results.sarif results_format: sarif @@ -47,7 +47,7 @@ jobs: # uploads of run results in SARIF format to the repository Actions tab. # https://docs.github.com/en/actions/advanced-guides/storing-workflow-data-as-artifacts - name: "Upload artifact" - uses: actions/upload-artifact@89ef406dd8d7e03cfd12d9e0a4a378f454709029 # v4.3.5 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: SARIF file path: results.sarif @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@afb54ba388a7dca6ecae48f608c4ff05ff4cc77a # v3.25.15 + uses: github/codeql-action/upload-sarif@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 with: sarif_file: results.sarif diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 06e12ada528c..4140dacbd63d 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -19,6 +19,9 @@ on: - 'scripts/build/**' - '.github/workflows/scripts_tests.yml' +permissions: + contents: read + jobs: scripts-tests: name: Scripts tests @@ -26,10 +29,10 @@ jobs: strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-20.04] + os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -49,22 +52,15 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: cache-pip-linux - if: startsWith(runner.os, 'Linux') - uses: actions/cache@v4 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - - name: install-packages + - name: Install Python packages run: | - pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt + pip install -r scripts/requirements-actions.txt --require-hashes - name: Run pytest env: diff --git a/.github/workflows/stale-workflow-queue-cleanup.yml b/.github/workflows/stale-workflow-queue-cleanup.yml index ec1a4cc716fb..f40d5b928da8 100644 --- a/.github/workflows/stale-workflow-queue-cleanup.yml +++ b/.github/workflows/stale-workflow-queue-cleanup.yml @@ -7,6 +7,9 @@ on: # everyday at 15:00 - cron: '0 15 * * *' +permissions: + contents: read + concurrency: group: stale-workflow-queue-cleanup cancel-in-progress: true @@ -14,11 +17,13 @@ concurrency: jobs: cleanup: name: Cleanup - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + actions: write # to delete stale workflow runs steps: - name: Delete stale queued workflow runs - uses: MajorScruffy/delete-old-workflow-runs@v0.3.0 + uses: MajorScruffy/delete-old-workflow-runs@78b5af714fefaefdf74862181c467b061782719e # v0.3.0 with: repository: ${{ github.repository }} # Remove any workflow runs in "queued" state for more than 1 day diff --git a/.github/workflows/stale_issue.yml b/.github/workflows/stale_issue.yml index f71e485ff8ee..ec59d2641d90 100644 --- a/.github/workflows/stale_issue.yml +++ b/.github/workflows/stale_issue.yml @@ -3,13 +3,20 @@ on: schedule: - cron: "16 00 * * *" +permissions: + contents: read + jobs: stale: name: Find Stale issues and PRs - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 if: github.repository == 'zephyrproject-rtos/zephyr' + permissions: + pull-requests: write # to comment on stale pull requests + issues: write # to comment on stale issues + steps: - - uses: actions/stale@v9 + - uses: actions/stale@5bef64f19d7facfb25b37b414482c7164d639639 # v9.1.0 with: stale-pr-message: 'This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index 0f86958e47b7..5ca8eb9aa9d5 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -6,13 +6,28 @@ on: - main - v*-branch types: [closed] + +permissions: + contents: read + jobs: record_merged: if: github.event.pull_request.merged == true && github.repository == 'zephyrproject-rtos/zephyr' - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: PR event env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} @@ -20,5 +35,4 @@ jobs: ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" PR_STAT_ES_INDEX: ${{ vars.PR_STAT_ES_INDEX }} run: | - pip install pygithub elasticsearch python3 ./scripts/ci/stats/merged_prs.py --pull-request ${{ github.event.pull_request.number }} --repo ${{ github.repository }} diff --git a/.github/workflows/twister-prep.yaml b/.github/workflows/twister-prep.yaml deleted file mode 100644 index 51bc771059d6..000000000000 --- a/.github/workflows/twister-prep.yaml +++ /dev/null @@ -1,147 +0,0 @@ -name: Prepare For a Twister Run - -on: - workflow_call: - outputs: - subset: - description: subset - value: ${{ jobs.prep_push.outputs.subset != '' && jobs.prep_push.outputs.subset || jobs.prep_pr.outputs.subset }} - size: - description: size - value: ${{ jobs.prep_push.outputs.size != '' && jobs.prep_push.outputs.size || jobs.prep_pr.outputs.size }} - fullrun: - description: fullrun - value: ${{ jobs.prep_push.outputs.fullrun != '' && jobs.prep_push.outputs.fullrun || jobs.prep_pr.outputs.size }} - -jobs: - prep_pr: - if: github.repository_owner == 'zephyrproject-rtos' && github.event_name == 'pull_request_target' - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge - container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 - options: '--entrypoint /bin/bash' - outputs: - subset: ${{ steps.output-services.outputs.subset }} - size: ${{ steps.output-services.outputs.size }} - fullrun: ${{ steps.output-services.outputs.fullrun }} - env: - MATRIX_SIZE: 10 - PUSH_MATRIX_SIZE: 20 - DAILY_MATRIX_SIZE: 80 - BSIM_OUT_PATH: /opt/bsim/ - BSIM_COMPONENTS_PATH: /opt/bsim/components - TESTS_PER_BUILDER: 700 - COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} - BASE_REF: ${{ github.base_ref }} - steps: - - name: Apply container owner mismatch workaround - run: | - # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not - # match the container user UID because of the way GitHub - # Actions runner is implemented. Remove this workaround when - # GitHub comes up with a fundamental fix for this problem. - git config --global --add safe.directory ${GITHUB_WORKSPACE} - - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - - name: Clone cached Zephyr repository - continue-on-error: true - run: | - git clone --shared /repo-cache/zephyrproject/zephyr . - git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - - - name: Checkout - uses: actions/checkout@v4 - with: - ref: ${{ github.event.pull_request.head.sha }} - fetch-depth: 0 - persist-credentials: false - - - name: Environment Setup - run: | - git config --global user.email "bot@zephyrproject.org" - git config --global user.name "Zephyr Bot" - rm -fr ".git/rebase-apply" - rm -fr ".git/rebase-merge" - git rebase origin/${BASE_REF} - git clean -f -d - git log --pretty=oneline | head -n 10 - west init -l . || true - west config manifest.group-filter -- +ci,+optional - west config --global update.narrow true - west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) - west forall -c 'git reset --hard HEAD' - - echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - - - name: Generate Test Plan with Twister - id: test-plan - run: | - export ZEPHYR_BASE=${PWD} - export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER - if [ -s .testplan ]; then - cat .testplan >> $GITHUB_ENV - else - echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV - fi - rm -f testplan.json .testplan - - - name: Determine matrix size - id: output-services - run: | - if [ -n "${TWISTER_NODES}" ]; then - subset="[$(seq -s',' 1 ${TWISTER_NODES})]" - else - subset="[$(seq -s',' 1 ${MATRIX_SIZE})]" - fi - size=${TWISTER_NODES} - - echo "subset=${subset}" >> $GITHUB_OUTPUT - echo "size=${size}" >> $GITHUB_OUTPUT - echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT - - prep_push: - if: github.repository_owner == 'zephyrproject-rtos' && (github.event_name == 'push' || github.event_name == 'schedule') - runs-on: ubuntu-22.04 - outputs: - subset: ${{ steps.output-services.outputs.subset }} - size: ${{ steps.output-services.outputs.size }} - fullrun: ${{ steps.output-services.outputs.fullrun }} - env: - MATRIX_SIZE: 10 - PUSH_MATRIX_SIZE: 20 - DAILY_MATRIX_SIZE: 80 - BSIM_OUT_PATH: /opt/bsim/ - BSIM_COMPONENTS_PATH: /opt/bsim/components - TESTS_PER_BUILDER: 700 - COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} - BASE_REF: ${{ github.base_ref }} - steps: - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - - name: Determine matrix size - id: output-services - run: | - if [ "${{github.event_name}}" = "push" ]; then - subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]" - size=${MATRIX_SIZE} - elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then - subset="[$(seq -s',' 1 ${DAILY_MATRIX_SIZE})]" - size=${DAILY_MATRIX_SIZE} - else - size=0 - fi - - echo "subset=${subset}" >> $GITHUB_OUTPUT - echo "size=${size}" >> $GITHUB_OUTPUT - echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index 77078f8fdbcb..8c700a81f38c 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -8,26 +8,38 @@ on: types: - completed +permissions: + contents: read + jobs: upload-to-elasticsearch: if: | github.repository == 'zephyrproject-rtos/zephyr' && - github.event.workflow_run.event != 'pull_request_target' + github.event.workflow_run.event != 'pull_request' env: ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }} ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 steps: # Needed for elasticearch and upload script - name: Checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: fetch-depth: 0 persist-credentials: false + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@v8 + uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 with: path: artifacts workflow: twister.yml @@ -37,7 +49,6 @@ jobs: - name: Upload to elasticsearch if: steps.download-artifacts.outputs.found_artifact == 'true' run: | - pip install elasticsearch # set run date on upload to get consistent and unified data across the matrix. run_date=`date --iso-8601=minutes` if [ "${{github.event.workflow_run.event}}" = "push" ]; then diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 668813b5c519..b8ddd8e82caf 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -6,14 +6,17 @@ on: - main - v*-branch - collab-* - pull_request_target: + pull_request: branches: - main - v*-branch - collab-* schedule: - # Run at 03:00 UTC on every Sunday - - cron: '0 3 * * 0' + # Run at 02:00 UTC on every Sunday + - cron: '0 2 * * 0' + +permissions: + contents: read concurrency: group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }} @@ -21,7 +24,102 @@ concurrency: jobs: twister-build-prep: - uses: ./.github/workflows/twister-prep.yaml + if: github.repository_owner == 'zephyrproject-rtos' + runs-on: ubuntu-24.04 + outputs: + subset: ${{ steps.output-services.outputs.subset }} + size: ${{ steps.output-services.outputs.size }} + fullrun: ${{ steps.output-services.outputs.fullrun }} + env: + MATRIX_SIZE: 10 + PUSH_MATRIX_SIZE: 20 + WEEKLY_MATRIX_SIZE: 200 + BSIM_OUT_PATH: /opt/bsim/ + BSIM_COMPONENTS_PATH: /opt/bsim/components + TESTS_PER_BUILDER: 900 + COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} + BASE_REF: ${{ github.base_ref }} + steps: + - name: Checkout + if: github.event_name == 'pull_request' + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + path: zephyr + persist-credentials: false + + - name: Set up Python + if: github.event_name == 'pull_request' + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: install-packages + working-directory: zephyr + if: github.event_name == 'pull_request' + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + + - name: Setup Zephyr project + if: github.event_name == 'pull_request' + uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + with: + app-path: zephyr + toolchains: all + + - name: Environment Setup + working-directory: zephyr + if: github.event_name == 'pull_request' + run: | + git config --global user.email "bot@zephyrproject.org" + git config --global user.name "Zephyr Bot" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" + git rebase origin/${BASE_REF} + git clean -f -d + git log --pretty=oneline | head -n 10 + + - name: Generate Test Plan with Twister + working-directory: zephyr + if: github.event_name == 'pull_request' + id: test-plan + run: | + export ZEPHYR_BASE=${PWD} + export ZEPHYR_TOOLCHAIN_VARIANT=zephyr + python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER + if [ -s .testplan ]; then + cat .testplan >> $GITHUB_ENV + else + echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV + fi + rm -f testplan.json .testplan + + - name: Determine matrix size + id: output-services + run: | + if [ "${{github.event_name}}" = "push" ]; then + subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]" + size=${MATRIX_SIZE} + elif [ "${{github.event_name}}" = "pull_request" ]; then + if [ -n "${TWISTER_NODES}" ]; then + subset="[$(seq -s',' 1 ${TWISTER_NODES})]" + else + subset="[$(seq -s',' 1 ${MATRIX_SIZE})]" + fi + size=${TWISTER_NODES} + elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then + subset="[$(seq -s',' 1 ${WEEKLY_MATRIX_SIZE})]" + size=${WEEKLY_MATRIX_SIZE} + else + size=0 + fi + + echo "subset=${subset}" >> $GITHUB_OUTPUT + echo "size=${size}" >> $GITHUB_OUTPUT + echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT twister-build: runs-on: @@ -29,7 +127,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -44,13 +142,13 @@ jobs: CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components - TWISTER_COMMON: '--no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' - WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered' - PR_OPTIONS: ' --clobber-output --integration' - PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered' + TWISTER_COMMON: ' --test-config tests/test_config_ci.yaml --no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' + WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered -j 32' + PR_OPTIONS: ' --clobber-output --integration -j 16' + PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered -j 16' COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} - LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 + LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-20 steps: - name: Print cloud service information run: | @@ -73,7 +171,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -81,7 +179,7 @@ jobs: - name: Environment Setup run: | - if [ "${{github.event_name}}" = "pull_request_target" ]; then + if [ "${{github.event_name}}" = "pull_request" ]; then git config --global user.email "bot@zephyrproject.org" git config --global user.name "Zephyr Builder" rm -fr ".git/rebase-apply" @@ -143,7 +241,7 @@ jobs: fi fi - - if: github.event_name == 'pull_request_target' + - if: github.event_name == 'pull_request' name: Run Tests with Twister (Pull Request) id: run_twister_pr run: | @@ -180,7 +278,7 @@ jobs: - name: Upload Unit Test Results if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: Unit Test Results (Subset ${{ matrix.subset }}) if-no-files-found: ignore @@ -202,7 +300,7 @@ jobs: - if: matrix.subset == 1 && github.event_name == 'push' name: Upload the list of Python packages - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: Frozen PIP package set path: | @@ -212,41 +310,53 @@ jobs: name: "Publish Unit Tests Results" needs: - twister-build - runs-on: ubuntu-22.04 + runs-on: ubuntu-24.04 + permissions: + checks: write # to create the check run entry with Twister test results # the build-and-test job might be skipped, we don't need to run this job then if: success() || failure() steps: - name: Check out source code - if: needs.twister-build.result == 'failure' - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 persist-credentials: false + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Download Artifacts - uses: actions/download-artifact@v4 + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 with: path: artifacts - name: Merge Test Results run: | - pip install junitparser junit2html junitparser merge artifacts/*/*/twister.xml junit.xml junit2html junit.xml junit.html - - name: Upload Unit Test Results in HTML + - name: Upload Unit Test Results if: always() - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: - name: HTML Unit Test Results + name: Unit Test Results if-no-files-found: ignore path: | junit.html + junit.xml - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@v2 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: Unit Test Results files: "**/twister.xml" @@ -263,7 +373,7 @@ jobs: - name: Upload Twister Analysis Results if: needs.twister-build.result == 'failure' - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2 with: name: Twister Analysis Results if-no-files-found: ignore diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 66409bce8763..bb95812b7be6 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -26,6 +26,9 @@ on: - '.github/workflows/twister_tests.yml' - 'scripts/schemas/twister/' +permissions: + contents: read + jobs: twister-tests: name: Twister Unit Tests @@ -33,25 +36,22 @@ jobs: strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-22.04] + os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} - - name: cache-pip-linux - if: startsWith(runner.os, 'Linux') - uses: actions/cache@v4 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: install-packages + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages run: | - pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt + pip install -r scripts/requirements-actions.txt --require-hashes + - name: Run pytest for twisterlib env: ZEPHYR_BASE: ./ diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index cd24a2a39aea..6cc922adb613 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -15,66 +15,172 @@ on: - 'scripts/tests/twister_blackbox/**' - '.github/workflows/twister_tests_blackbox.yml' +permissions: + contents: read + +env: + PYTHONIOENCODING: utf-8 + jobs: twister-tests: name: Twister Black Box Tests - runs-on: ${{ matrix.os }} strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-22.04] - container: - image: ghcr.io/zephyrproject-rtos/ci:v0.27.4 - + os: [ubuntu-24.04, macos-14, windows-2022] + fail-fast: false + runs-on: ${{ matrix.os }} steps: - - name: Apply Container Owner Mismatch Workaround - run: | - # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not - # match the container user UID because of the way GitHub - # Actions runner is implemented. Remove this workaround when - # GitHub comes up with a fundamental fix for this problem. - git config --global --add safe.directory ${GITHUB_WORKSPACE} - - name: Checkout - uses: actions/checkout@v4 - - - name: Environment Setup - run: | - echo "$HOME/.local/bin" >> $GITHUB_PATH - - west init -l . || true - # we do not depend on any hals, tools or bootloader, save some time and space... - west config manifest.group-filter -- -hal,-tools,-bootloader,-babblesim - west config manifest.project-filter -- -nrf_hw_models - west config --global update.narrow true - west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) - west forall -c 'git reset --hard HEAD' - - echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + path: zephyr + fetch-depth: 0 - name: Set Up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} + cache: pip + cache-dependency-path: scripts/requirements-actions.txt - - name: Go Into Venv - shell: bash - run: | - python3 -m pip install --user virtualenv - python3 -m venv env - source env/bin/activate - echo "$(which python)" - - - name: Install Packages - run: | - python3 -m pip install -U -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt + - name: Setup Zephyr project + uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + with: + app-path: zephyr + toolchains: all - name: Run Pytest For Twister Black Box Tests + if: ${{ startsWith(runner.os, 'ubuntu') }} + working-directory: zephyr shell: bash env: ZEPHYR_BASE: ./ ZEPHYR_TOOLCHAIN_VARIANT: zephyr run: | + export ZEPHYR_SDK_INSTALL_DIR=${{ github.workspace }}/zephyr-sdk echo "Run twister tests" source zephyr-env.sh - PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox + PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/ + + - name: Build firmware No. 1 - basic + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS + + - name: Build firmware No. 2 - save and load with emulation only + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --save-tests tests.file $BASIC_FLAGS + ./scripts/twister --load-tests tests.file --emulation-only $BASIC_FLAGS + rm tests.file + + - name: Build firmware No. 3 - print out test plan + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --test-tree -T tests/kernel/spinlock $BASIC_FLAGS + + - name: Build firmware No. 4 - integration, exclude tag, filter, shuffle, dry run + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --dry-run --integration --subset 1/3 --shuffle-tests --shuffle-tests-seed 1 --filter runnable --exclude-tag audio --exclude-tag driver $BASIC_FLAGS + + - name: Build firmware No. 5 - test, arch, vendor, exclude-platform, platform-reports + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --test kernel.multiprocessing.spinlock --arch x86 --exclude-platform qemu_x86_64 --vendor qemu --platform-reports $BASIC_FLAGS + + - name: Build firmware No. 6 - subtest, platform, rom-ram report, ROM footprint report from buildlog, size report + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS + + - name: Build firmware No. 7 - list tags + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS + + - name: Build firmware No. 8 - list tests + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister -T tests/posix/common --list-tests $BASIC_FLAGS + + - name: Build firmware No. 9 - report flags - dir, name, suffix, summary, all-options, filtered + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS + + - name: Build firmware No. 10 - force platform and toolchain, log level, timestamps, logfile + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS + rm log.file diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index dc75c7578cc6..c391148b5812 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -23,8 +23,11 @@ on: - 'scripts/west_commands/**' - '.github/workflows/west_cmds.yml' +permissions: + contents: read + jobs: - west-commnads: + west-commands: name: West Command Tests runs-on: ${{ matrix.os }} strategy: @@ -33,43 +36,24 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@v4 + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} - - name: cache-pip-linux - if: startsWith(runner.os, 'Linux') - uses: actions/cache@v4 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: cache-pip-mac - if: startsWith(runner.os, 'macOS') - uses: actions/cache@v4 - with: - path: ~/Library/Caches/pip - # Trailing '-' was just to get a different cache name - key: ${{ runner.os }}-pip-${{ matrix.python-version }}- - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }}- - - name: cache-pip-win - if: startsWith(runner.os, 'Windows') - uses: actions/cache@v4 - with: - path: ~\AppData\Local\pip\Cache - key: ${{ runner.os }}-pip-${{ matrix.python-version }} - restore-keys: | - ${{ runner.os }}-pip-${{ matrix.python-version }} - - name: install pytest + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages run: | - pip install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree junitparser + pip install -r scripts/requirements-actions.txt --require-hashes + - name: run pytest-win if: runner.os == 'Windows' run: | python ./scripts/west_commands/run_tests.py + - name: run pytest-mac-linux if: runner.os != 'Windows' run: | diff --git a/.gitlint b/.gitlint index e83edce6b6e6..16e9bdca9aaa 100644 --- a/.gitlint +++ b/.gitlint @@ -59,3 +59,7 @@ ignore-merge-commits=false # By specifying this rule, developers can only change the file when they explicitly reference # it in the commit message. #files=gitlint/rules.py,README.md + +[ignore-by-author-name] +regex=^dependabot\[bot\]$ +ignore=all diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 269a0c9fcf17..e7d51e2294f0 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -43,6 +43,9 @@ "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] +"./doc/_scripts/gen_devicetree_rest.py" = [ + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string +] "./doc/_scripts/redirects.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long ] @@ -233,15 +236,7 @@ "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting ] "./scripts/build/gen_relocate_app.py" = [ - "B028", # https://docs.astral.sh/ruff/rules/no-explicit-stacklevel "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get - "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import - "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation ] "./scripts/build/gen_strerror_table.py" = [ "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders @@ -421,11 +416,10 @@ "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/dts/gen_driver_kconfig_dts.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] "./scripts/dts/gen_dts_cmake.py" = [ @@ -436,24 +430,11 @@ "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/dts/python-devicetree/src/devicetree/dtlib.py" = [ - "E701", # https://docs.astral.sh/ruff/rules/multiple-statements-on-one-line-colon - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM201", # https://docs.astral.sh/ruff/rules/negate-equal-op - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import - "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/src/devicetree/edtlib.py" = [ - "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except - "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict - "E713", # https://docs.astral.sh/ruff/rules/not-in-test - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import - "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/src/devicetree/grutils.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long @@ -467,7 +448,7 @@ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/tests/test_edtlib.py" = [ "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict @@ -592,7 +573,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP032", # https://docs.astral.sh/ruff/rules/f-string "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import @@ -634,7 +615,6 @@ ] "./scripts/logging/dictionary/dictionary_parser/log_parser_v3.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get ] "./scripts/logging/dictionary/dictionary_parser/mipi_syst.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -691,9 +671,6 @@ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py" = [ - "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception -] "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -748,6 +725,9 @@ "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler "UP012", # https://docs.astral.sh/ruff/rules/unnecessary-encode-utf8 ] +"./scripts/pylib/pytest-twister-harness/tests/resources/zen_of_python.py" = [ + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string +] "./scripts/pylib/twister/expr_parser.py" = [ "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool "SIM110", # https://docs.astral.sh/ruff/rules/reimplemented-builtin @@ -794,7 +774,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM117", # https://docs.astral.sh/ruff/rules/multiple-with-statements "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/set_assignees.py" = [ @@ -811,11 +791,6 @@ "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] -"./scripts/support/quartus-flash.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler -] "./scripts/tests/twister/conftest.py" = [ "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -1100,42 +1075,9 @@ "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler "UP004", # https://docs.astral.sh/ruff/rules/useless-object-inheritance "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] -"./scripts/west_commands/bindesc.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance -] -"./scripts/west_commands/blobs.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/west_commands/build.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/build_helpers.py" = [ - "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/completion.py" = [ - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/debug.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/export.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/west_commands/fetchers/__init__.py" = [ "UP032", # https://docs.astral.sh/ruff/rules/f-string ] @@ -1148,14 +1090,6 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler ] -"./scripts/west_commands/flash.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/robot.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] "./scripts/west_commands/run_common.py" = [ "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict @@ -1183,12 +1117,7 @@ "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters "UP032", # https://docs.astral.sh/ruff/rules/f-string ] -"./scripts/west_commands/simulate.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] "./scripts/west_commands/spdx.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] @@ -1227,9 +1156,8 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] "./scripts/west_commands/tests/test_nrf.py" = [ - "B011", # https://docs.astral.sh/ruff/rules/assert-false "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/west_commands/tests/test_nxp_s32dbg.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long @@ -1262,51 +1190,6 @@ "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP032", # https://docs.astral.sh/ruff/rules/f-string ] -"./scripts/west_commands/zspdx/cmakecache.py" = [ - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/cmakefileapi.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/cmakefileapijson.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM116", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-lookup - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/datatypes.py" = [ - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/getincludes.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP021", # https://docs.astral.sh/ruff/rules/replace-universal-newlines - "UP022", # https://docs.astral.sh/ruff/rules/replace-stdout-stderr -] -"./scripts/west_commands/zspdx/sbom.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/scanner.py" = [ - "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/walker.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/writer.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/zephyr_module.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -1373,7 +1256,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./tests/drivers/can/host/pytest/test_can.py" = [ @@ -1388,6 +1271,11 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP032", # https://docs.astral.sh/ruff/rules/f-string ] +"./tests/lib/devicetree/memory_region_flags/pytest/test_memory_region_flags.py" = [ + "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] "./tests/misc/check_init_priorities/validate_check_init_priorities_output.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes @@ -1447,6 +1335,7 @@ exclude = [ "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py", "./doc/_extensions/zephyr/api_overview.py", "./doc/_extensions/zephyr/application.py", + "./doc/_extensions/zephyr/domain/__init__.py", "./doc/_extensions/zephyr/doxybridge.py", "./doc/_extensions/zephyr/doxyrunner.py", "./doc/_extensions/zephyr/doxytooltip/__init__.py", @@ -1498,7 +1387,6 @@ exclude = [ "./scripts/build/gen_kobject_list.py", "./scripts/build/gen_kobject_placeholders.py", "./scripts/build/gen_offset_header.py", - "./scripts/build/gen_relocate_app.py", "./scripts/build/gen_strerror_table.py", "./scripts/build/gen_strsignal_table.py", "./scripts/build/gen_symtab.py", @@ -1517,6 +1405,7 @@ exclude = [ "./scripts/ci/guideline_check.py", "./scripts/ci/stats/merged_prs.py", "./scripts/ci/test_plan.py", + "./scripts/ci/twister_report_analyzer.py", "./scripts/ci/upload_test_results_es.py", "./scripts/ci/version_mgr.py", "./scripts/coredump/coredump_gdbserver.py", @@ -1581,7 +1470,6 @@ exclude = [ "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/qemu_adapter.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/mcumgr.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py", "./scripts/pylib/pytest-twister-harness/tests/conftest.py", @@ -1619,7 +1507,6 @@ exclude = [ "./scripts/release/list_devicetree_bindings_changes.py", "./scripts/set_assignees.py", "./scripts/snippets.py", - "./scripts/support/quartus-flash.py", "./scripts/tests/twister/conftest.py", "./scripts/tests/twister/pytest_integration/test_harness_pytest.py", "./scripts/tests/twister/test_cmakecache.py", @@ -1686,6 +1573,7 @@ exclude = [ "./scripts/west_commands/fetchers/core.py", "./scripts/west_commands/fetchers/http.py", "./scripts/west_commands/flash.py", + "./scripts/west_commands/patch.py", "./scripts/west_commands/robot.py", "./scripts/west_commands/run_common.py", "./scripts/west_commands/run_tests.py", @@ -1707,7 +1595,6 @@ exclude = [ "./scripts/west_commands/runners/mdb.py", "./scripts/west_commands/runners/misc.py", "./scripts/west_commands/runners/native.py", - "./scripts/west_commands/runners/nios2.py", "./scripts/west_commands/runners/nrf_common.py", "./scripts/west_commands/runners/nrfjprog.py", "./scripts/west_commands/runners/nrfutil.py", @@ -1769,6 +1656,7 @@ exclude = [ "./soc/nuvoton/npcx/common/ecst/ecst.py", "./soc/nuvoton/npcx/common/ecst/ecst_args.py", "./soc/silabs/silabs_sim3/sim3u/gen_crossbar_config.py", + "./tests/bluetooth/classic/sdp_s/pytest/test_sdp.py", "./tests/boot/with_mcumgr/pytest/test_downgrade_prevention.py", "./tests/boot/with_mcumgr/pytest/test_upgrade.py", "./tests/boot/with_mcumgr/pytest/west_sign_wrapper.py", @@ -1777,8 +1665,8 @@ exclude = [ "./tests/drivers/can/host/pytest/test_can.py", "./tests/kernel/timer/timer_behavior/pytest/saleae_logic2.py", "./tests/kernel/timer/timer_behavior/pytest/test_timer.py", + "./tests/lib/devicetree/memory_region_flags/pytest/test_memory_region_flags.py", "./tests/misc/check_init_priorities/validate_check_init_priorities_output.py", - "./tests/misc/llext-edk/pytest/test_edk.py", "./tests/net/lib/lwm2m/interop/pytest/conftest.py", "./tests/net/lib/lwm2m/interop/pytest/leshan.py", "./tests/net/lib/lwm2m/interop/pytest/test_blockwise.py", diff --git a/CMakeLists.txt b/CMakeLists.txt index 16a471ae6ee6..0effc0c381cd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,6 +71,15 @@ set(ZEPHYR_CURRENT_LINKER_PASS 0) set(ZEPHYR_CURRENT_LINKER_CMD linker_zephyr_pre${ZEPHYR_CURRENT_LINKER_PASS}.cmd) set(ZEPHYR_LINK_STAGE_EXECUTABLE zephyr_pre${ZEPHYR_CURRENT_LINKER_PASS}) +# Make kconfig variables available to the linker script generator +zephyr_linker_include_generated(KCONFIG ${CMAKE_CURRENT_BINARY_DIR}/.config) + +# The linker generator also needs sections.h to be able to access e.g. _APP_SMEM_SECTION_NAME +# for linkerscripts that do not support c-preprocessing. +zephyr_linker_include_generated(HEADER ${ZEPHYR_BASE}/include/zephyr/linker/sections.h) + +zephyr_linker_include_var(VAR CMAKE_VERBOSE_MAKEFILE VALUE ${CMAKE_VERBOSE_MAKEFILE}) + # ZEPHYR_PREBUILT_EXECUTABLE is used outside of this file, therefore keep the # existing variable to allow slowly cleanup of linking stage handling. # Three stage linking active: pre0 -> pre1 -> final, this will correspond to `pre1` @@ -87,7 +96,6 @@ set(OFFSETS_H_TARGET offsets_h) set(SYSCALL_LIST_H_TARGET syscall_list_h_target) set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target) set(KOBJ_TYPES_H_TARGET kobj_types_h_target) -set(PARSE_SYSCALLS_TARGET parse_syscalls_target) set(DEVICE_API_LD_TARGET device_api_ld_target) define_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT BRIEF_DOCS " " FULL_DOCS " ") @@ -174,13 +182,17 @@ endif() # @Intent: Set compiler flags to detect general stack overflows across all functions if(CONFIG_STACK_CANARIES) - zephyr_compile_options($) + zephyr_compile_options("$<$:$>") + zephyr_compile_options("$<$:$>") elseif(CONFIG_STACK_CANARIES_STRONG) - zephyr_compile_options($) + zephyr_compile_options("$<$:$>") + zephyr_compile_options("$<$:$>") elseif(CONFIG_STACK_CANARIES_ALL) - zephyr_compile_options($) + zephyr_compile_options("$<$:$>") + zephyr_compile_options("$<$:$>") elseif(CONFIG_STACK_CANARIES_EXPLICIT) - zephyr_compile_options($) + zephyr_compile_options("$<$:$>") + zephyr_compile_options("$<$:$>") endif() # @Intent: Obtain compiler optimizations flags and store in variables @@ -227,7 +239,8 @@ SOC_* symbol.") endif() # Apply the final optimization flag(s) -zephyr_compile_options(${OPTIMIZATION_FLAG}) +zephyr_compile_options($<$:${OPTIMIZATION_FLAG}>) +zephyr_compile_options($<$:${OPTIMIZATION_FLAG}>) if(CONFIG_LTO) zephyr_compile_options($) @@ -315,7 +328,9 @@ if(CONFIG_CODING_GUIDELINE_CHECK) endif() # @Intent: Set compiler specific macro inclusion of AUTOCONF_H -zephyr_compile_options("SHELL: $ ${AUTOCONF_H}") +zephyr_compile_options("SHELL: $<$:$ ${AUTOCONF_H}>") +zephyr_compile_options("SHELL: $<$:$ ${AUTOCONF_H}>") +zephyr_compile_options("SHELL: $<$:$ ${AUTOCONF_H}>") if(CONFIG_COMPILER_FREESTANDING) # @Intent: Set compiler specific flag for bare metal freestanding option @@ -328,6 +343,18 @@ if (CONFIG_PICOLIBC AND NOT CONFIG_PICOLIBC_IO_FLOAT) zephyr_compile_options($<$:$>) endif() +if(CONFIG_UBSAN) + zephyr_compile_options($<$:$>) + zephyr_link_libraries($) + if(CONFIG_UBSAN_LIBRARY) + zephyr_compile_options($<$:$>) + zephyr_link_libraries($) + elseif(CONFIG_UBSAN_TRAP) + zephyr_compile_options($<$:$>) + zephyr_link_libraries($) + endif() +endif() + # @Intent: Set compiler specific flag for tentative definitions, no-common zephyr_compile_options($) @@ -360,7 +387,9 @@ zephyr_compile_options($<$:$ # @Intent: Enforce standard integer type correspondence to match Zephyr usage. # (must be after compiler specific flags) if(CONFIG_ENFORCE_ZEPHYR_STDINT) - zephyr_compile_options("SHELL: $ ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h") + zephyr_compile_options("SHELL:$<$:$ ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>") + zephyr_compile_options("SHELL:$<$:$ ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>") + zephyr_compile_options("SHELL:$<$:$ ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>") endif() # Common toolchain-agnostic assembly flags @@ -804,7 +833,7 @@ add_custom_command( --file-list ${syscalls_file_list_output} $<$:--emit-all-syscalls> DEPENDS ${syscalls_subdirs_trigger} ${PARSE_SYSCALLS_HEADER_DEPENDS} - ${syscalls_file_list_output} ${syscalls_interface} + ${syscalls_file_list_output} syscalls_interface ) # Make sure Picolibc is built before the rest of the system; there's no explicit @@ -822,12 +851,6 @@ set_property(TARGET ${SYSCALL_LIST_H_TARGET} ${CMAKE_CURRENT_BINARY_DIR}/include/generated/zephyr/syscalls ) -add_custom_target(${PARSE_SYSCALLS_TARGET} - DEPENDS - ${syscalls_json} - ${struct_tags_json} - ) - # 64-bit systems do not require special handling of 64-bit system call # parameters or return values, indicate this to the system call boilerplate # generation script. @@ -870,30 +893,24 @@ add_custom_command( COMMAND ${LEGACY_SYSCALL_LIST_H_ARGS} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS ${PARSE_SYSCALLS_TARGET} + DEPENDS ${syscalls_json} ) -# This is passed into all calls to the gen_kobject_list.py script. -set(gen_kobject_list_include_args --include-subsystem-list ${struct_tags_json}) +include(${ZEPHYR_BASE}/cmake/kobj.cmake) set(DRV_VALIDATION ${PROJECT_BINARY_DIR}/include/generated/zephyr/driver-validation.h) -add_custom_command( - OUTPUT ${DRV_VALIDATION} - COMMAND - ${PYTHON_EXECUTABLE} - ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py - --validation-output ${DRV_VALIDATION} - ${gen_kobject_list_include_args} - $<$:--verbose> - DEPENDS - ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py - ${PARSE_SYSCALLS_TARGET} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} +gen_kobject_list( + TARGET ${DRIVER_VALIDATION_H_TARGET} + OUTPUTS ${DRV_VALIDATION} + SCRIPT_ARGS --validation-output ${DRV_VALIDATION} + INCLUDES ${struct_tags_json} + DEPENDS ${struct_tags_json} ) -add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION}) -include(${ZEPHYR_BASE}/cmake/kobj.cmake) -gen_kobj(KOBJ_INCLUDE_PATH) +gen_kobject_list_headers( + INCLUDES ${struct_tags_json} + DEPENDS ${struct_tags_json} + ) # Generate sections for kernel device subsystems set( @@ -926,6 +943,8 @@ add_custom_target(${DEVICE_API_LD_TARGET} ${DEVICE_API_LINKER_SECTIONS_CMAKE} ) +zephyr_linker_include_generated(CMAKE ${DEVICE_API_LINKER_SECTIONS_CMAKE}) + # Add a pseudo-target that is up-to-date when all generated headers # are up-to-date. @@ -1085,12 +1104,20 @@ if(CONFIG_CODE_DATA_RELOCATION) endif() if(CONFIG_USERSPACE) - zephyr_get_compile_options_for_lang_as_string(C compiler_flags_priv) + # Go for raw properties here since zephyr_get_compile_options_for_lang() + # processes the list of options, and wraps it in a $" "" - NO_COVERAGE_FLAGS "${compiler_flags_priv}" - ) + KOBJECT_HASH_COMPILE_OPTIONS "${compiler_flags_priv}") + + list(APPEND KOBJECT_HASH_COMPILE_OPTIONS + $ + $) - set(GEN_KOBJ_LIST ${ZEPHYR_BASE}/scripts/build/gen_kobject_list.py) set(PROCESS_GPERF ${ZEPHYR_BASE}/scripts/build/process_gperf.py) endif() @@ -1118,8 +1145,6 @@ elseif(DEFINED BOARD_LINKER_SCRIPT) set(LINKER_SCRIPT ${BOARD_LINKER_SCRIPT}) elseif(DEFINED SOC_LINKER_SCRIPT) set(LINKER_SCRIPT ${SOC_LINKER_SCRIPT}) -else() - find_package(Deprecated COMPONENTS SEARCHED_LINKER_SCRIPT) endif() if(NOT EXISTS ${LINKER_SCRIPT}) @@ -1127,14 +1152,20 @@ if(NOT EXISTS ${LINKER_SCRIPT}) endif() if(CONFIG_USERSPACE) - set(APP_SMEM_ALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_aligned.ld") - set(APP_SMEM_UNALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_unaligned.ld") + if(CONFIG_CMAKE_LINKER_GENERATOR) + set(APP_SMEM_LD_EXT "cmake") + else() + set(APP_SMEM_LD_EXT "ld") + endif() + + set(APP_SMEM_ALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_aligned.${APP_SMEM_LD_EXT}") + set(APP_SMEM_UNALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_unaligned.${APP_SMEM_LD_EXT}") if(CONFIG_LINKER_USE_PINNED_SECTION) set(APP_SMEM_PINNED_ALIGNED_LD - "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_aligned.ld") + "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_aligned.${APP_SMEM_LD_EXT}") set(APP_SMEM_PINNED_UNALIGNED_LD - "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_unaligned.ld") + "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_unaligned.${APP_SMEM_LD_EXT}") if(NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) # The libc partition may hold symbols that are required during boot process, @@ -1199,9 +1230,11 @@ if(CONFIG_USERSPACE) set(APP_SMEM_UNALIGNED_LIB app_smem_unaligned_output_obj_renamed_lib) list(APPEND LINKER_PASS_${ZEPHYR_CURRENT_LINKER_PASS}_DEFINE "LINKER_APP_SMEM_UNALIGNED") -endif() -if (CONFIG_USERSPACE) + foreach(dep ${APP_SMEM_UNALIGNED_LD} ${APP_SMEM_PINNED_UNALIGNED_LD}) + zephyr_linker_include_generated(CMAKE ${dep} PASS LINKER_APP_SMEM_UNALIGNED) + endforeach() + add_custom_command( OUTPUT ${APP_SMEM_ALIGNED_LD} ${APP_SMEM_PINNED_ALIGNED_LD} COMMAND ${PYTHON_EXECUTABLE} @@ -1221,6 +1254,9 @@ if (CONFIG_USERSPACE) COMMAND_EXPAND_LISTS COMMENT "Generating app_smem_aligned linker section" ) + foreach(dep ${APP_SMEM_ALIGNED_LD} ${APP_SMEM_PINNED_ALIGNED_LD}) + zephyr_linker_include_generated(CMAKE ${dep} PASS NOT LINKER_APP_SMEM_UNALIGNED) + endforeach() endif() if(CONFIG_USERSPACE) @@ -1235,23 +1271,13 @@ if(CONFIG_USERSPACE) set(KOBJECT_PREBUILT_HASH_OUTPUT_SRC_PRE kobject_prebuilt_hash_preprocessed.c) set(KOBJECT_PREBUILT_HASH_OUTPUT_SRC kobject_prebuilt_hash.c) - add_custom_command( + gen_kobject_list_gperf( + TARGET kobj_prebuilt_hash_list OUTPUT ${KOBJECT_PREBUILT_HASH_LIST} - COMMAND - ${PYTHON_EXECUTABLE} - ${GEN_KOBJ_LIST} - --kernel $ - --gperf-output ${KOBJECT_PREBUILT_HASH_LIST} - ${gen_kobject_list_include_args} - $<$:--verbose> - DEPENDS - ${ZEPHYR_LINK_STAGE_EXECUTABLE} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + KERNEL_TARGET ${ZEPHYR_LINK_STAGE_EXECUTABLE} + INCLUDES ${struct_tags_json} + DEPENDS ${struct_tags_json} ) - add_custom_target( - kobj_prebuilt_hash_list - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_PREBUILT_HASH_LIST} - ) add_custom_command( OUTPUT ${KOBJECT_PREBUILT_HASH_OUTPUT_SRC_PRE} @@ -1288,11 +1314,13 @@ if(CONFIG_USERSPACE) add_library( kobj_prebuilt_hash_output_lib OBJECT ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_PREBUILT_HASH_OUTPUT_SRC} - ) + ) - set_source_files_properties(${KOBJECT_PREBUILT_HASH_OUTPUT_SRC} - PROPERTIES COMPILE_FLAGS - "${NO_COVERAGE_FLAGS} -fno-function-sections -fno-data-sections") + # set_target_properties sets ALL properties, target_compile_options() adds + # and KOBJECT_HASH_COMPILE_OPTIONS contains all the options. + set_target_properties(kobj_prebuilt_hash_output_lib PROPERTIES + COMPILE_OPTIONS "${KOBJECT_HASH_COMPILE_OPTIONS}" + ) target_compile_definitions(kobj_prebuilt_hash_output_lib PRIVATE $ @@ -1328,6 +1356,13 @@ if(CONFIG_USERSPACE) DEPENDS ${KOBJECT_LINKER_HEADER_DATA} ) + + # gen_kobject_placeholders.py generates linker-kobject-prebuild-data.h, + # linker-kobject-prebuild-priv-stacks.h and linker-kobject-prebuild-rodata.h + foreach(ext "-data.h" "-priv-stacks.h" "-rodata.h") + string(REGEX REPLACE "-data.h$" ${ext} file ${KOBJECT_LINKER_HEADER_DATA}) + zephyr_linker_include_generated(HEADER ${file} PASS LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL) + endforeach() endif() if(CONFIG_USERSPACE OR CONFIG_DEVICE_DEPS) @@ -1435,23 +1470,13 @@ if(CONFIG_USERSPACE) # Use the script GEN_KOBJ_LIST to scan the kernel binary's # (${ZEPHYR_LINK_STAGE_EXECUTABLE}) DWARF information to produce a table of kernel # objects (KOBJECT_HASH_LIST) which we will then pass to gperf - add_custom_command( + gen_kobject_list_gperf( + TARGET kobj_hash_list OUTPUT ${KOBJECT_HASH_LIST} - COMMAND - ${PYTHON_EXECUTABLE} - ${GEN_KOBJ_LIST} - --kernel $ - --gperf-output ${KOBJECT_HASH_LIST} - ${gen_kobject_list_include_args} - $<$:--verbose> - DEPENDS - ${ZEPHYR_LINK_STAGE_EXECUTABLE} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + KERNEL_TARGET ${ZEPHYR_LINK_STAGE_EXECUTABLE} + INCLUDES ${struct_tags_json} + DEPENDS ${struct_tags_json} ) - add_custom_target( - kobj_hash_list - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_HASH_LIST} - ) # Use gperf to generate C code (KOBJECT_HASH_OUTPUT_SRC_PRE) which implements a # perfect hashtable based on KOBJECT_HASH_LIST @@ -1500,9 +1525,9 @@ if(CONFIG_USERSPACE) OBJECT ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_HASH_OUTPUT_SRC} ) - set_source_files_properties(${KOBJECT_HASH_OUTPUT_SRC} - PROPERTIES COMPILE_FLAGS - "${NO_COVERAGE_FLAGS} -fno-function-sections -fno-data-sections") + set_target_properties(kobj_hash_output_lib PROPERTIES + COMPILE_OPTIONS "${KOBJECT_HASH_COMPILE_OPTIONS}" + ) target_compile_definitions(kobj_hash_output_lib PRIVATE $ @@ -1714,13 +1739,8 @@ if(CONFIG_BUILD_OUTPUT_ADJUST_LMA) ) endif() -if(NOT CONFIG_CPP_EXCEPTIONS) - set(eh_frame_section ".eh_frame") -else() - set(eh_frame_section "") -endif() set(remove_sections_argument_list "") -foreach(section .comment COMMON ${eh_frame_section}) +foreach(section .comment COMMON) list(APPEND remove_sections_argument_list $${section}) endforeach() @@ -1801,6 +1821,28 @@ if(CONFIG_BUILD_OUTPUT_BIN AND CONFIG_BUILD_OUTPUT_UF2) set(BYPRODUCT_KERNEL_UF2_NAME "${PROJECT_BINARY_DIR}/${KERNEL_UF2_NAME}" CACHE FILEPATH "Kernel uf2 file" FORCE) endif() +if(CONFIG_BUILD_OUTPUT_MOT) + get_property(elfconvert_formats TARGET bintools PROPERTY elfconvert_formats) + if(srec IN_LIST elfconvert_formats) + list(APPEND + post_build_commands + COMMAND $ + $ + ${GAP_FILL} + $srec + $${OUTPUT_FORMAT} + $${KERNEL_ELF_NAME} + $${KERNEL_MOT_NAME} + $ + ) + list(APPEND + post_build_byproducts + ${KERNEL_MOT_NAME} + ) + set(BYPRODUCT_KERNEL_MOT_NAME "${PROJECT_BINARY_DIR}/${KERNEL_MOT_NAME}" CACHE FILEPATH "Kernel mot file" FORCE) + endif() +endif() + set(KERNEL_META_PATH ${PROJECT_BINARY_DIR}/${KERNEL_META_NAME} CACHE INTERNAL "") if(CONFIG_BUILD_OUTPUT_META) list(APPEND @@ -2220,46 +2262,57 @@ if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING)) endif() # Extension Development Kit (EDK) generation. -set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.tar.xz) +if(CONFIG_LLEXT_EDK) + if(CONFIG_LLEXT_EDK_FORMAT_TAR_XZ) + set(llext_edk_extension "tar.xz") + elseif(CONFIG_LLEXT_EDK_FORMAT_TAR_ZSTD) + set(llext_edk_extension "tar.Z") + elseif(CONFIG_LLEXT_EDK_FORMAT_ZIP) + set(llext_edk_extension "zip") + else() + message(FATAL_ERROR "Unsupported LLEXT_EDK_FORMAT choice") + endif() + set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.${llext_edk_extension}) -# TODO maybe generate flags for C CXX ASM -zephyr_get_compile_definitions_for_lang(C zephyr_defs) -zephyr_get_compile_options_for_lang(C zephyr_flags) + # TODO maybe generate flags for C CXX ASM + zephyr_get_compile_definitions_for_lang(C zephyr_defs) + zephyr_get_compile_options_for_lang(C zephyr_flags) -# Filter out non LLEXT and LLEXT_EDK flags - and add required ones -llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags) -llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags) + # Filter out non LLEXT and LLEXT_EDK flags - and add required ones + llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags) + llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags) -set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD) -list(APPEND llext_edk_cflags ${llext_filt_flags}) -list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS}) -list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS}) + set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD) + list(APPEND llext_edk_cflags ${llext_filt_flags}) + list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS}) + list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS}) -build_info(llext-edk file PATH ${llext_edk_file}) -build_info(llext-edk cflags VALUE ${llext_edk_cflags}) -build_info(llext-edk include-dirs VALUE "$") + build_info(llext-edk file PATH ${llext_edk_file}) + build_info(llext-edk cflags VALUE ${llext_edk_cflags}) + build_info(llext-edk include-dirs VALUE "$") -add_custom_command( + add_custom_command( OUTPUT ${llext_edk_file} # Regenerate syscalls in case CONFIG_LLEXT_EDK_USERSPACE_ONLY COMMAND ${CMAKE_COMMAND} - -E make_directory edk/include/generated/zephyr + -E make_directory edk/include/generated/zephyr COMMAND - ${PYTHON_EXECUTABLE} - ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py - --json-file ${syscalls_json} # Read this file - --base-output edk/include/generated/zephyr/syscalls # Write to this dir - --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file - --syscall-list ${edk_syscall_list_h} - $<$:--userspace-only> - ${SYSCALL_LONG_REGISTERS_ARG} - ${SYSCALL_SPLIT_TIMEOUT_ARG} + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py + --json-file ${syscalls_json} # Read this file + --base-output edk/include/generated/zephyr/syscalls # Write to this dir + --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file + --syscall-list ${edk_syscall_list_h} + $<$:--userspace-only> + ${SYSCALL_LONG_REGISTERS_ARG} + ${SYSCALL_SPLIT_TIMEOUT_ARG} COMMAND ${CMAKE_COMMAND} -P ${ZEPHYR_BASE}/cmake/llext-edk.cmake - DEPENDS ${logical_target_for_zephyr_elf} build_info_yaml_saved + DEPENDS ${logical_target_for_zephyr_elf} ${syscalls_json} build_info_yaml_saved COMMAND_EXPAND_LISTS -) -add_custom_target(llext-edk DEPENDS ${llext_edk_file}) + ) + add_custom_target(llext-edk DEPENDS ${llext_edk_file}) +endif() # @Intent: Set compiler specific flags for standard C/C++ includes # Done at the very end, so any other system includes which may diff --git a/CODEOWNERS b/CODEOWNERS new file mode 100644 index 000000000000..54110c3f9a54 --- /dev/null +++ b/CODEOWNERS @@ -0,0 +1,4 @@ +# Instead of the CODEOWNERS file, The Zephyr Project uses a custom format. +# See MAINTAINERS.yml for details. +# +# DO NOT EDIT THIS FILE. diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 2d8031260ced..070b4231eee8 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -215,12 +215,6 @@ config LINKER_SORT_BY_ALIGNMENT in decreasing size of symbols. This helps to minimize padding between symbols. -config SRAM_VECTOR_TABLE - bool "Place the vector table in SRAM instead of flash" - help - The option specifies that the vector table should be placed at the - start of SRAM instead of the start of flash. - config HAS_SRAM_OFFSET bool help @@ -548,9 +542,18 @@ config LTO config COMPILER_WARNINGS_AS_ERRORS bool "Treat warnings as errors" + depends on !DEPRECATION_TEST help Turn on "warning as error" toolchain flags +config DEPRECATION_TEST + bool "Indicate test for deprecated feature" + help + This option is selected by tests which check functionality of + deprecated features. It ensures that COMPILER_WARNINGS_AS_ERRORS + is not selected as that would generate errors when the deprecated + features are used. + config COMPILER_SAVE_TEMPS bool "Save temporary object files" help @@ -621,6 +624,13 @@ config MISRA_SANE standard for safety reasons. Specifically variable length arrays are not permitted (and gcc will enforce this). +config TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS + bool + default y + help + Hidden symbol to state if the toolchain can handle vla in + statements. + endmenu choice @@ -784,6 +794,12 @@ config BUILD_OUTPUT_UF2 Build a UF2 binary zephyr/zephyr.uf2 in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. +config BUILD_OUTPUT_MOT + bool "Build a binary in MOT format" + help + Build a MOT binary zephyr/zephyr.mot in the build directory. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + if BUILD_OUTPUT_UF2 config BUILD_OUTPUT_UF2_FAMILY_ID diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 251006cbafb4..3e7c3048b538 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -126,6 +126,19 @@ ACPI: tests: - acpi +Aesc Platform: + status: maintained + maintainers: + - dnltz + files: + - soc/aesc/ + - dts/riscv/aesc/ + - boards/aesc/ + files-regex: + - ^drivers/.*aesc(\.c)?$ + labels: + - "area: Aesc Silicon Platform" + Antmicro platforms: status: maintained maintainers: @@ -170,6 +183,7 @@ Arduino Platforms: - facchinm files: - boards/arduino/ + - drivers/*/*modulino* ARM arch: status: maintained @@ -182,6 +196,7 @@ ARM arch: - MaureenHelm - stephanosio - bbolen + - ithinuel files: - arch/arm/ - arch/arm/core/offsets/ @@ -202,6 +217,9 @@ ARM64 arch: - npitre - povergoing - sgrrzhf + - wearyzen + - ithinuel + - JiafeiPan files: - arch/arm64/ - include/zephyr/arch/arm64/ @@ -218,6 +236,8 @@ ARM Platforms: status: maintained maintainers: - wearyzen + collaborators: + - ithinuel files: - boards/arm/mps*/ - boards/arm/v2m_*/ @@ -285,6 +305,21 @@ Ambiq Platforms: labels: - "platform: Ambiq" +AndesTech Platforms: + status: maintained + maintainers: + - jimmyzhe + collaborators: + - kevinwang821020 + files: + - boards/andestech/ + - drivers/*/*andes* + - dts/bindings/*/*andestech* + - dts/riscv/andes/ + - soc/andestech/ + labels: + - "platform: Andes Technology" + BeagleBoard Platforms: status: maintained maintainers: @@ -293,6 +328,7 @@ BeagleBoard Platforms: - ayush1325 - con-pax - vaishnavachath + - glneo files: - boards/beagle/ labels: @@ -358,9 +394,9 @@ Bluetooth Controller: - carlescufi - thoh-ot - ppryga - - mtpr-ot - wopu-ot - erbr-ot + - Tronil files: - doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst - doc/connectivity/bluetooth/img/ctlr* @@ -432,6 +468,7 @@ Bluetooth Host: - subsys/bluetooth/host/iso_internal.h - subsys/bluetooth/host/shell/iso.c - tests/bluetooth/audio/ + - tests/bluetooth/classic/ - tests/bluetooth/controller/ - tests/bluetooth/mesh*/ - tests/bluetooth/qualification/ @@ -499,6 +536,7 @@ Bluetooth Audio: - tests/bsim/bluetooth/audio_samples/ - tests/bluetooth/shell/audio.conf - tests/bluetooth/tester/overlay-le-audio.conf + - tests/bluetooth/tester/overlay-bt_ll_sw_split.conf - tests/bluetooth/tester/src/audio/ - doc/connectivity/bluetooth/api/audio/ - doc/connectivity/bluetooth/shell/audio/ @@ -520,11 +558,15 @@ Bluetooth Classic: - lylezhu2012 collaborators: - jhedberg + - MarkWangChinese + - gzh-terry + - makeshi files: - doc/connectivity/bluetooth/shell/classic/a2dp.rst - subsys/bluetooth/common/ - subsys/bluetooth/host/classic/ - include/zephyr/bluetooth/classic/ + - tests/bluetooth/classic/ labels: - "area: Bluetooth Classic" - "area: Bluetooth" @@ -826,22 +868,15 @@ Debug: - scripts/coredump/ - samples/subsys/debug/ - doc/services/debugging/ - labels: - - "area: Debugging" - tests: - - debug - -"Debug: Profiling: Perf": - status: odd fixes - files: - doc/services/profiling/perf.rst - samples/subsys/profiling/perf/ - scripts/profiling/stackcollapse.py - subsys/profiling/perf/ labels: - - "area: Profiling / Perf" + - "area: Debugging" tests: - - debug.profiling.perf + - debug + "Debug: Symtab": status: maintained @@ -874,7 +909,6 @@ Demand Paging: Device Driver Model: status: maintained maintainers: - - gmarull - tbursztyka collaborators: - dcpleung @@ -929,8 +963,6 @@ Devicetree: - include/zephyr/dt-bindings/dt-util.h - dts/binding-template.yaml - dts/bindings/base/ - files-exclude: - - dts/common/nordic/ labels: - "area: Devicetree" tests: @@ -966,6 +998,8 @@ Display drivers: collaborators: - jfischer-no - danieldegrasse + - VynDragon + - jarmouniA files: - drivers/display/ - dts/bindings/display/ @@ -1021,9 +1055,9 @@ Documentation: Documentation Infrastructure: status: maintained maintainers: - - gmarull - kartben collaborators: + - gmarull - carlescufi - nashif files: @@ -1038,8 +1072,8 @@ Documentation Infrastructure: Release Notes: status: maintained maintainers: - - fabiobaltieri - - kartben + - danieldegrasse + - dkalowsk collaborators: - kartben files: @@ -1408,12 +1442,14 @@ Release Notes: - drivers.espi "Drivers: Ethernet": - status: odd fixes + status: maintained + maintainers: + - maass-hamburg collaborators: - decsny - lmajewski - pdgendt - - maass-hamburg + - clamattia files: - drivers/ethernet/ - include/zephyr/dt-bindings/ethernet/ @@ -1642,6 +1678,9 @@ Release Notes: status: maintained maintainers: - carlocaione + collaborators: + - wearyzen + - ithinuel files: - include/zephyr/drivers/mbox.h - drivers/mbox/ @@ -1668,10 +1707,11 @@ Release Notes: - drivers.memc "Drivers: MDIO": - status: odd fixes + status: maintained + maintainers: + - maass-hamburg collaborators: - decsny - - maass-hamburg files: - doc/hardware/peripherals/mdio.rst - drivers/mdio/ @@ -1731,6 +1771,10 @@ Release Notes: "Interrupt Handling": status: odd fixes + collaborators: + - ycsin + - dcpleung + - nashif files: - drivers/interrupt_controller/ - dts/bindings/interrupt-controller/ @@ -1764,24 +1808,6 @@ Release Notes: tests: - drivers.ipm -"Drivers: kscan": - status: maintained - maintainers: - - albertofloyd - collaborators: - - VenkatKotakonda - files: - - drivers/kscan/ - - include/zephyr/drivers/kscan.h - - samples/drivers/kscan/ - - tests/drivers/kscan/ - - dts/bindings/kscan/ - - doc/hardware/peripherals/kscan.rst - labels: - - "area: Kscan" - tests: - - drivers.kscan - "Drivers: LED": status: maintained maintainers: @@ -1823,8 +1849,9 @@ Release Notes: "Drivers: MFD": status: odd fixes collaborators: - - gmarull - aasinclair + - nordic-auko + - seov-nordic files: - drivers/mfd/ - include/zephyr/drivers/mfd/ @@ -1852,7 +1879,8 @@ Release Notes: "Drivers: Regulators": status: maintained maintainers: - - gmarull + - nordic-auko + - seov-nordic collaborators: - danieldegrasse - aasinclair @@ -1934,8 +1962,8 @@ Release Notes: - samples.drivers.peci "Drivers: Pin Control": - status: maintained - maintainers: + status: odd fixes + collaborators: - gmarull files: - doc/hardware/pinctrl/ @@ -1966,7 +1994,7 @@ Release Notes: "Drivers: PTP Clock": status: maintained maintainers: - - tbursztyka + - yangbolu1991 files: - drivers/ptp_clock/ - include/zephyr/drivers/ptp_clock.h @@ -2071,7 +2099,7 @@ Release Notes: labels: - "area: Sensors" tests: - - drivers.sensors + - drivers.sensor "Drivers: SMBus": status: maintained @@ -2116,12 +2144,16 @@ Release Notes: - dipakgmx - fabiobaltieri - faxe1008 + - jbehrensnx files: - drivers/stepper/ + - include/zephyr/drivers/stepper/ - include/zephyr/drivers/stepper.h - dts/bindings/stepper/ - doc/hardware/peripherals/stepper.rst + - samples/drivers/stepper/ - tests/drivers/build_all/stepper/ + - tests/drivers/stepper/ labels: - "area: Stepper" tests: @@ -2142,11 +2174,13 @@ Release Notes: - "area: Timer" "Drivers: Video": - status: odd fixes - collaborators: - - loicpoulain + status: maintained + maintainers: - josuah - ngphibang + collaborators: + - loicpoulain + - avolmat-st files: - drivers/video/ - include/zephyr/drivers/video.h @@ -2160,6 +2194,20 @@ Release Notes: tests: - drivers.video +"Drivers: VIRTIO": + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - drivers/virtio/ + - dts/bindings/virtio/ + - include/zephyr/virtio/ + labels: + - "area: VIRTIO" + "Drivers: W1": status: maintained maintainers: @@ -2276,9 +2324,7 @@ Release Notes: - "area: Display Controller" "Drivers: Virtualization": - status: maintained - maintainers: - - tbursztyka + status: odd fixes files: - drivers/virtualization/ - tests/drivers/virtualization/ @@ -2307,11 +2353,9 @@ EC Host Commands: Xen Platform: status: maintained maintainers: - - povergoing + - firscity collaborators: - - SgrrZhf - lorc - - firscity - luca-fancellu files: - include/zephyr/xen/ @@ -2392,8 +2436,6 @@ Input: status: maintained maintainers: - fabiobaltieri - collaborators: - - gmarull files: - doc/services/input/ - drivers/input/ @@ -2751,6 +2793,21 @@ Modem: tests: - modem +NEORV32 platform: + status: maintained + maintainers: + - henrikbrixandersen + files: + - boards/others/neorv32/ + - drivers/*/*neorv32* + - dts/bindings/*/*neorv32* + - soc/neorv32/ + - tests/boards/neorv32/ + labels: + - "platform: NEORV32" + tests: + - boards.neorv32 + OSDP: status: maintained maintainers: @@ -2796,7 +2853,7 @@ hawkBit: tests: - sample.net.updatehub -Native POSIX/Sim and POSIX arch: +Native_sim and POSIX arch: status: maintained maintainers: - aescolar @@ -2819,7 +2876,7 @@ Native POSIX/Sim and POSIX arch: labels: - "area: native port" description: >- - POSIX architecture and SOC, native_posix & native_sim boards, and related drivers + POSIX architecture and SOC, native_sim boards, and related drivers tests: - boards.native_sim @@ -2830,7 +2887,6 @@ Networking: - jukkar collaborators: - pdgendt - - tbursztyka - ssharks files: - scripts/net/ @@ -2851,7 +2907,6 @@ Networking: - include/zephyr/net/ieee802154*.h - include/zephyr/net/ptp.h - include/zephyr/net/wifi*.h - - include/zephyr/net/buf.h - include/zephyr/net/dhcpv4*.h - include/zephyr/net/http/ - samples/net/gptp/ @@ -2900,11 +2955,9 @@ Networking: - jhedberg collaborators: - rlubos - - tbursztyka - jukkar files: - doc/services/net_buf/ - - include/zephyr/net/buf.h - include/zephyr/net_buf.h - lib/net_buf/ - tests/lib/net_buf/ @@ -3113,25 +3166,6 @@ Networking: tests: - net.http -NIOS-2 arch: - status: maintained - maintainers: - - nashif - files: - - arch/nios2/ - - dts/nios2/intel/ - - boards/common/nios2.board.cmake - - soc/altr/*nios2*/ - - include/zephyr/arch/nios2/ - - tests/boards/altera_max10/ - - boards/qemu/nios2/ - - boards/altr/max10/ - - scripts/support/quartus-flash.py - labels: - - "area: NIOS2" - tests: - - boards.altera_max10 - nRF BSIM: status: maintained maintainers: @@ -3179,6 +3213,20 @@ PHYTEC Platforms: labels: - "platform: PHYTEC" +PMCI: + status: maintained + maintainers: + - teburd + collaborators: + - nashif + - inteljiangwe1 + - kehintel + files: + - subsys/pmci/ + - samples/modules/pmci/ + labels: + - "area: PMCI" + POSIX API layer: status: maintained maintainers: @@ -3243,6 +3291,7 @@ RISCV arch: - carlocaione - npitre - ycsin + - VynDragon files: - arch/riscv/ - boards/enjoydigital/litex_vexriscv/ @@ -3352,7 +3401,7 @@ Settings: - subsys/settings/ - tests/subsys/settings/ - samples/subsys/settings/ - - doc/services/settings/ + - doc/services/storage/settings/ labels: - "area: Settings" tests: @@ -3445,26 +3494,44 @@ ADI Platforms: - microbuilder files: - boards/adi/ + - boards/shields/eval*ardz/ - boards/shields/pmod_acl/ - drivers/*/*max* - drivers/*/*max*/ - drivers/dac/dac_ltc* - drivers/ethernet/eth_adin* + - drivers/ethernet/phy/phy_adin* - drivers/mdio/mdio_adin* - - drivers/regulator/regulator_adp5360* - drivers/sensor/adi/ + - drivers/stepper/adi_tmc/ - dts/arm/adi/ - dts/bindings/*/adi,* - dts/bindings/*/lltc,* - dts/bindings/*/maxim,* - soc/adi/ + files-regex: + - ^drivers/(adc|dac|gpio|mfd|regulator)/.*adp?\d+ labels: - "platform: ADI" +Bouffalolab Platforms: + status: maintained + maintainers: + - nandojve + - VynDragon + files: + - boards/bflb/ + - drivers/*/*bflb* + - dts/riscv/bflb/ + - dts/bindings/*/bflb,* + - soc/bflb/ + labels: + - "platform: bouffalolab" + Broadcom Platforms: status: odd fixes files: - - dts/arm/broadcom/ + - dts/*/broadcom/ - soc/brcm/ - boards/brcm/ @@ -3473,7 +3540,6 @@ GD32 Platforms: maintainers: - nandojve collaborators: - - gmarull - soburi - cameled files: @@ -3573,9 +3639,15 @@ Raspberry Pi Pico Platforms: - threeeights - ajf58 files: - - boards/raspberrypi/ + - boards/raspberrypi/rpi_pico*/ - boards/adafruit/kb2040/ + - boards/adafruit/macropad_rp2040/ + - boards/adafruit/qt_py_rp2040/ + - boards/pimoroni/pico_plus2/ + - boards/seeed/xiao_rp2040/ - boards/sparkfun/pro_micro_rp2040/ + - boards/waveshare/rp2040_zero/ + - boards/wiznet/w5500_evb_pico*/ - dts/arm/raspberrypi/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico @@ -3599,8 +3671,11 @@ Silabs Platforms: - dts/arm/silabs/ - dts/bindings/*/silabs* - drivers/*/*gecko* - - drivers/bluetooth/hci/hci_silabs_* - drivers/*/*silabs* + - drivers/*/*siwx91x* + - drivers/*/*/*silabs* + - drivers/*/*/*siwx91x* + - tests/boards/silabs/ labels: - "platform: Silabs" @@ -3721,7 +3796,7 @@ Intel Platforms (Agilex): labels: - "platform: Intel SoC FPGA Agilex" -NXP Drivers: +NXP Platform Drivers: status: maintained maintainers: - dleach02 @@ -3762,21 +3837,23 @@ NXP Drivers: - "platform: NXP Drivers" description: NXP Drivers -NXP Wireless: +NXP Platform Wireless: status: maintained maintainers: - dleach02 collaborators: - MaochenWang1 - axelnxp + - George-Stefan files: - drivers/wifi/nxp/ - drivers/bluetooth/hci/*nxp* - drivers/ieee802154/ieee802154_kw41z.c + - drivers/*/*mcxw*.c labels: - "platform: NXP Drivers" -NXP MCUX USB: +NXP Platform MCUX USB: status: maintained maintainers: - mmahadevan108 @@ -3829,6 +3906,7 @@ NXP Platforms (S32): - manuargue collaborators: - Dat-NguyenDuy + - congnguyenhuu files: - boards/nxp/*s32*/ - boards/common/*nxp_s32* @@ -3841,6 +3919,8 @@ NXP Platforms (S32): - include/zephyr/dt-bindings/*/nxp-s32* - include/zephyr/dt-bindings/*/nxp_s32* - include/zephyr/drivers/*/*nxp_s32* + files-exclude: + - boards/nxp/ucans32k1sic/ labels: - "platform: NXP S32" description: NXP S32 platforms and S32-specific drivers @@ -3853,6 +3933,8 @@ NXP Platforms (MPU): - dleach02 - dbaluta - iuliana-prodan + - yangbolu1991 + - Zhiqiang-Hou files: - dts/arm64/nxp/ - dts/arm/nxp/nxp_imx* @@ -3883,12 +3965,15 @@ NXP Platforms (Robotics Products): maintainers: - bperseghetti - PetervdPerk-NXP + collaborators: + - manuargue files: - boards/nxp/vmu*/ - boards/nxp/rddrone_fmuk66/ - boards/nxp/mr_canhubk3/ + - boards/nxp/ucans32k1sic/ labels: - - "platform: NXP" + - "platform: NXP Robotics" description: NXP Robotics Module Platform Products Microchip MEC Platforms: @@ -3955,16 +4040,35 @@ nRF Platforms: files: - boards/nordic/ - drivers/*/*nrf*.c + - drivers/*/*nrf*/ - drivers/*/*nordic*/ - soc/nordic/ - samples/boards/nordic/ - dts/*/nordic/ - dts/bindings/*/nordic,* + - include/zephyr/drivers/*/*nrf*.h + - include/zephyr/drivers/*/*nrf*/ + - include/zephyr/dt-bindings/*/nordic*.h + - include/zephyr/dt-bindings/*/nrf*.h - tests/drivers/*/*nrf*/ - snippets/nordic*/ + - tests/boards/nrf/ labels: - "platform: nRF" +Octavo Systems Platforms: + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - boards/oct/ + - soc/oct/ + labels: + - "platform: Octavo Systems" + OpenTitan Platforms: status: maintained maintainers: @@ -4022,6 +4126,7 @@ Renesas RA Platforms: collaborators: - duynguyenxa - thaoluonguw + - thenguyenyf files: - boards/arduino/uno_r4/ - boards/renesas/*ra*/ @@ -4030,6 +4135,7 @@ Renesas RA Platforms: - dts/arm/renesas/ra/ - dts/bindings/*/*renesas,ra* - soc/renesas/ra/ + - samples/boards/renesas/ labels: - "platform: Renesas RA" description: >- @@ -4040,8 +4146,8 @@ Renesas RZ Platforms: status: maintained maintainers: - tgorochowik - collaborators: - binhnguyen2434 + collaborators: - nhutnguyenkc files: - boards/renesas/rz*/ @@ -4051,7 +4157,6 @@ Renesas RZ Platforms: - dts/arm/renesas/rz/ - dts/bindings/*/*rzt2m* - dts/bindings/*/*renesas,rz* - - soc/renesas/rzt2m/ - soc/renesas/rz/ labels: - "platforms: Renesas RZ" @@ -4093,6 +4198,7 @@ STM32 Platforms: - marwaiehm-st - mathieuchopstm - djiatsaf-st + - etienne-lms files: - boards/st/ - drivers/*/*stm32*.c @@ -4160,8 +4266,7 @@ Espressif Platforms: - drivers/*/*esp32*.c - boards/espressif/ - soc/espressif/ - - dts/xtensa/espressif/ - - dts/riscv/espressif/ + - dts/*/espressif/ - dts/bindings/*/*esp32* - samples/boards/espressif/ - tests/boards/espressif/ @@ -4191,6 +4296,20 @@ ITE Platforms: labels: - "platform: ITE" +TI MSPM0 Platforms: + status: maintained + maintainers: + - ssekar15 + files: + - soc/ti/mspm0/ + - boards/ti/lp_mspm0g3507/ + - dts/arm/ti/mspm0/ + - dts/bindings/*/*mspm0* + - drivers/*/*_mspm0* + - modules/Kconfig.mspm0 + labels: + - "platform: Texas Instruments MSPM0" + TI SimpleLink Platforms: status: maintained maintainers: @@ -4204,7 +4323,7 @@ TI SimpleLink Platforms: - drivers/*/*cc25* - drivers/*/*cc26* - drivers/*/*cc32* - - dts/arm/ti/ + - dts/arm/ti/cc* - dts/bindings/*/ti,* - soc/ti/simplelink/ - dts/bindings/*/ti,* @@ -4219,11 +4338,14 @@ TI K3 Platforms: collaborators: - gramsay0 - dnltz + - glneo files: - boards/ti/*am62*/ - drivers/*/*davinci* - drivers/*/*omap* - drivers/*/*ti_k3* + - dts/arm/ti/am6* + - dts/arm/ti/j7* - dts/bindings/*/ti,k3* - soc/ti/k3/ labels: @@ -4332,14 +4454,26 @@ Secure storage: - tomi-font files: - subsys/secure_storage/ + - include/zephyr/psa/ - samples/psa/ - - doc/services/secure_storage.rst + - doc/services/storage/secure_storage/index.rst - tests/subsys/secure_storage/ labels: - "area: Secure storage" tests: - psa.secure_storage +Sensry Platforms: + status: maintained + maintainers: + - tswaehn + files: + - boards/sensry/ + files-regex: + - .*sy1xx.* + labels: + - "platform: sensry" + Storage: status: odd fixes files: @@ -4407,8 +4541,13 @@ Task Watchdog: TDK Sensors: status: maintained maintainers: + - afontaine-invn + - rbuisson-invn + collaborators: - teburd - MaureenHelm + - sriccardi-invn + - gjabouley-invn files: - drivers/sensor/tdk/ labels: @@ -4471,6 +4610,21 @@ TDK Sensors: labels: - "area: Toolchains" +"Toolchain IAR": + status: maintained + maintainers: + - RobinKastberg + collaborators: + - bjorniuppsala + - LoveKarlsson + files: + - cmake/*/iar/ + - include/zephyr/toolchain/iar.h + - include/zephyr/toolchain/iar/* + - lib/libc/iar/* + labels: + - "area: Toolchains" + "Toolchain oneApi": status: maintained maintainers: @@ -4772,6 +4926,7 @@ West: - wearyzen collaborators: - tomi-font + - ithinuel files: [] labels: - "area: CMSIS_6" @@ -4808,14 +4963,17 @@ West: labels: - "platform: ADI" -"West project: hal_altera": - status: odd fixes +"West project: hal_afbr": + status: maintained + maintainers: + - ubieda + - bperseghetti collaborators: - - nashif - files: - - modules/Kconfig.altera + - PetervdPerk-NXP + - jgoppert + files: [] labels: - - "platform: Altera" + - "platform: Broadcom" "West project: hal_ambiq": status: odd fixes @@ -4839,6 +4997,16 @@ West: labels: - "platform: Microchip SAM" +"West project: hal_bouffalolab": + status: maintained + maintainers: + - nandojve + - VynDragon + files: + - modules/hal_bouffalolab/ + labels: + - "platform: Bouffalo Lab" + "West project: hal_cypress": status: maintained maintainers: @@ -4868,6 +5036,8 @@ West: maintainers: - kristofer-jonsson-arm - wearyzen + collaborators: + - ithinuel files: - drivers/misc/ethos_u/ - modules/hal_ethos_u/ @@ -4879,7 +5049,6 @@ West: maintainers: - nandojve collaborators: - - gmarull - soburi files: - modules/hal_gigadevice/ @@ -4946,9 +5115,6 @@ West: - bperseghetti files: - modules/hal_nxp/ - - modules/Kconfig.imx - - modules/Kconfig.mcux - - modules/Kconfig.nxp_s32 labels: - "platform: NXP" @@ -5073,6 +5239,8 @@ West: maintainers: - nzmichaelh - kholia + collaborators: + - VynDragon files: - modules/hal_wch/ @@ -5122,8 +5290,7 @@ West: collaborators: - nashif - inteljiangwe1 - files: - - samples/modules/mctp/ + files: [] labels: - "area: MCTP" @@ -5200,6 +5367,7 @@ West: - wearyzen - valeriosetti - tomi-font + - ithinuel files: - modules/mbedtls/ - tests/crypto/mbedtls/ @@ -5351,7 +5519,9 @@ West: - "area: Audio" "West project: tflite-micro": - status: odd fixes + status: maintained + maintainers: + - XenuIsWatching collaborators: - laurenmurphyx64 files: @@ -5390,6 +5560,7 @@ West: - wearyzen - valeriosetti - tomi-font + - ithinuel files: - modules/trusted-firmware-m/ - samples/tfm_integration/ @@ -5407,6 +5578,7 @@ West: collaborators: - Vge0rge - wearyzen + - ithinuel files: [] labels: - "area: TF-M" @@ -5419,6 +5591,7 @@ West: collaborators: - carlocaione - wearyzen + - ithinuel files: - modules/trusted-firmware-a/ labels: @@ -5431,6 +5604,7 @@ West: collaborators: - Vge0rge - wearyzen + - ithinuel files: [] labels: - "area: TF-M" @@ -5528,6 +5702,7 @@ Continuous Integration: - kartben files: - .github/ + - scripts/requirements-actions.* - scripts/ci/ - scripts/make_bugs_pickle.py - .checkpatch.conf @@ -5602,6 +5777,22 @@ Peregrine Platforms: labels: - "platform: Peregrine" +WCH Platforms: + status: maintained + maintainers: + - nzmichaelh + - kholia + collaborators: + - VynDragon + files: + - boards/wch/ + - dts/riscv/wch/ + - soc/wch/ + - drivers/*/*wch* + - dts/bindings/*/wch,* + labels: + - "platform: WinChipHead" + # This area is to be converted to a subarea Testing with Renode: status: odd fixes @@ -5612,8 +5803,8 @@ Testing with Renode: - cmake/emu/renode.cmake - soc/renode/ - boards/renode/ - - boards/**/*/support/*.repl - - boards/**/*/support/*.resc + - boards/*/*/support/*.repl + - boards/*/*/support/*.resc labels: - "area: Renode" @@ -5651,3 +5842,19 @@ zbus: - "area: llext" tests: - llext + +RX arch: + status: maintained + maintainers: + - duynguyenxa + files: + - arch/rx/ + - include/zephyr/arch/rx/ + - dts/rx/ + - boards/qemu/rx/ + - soc/renesas/rx/ + - tests/arch/rx/ + labels: + - "area: RX" + tests: + - arch.rx diff --git a/README.rst b/README.rst index 9472db6d5ee7..a82f73b6fb0a 100644 --- a/README.rst +++ b/README.rst @@ -24,7 +24,7 @@ resource-constrained systems: from simple embedded environmental sensors and LED wearables to sophisticated smart watches and IoT wireless gateways. The Zephyr kernel supports multiple architectures, including ARM (Cortex-A, -Cortex-R, Cortex-M), Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, +Cortex-R, Cortex-M), Intel x86, ARC, Tensilica Xtensa, and RISC-V, SPARC, MIPS, and a large number of `supported boards`_. .. below included in doc/introduction/introduction.rst diff --git a/SDK_VERSION b/SDK_VERSION index c5523bd09b18..7cca7711a0dd 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.17.0 +0.17.1 diff --git a/VERSION b/VERSION index b170abf44be1..9749142466ba 100644 --- a/VERSION +++ b/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 4 -VERSION_MINOR = 0 +VERSION_MINOR = 1 PATCHLEVEL = 99 VERSION_TWEAK = 0 EXTRAVERSION = diff --git a/arch/Kconfig b/arch/Kconfig index 94e9a540a08e..646b83c9d653 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -8,7 +8,7 @@ # Include these first so that any properties (e.g. defaults) below can be # overridden (by defining symbols in multiple locations) -source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)" +source "$(KCONFIG_BINARY_DIR)/arch/Kconfig" # ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2. osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch" @@ -33,6 +33,7 @@ config ARM select ARCH_IS_SET select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M select ARCH_SUPPORTS_COREDUMP_THREADS if CPU_CORTEX_M + select ARCH_SUPPORTS_COREDUMP_STACK_PTR if CPU_CORTEX_M # FIXME: current state of the code for all ARM requires this, but # is really only necessary for Cortex-M with ARM MPU! select GEN_PRIV_STACKS @@ -103,15 +104,6 @@ config X86 help x86 architecture -config NIOS2 - bool - select ARCH_IS_SET - select ATOMIC_OPERATIONS_C - imply XIP - select ARCH_HAS_TIMING_FUNCTIONS - help - Nios II Gen 2 architecture - config RISCV bool select ARCH_IS_SET @@ -166,6 +158,15 @@ config ARCH_POSIX help POSIX (native) architecture +config RX + bool + select ARCH_IS_SET + select ATOMIC_OPERATIONS_C + select USE_SWITCH + select USE_SWITCH_SUPPORTED + help + Renesas RX architecture + config ARCH_IS_SET bool help @@ -227,7 +228,7 @@ config SRAM_BASE_ADDRESS /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. -if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV +if ARC || ARM || ARM64 || X86 || RISCV || RX # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_FLASH := zephyr,flash @@ -250,7 +251,7 @@ config FLASH_BASE_ADDRESS normally set by the board's defconfig file and the user should generally avoid modifying it via the menu configuration. -endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV +endif # ARM || ARM64 || ARC || X86 || RISCV || RX if ARCH_HAS_TRUSTED_EXECUTION @@ -317,7 +318,7 @@ config PRIVILEGED_STACK_SIZE int "Size of privileged stack" default 2048 if EMUL default 1024 - depends on ARCH_HAS_USERSPACE + depends on USERSPACE help This option sets the privileged stack region size that will be used in addition to the user mode thread stack. During normal execution, @@ -327,18 +328,19 @@ config PRIVILEGED_STACK_SIZE config KOBJECT_TEXT_AREA int "Size of kobject text area" + default 1024 if UBSAN default 512 if COVERAGE_GCOV default 512 if NO_OPTIMIZATIONS default 512 if STACK_CANARIES && RISCV default 256 - depends on ARCH_HAS_USERSPACE + depends on USERSPACE help Size of kernel object text area. Used in linker script. config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT int "Reserve extra kobject data area (in percentage)" default 100 - depends on ARCH_HAS_USERSPACE + depends on USERSPACE help Multiplication factor used to calculate the size of placeholder to reserve space for kobject metadata hash table. The hash table is @@ -352,7 +354,7 @@ config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT config KOBJECT_RODATA_AREA_EXTRA_BYTES int "Reserve extra bytes for kobject rodata area" default 16 - depends on ARCH_HAS_USERSPACE + depends on USERSPACE help Reserve a few more bytes for the RODATA region for kobject metadata. This is to account for the uncertainty of tables generated by gperf. @@ -513,6 +515,12 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN to be aligned to architecture specific size. The default size is 0 for no alignment. +config ARCH_DEVICE_STATE_ALIGN + int "Alignment size of device state" + default 4 + help + This option controls alignment size of device state. + choice IRQ_VECTOR_TABLE_TYPE prompt "IRQ vector table type" depends on GEN_IRQ_VECTOR_TABLE @@ -573,6 +581,15 @@ config IRQ_OFFLOAD run in interrupt context. Only useful for test cases that need to validate the correctness of kernel objects in IRQ context. +config SRAM_VECTOR_TABLE + bool "Place the vector table in SRAM instead of flash" + depends on ARCH_HAS_VECTOR_TABLE_RELOCATION + depends on XIP + depends on !ROMSTART_RELOCATION_ROM + help + When XiP is enabled, this option will result in the vector table being + relocated from Flash to SRAM. + config IRQ_OFFLOAD_NESTED bool "irq_offload() supports nested IRQs" depends on IRQ_OFFLOAD @@ -671,6 +688,9 @@ config ARCH_HAS_NOCACHE_MEMORY_SUPPORT config ARCH_HAS_RAMFUNC_SUPPORT bool +config ARCH_HAS_VECTOR_TABLE_RELOCATION + bool + config ARCH_HAS_NESTED_EXCEPTION_DETECTION bool @@ -683,6 +703,9 @@ config ARCH_SUPPORTS_COREDUMP_THREADS config ARCH_SUPPORTS_COREDUMP_PRIV_STACKS bool +config ARCH_SUPPORTS_COREDUMP_STACK_PTR + bool + config ARCH_SUPPORTS_ARCH_HW_INIT bool @@ -1134,9 +1157,9 @@ config ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE config ARCH_HAS_CUSTOM_SWAP_TO_MAIN bool help - It's possible that an architecture port cannot use _Swap() to swap to - the _main() thread, but instead must do something custom. It must - enable this option in that case. + It's possible that an architecture port cannot use z_swap_unlocked() + to swap to the main thread (bg_thread_main), but instead must do + something custom. It must enable this option in that case. config ARCH_HAS_CUSTOM_BUSY_WAIT bool diff --git a/arch/Kconfig.v1 b/arch/Kconfig.v1 deleted file mode 100644 index d76acba59a3e..000000000000 --- a/arch/Kconfig.v1 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Note: $ARCH might be a glob pattern -source "$(ARCH_DIR)/$(ARCH)/Kconfig" diff --git a/arch/Kconfig.v2 b/arch/Kconfig.v2 deleted file mode 100644 index 19db8d462465..000000000000 --- a/arch/Kconfig.v2 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -source "$(KCONFIG_BINARY_DIR)/arch/Kconfig" diff --git a/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c index 6ba748b34558..f33bd638d770 100644 --- a/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c +++ b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c @@ -8,14 +8,6 @@ __weak void *__dso_handle; -int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso) -{ - ARG_UNUSED(destructor); - ARG_UNUSED(objptr); - ARG_UNUSED(dso); - return 0; -} - int atexit(void (*function)(void)) { return 0; diff --git a/arch/arc/core/elf.c b/arch/arc/core/elf.c index 9f9f1073431a..db2a74e164ef 100644 --- a/arch/arc/core/elf.c +++ b/arch/arc/core/elf.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -31,12 +32,32 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); * https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf * https://github.com/zephyrproject-rtos/binutils-gdb */ -int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name, - uintptr_t load_bias) +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) { int ret = 0; - uint32_t insn = UNALIGNED_GET((uint32_t *)loc); uint32_t value; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + uint32_t insn = UNALIGNED_GET((uint32_t *)loc); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } sym_base_addr += rel->r_addend; diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index bf3ab454a2c4..113ac5029736 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -26,49 +26,6 @@ #include #include -/* XXX - keep for future use in full-featured cache APIs */ -#if 0 -/** - * @brief Disable the i-cache if present - * - * For those ARC CPUs that have a i-cache present, - * invalidate the i-cache and then disable it. - */ - -static void disable_icache(void) -{ - unsigned int val; - - val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD); - val &= 0xff; /* version field */ - if (val == 0) { - return; /* skip if i-cache is not present */ - } - z_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0); - __builtin_arc_nop(); - z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1); -} - -/** - * @brief Invalidate the data cache if present - * - * For those ARC CPUs that have a data cache present, - * invalidate the data cache. - */ - -static void invalidate_dcache(void) -{ - unsigned int val; - - val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD); - val &= 0xff; /* version field */ - if (val == 0) { - return; /* skip if d-cache is not present */ - } - z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1); -} -#endif - #ifdef CONFIG_ISA_ARCV3 /* NOTE: it will be called from early C code - we must NOT use global / static variables in it! */ static void arc_cluster_scm_enable(void) @@ -92,8 +49,8 @@ static void arc_cluster_scm_enable(void) /* Invalidate SCM before enabling. */ arc_cln_write_reg_nolock(ARC_CLN_CACHE_CMD, ARC_CLN_CACHE_CMD_OP_REG_INV | ARC_CLN_CACHE_CMD_INCR); - while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) - ; + while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) { + } arc_cln_write_reg_nolock(ARC_CLN_CACHE_STATUS, ARC_CLN_CACHE_STATUS_EN); } diff --git a/arch/archs.yml b/arch/archs.yml index e07d10ffe80b..352a296dde2a 100644 --- a/arch/archs.yml +++ b/arch/archs.yml @@ -7,8 +7,6 @@ archs: path: arm64 - name: mips path: mips - - name: nios2 - path: nios2 - name: posix path: posix - name: riscv @@ -19,3 +17,5 @@ archs: path: xtensa - name: x86 path: x86 + - name: rx + path: rx diff --git a/arch/arm/core/Kconfig b/arch/arm/core/Kconfig index 2573ca2cac6b..5505eee4e19b 100644 --- a/arch/arm/core/Kconfig +++ b/arch/arm/core/Kconfig @@ -16,6 +16,7 @@ config CPU_CORTEX_M select ARCH_HAS_USERSPACE if ARM_MPU select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE select ARCH_HAS_RAMFUNC_SUPPORT + select ARCH_HAS_VECTOR_TABLE_RELOCATION if CPU_CORTEX_M_HAS_VTOR select ARCH_HAS_NESTED_EXCEPTION_DETECTION select SWAP_NONATOMIC select ARCH_HAS_EXTRA_EXCEPTION_INFO diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 409968ca6c7c..a6176bbe5c09 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -13,6 +13,15 @@ # CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not # exposed if one selects a different ARM Cortex Family (Cortex-M). +config CPU_CORTEX_A7 + bool + select CPU_AARCH32_CORTEX_A + select ARMV7_A + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + help + This option signifies the use of a Cortex-A7 CPU. + config CPU_CORTEX_A9 bool select CPU_AARCH32_CORTEX_A @@ -82,6 +91,8 @@ config CPU_CORTEX_R5 select CPU_AARCH32_CORTEX_R select ARMV7_R select ARMV7_R_FP if CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE help This option signifies the use of a Cortex-R5 CPU diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index 31cf27a08e64..cab76d32f495 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -63,13 +63,13 @@ void arch_dcache_disable(void) { uint32_t val; + L1C_CleanInvalidateDCacheAll(); + val = __get_SCTLR(); val &= ~SCTLR_C_Msk; barrier_dsync_fence_full(); __set_SCTLR(val); barrier_isync_fence_full(); - - arch_dcache_flush_and_invd_all(); } int arch_dcache_flush_all(void) @@ -208,7 +208,13 @@ int arch_icache_flush_range(void *start_addr, size_t size) int arch_icache_invd_range(void *start_addr, size_t size) { - return -ENOTSUP; + /* Cortex A/R do have the ICIMVAU operation to selectively invalidate + * the instruction cache, but not currently supported by CMSIS. + * For now, invalidate the entire cache. + */ + L1C_InvalidateICacheAll(); + + return 0; } int arch_icache_flush_and_invd_range(void *start_addr, size_t size) diff --git a/arch/arm/core/cortex_a_r/exc.S b/arch/arm/core/cortex_a_r/exc.S index 78414fcd0a19..ecf7bab57f09 100644 --- a/arch/arm/core/cortex_a_r/exc.S +++ b/arch/arm/core/cortex_a_r/exc.S @@ -237,6 +237,28 @@ SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_data_abort) b z_arm_exc_exit #else + +GTEXT(z_arm_cortex_ar_exit_exc) +SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc) + + /* Note: + * This function is expected to be *always* called with + * processor mode set to MODE_SYS. + */ + + /* decrement exception depth */ + get_cpu r2 + ldrb r1, [r2, #_cpu_offset_to_exc_depth] + sub r1, r1, #1 + strb r1, [r2, #_cpu_offset_to_exc_depth] + + /* + * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack + * and return to the current thread. + */ + pop {r0-r3, r12, lr} + rfeia sp! + /** * @brief Undefined instruction exception handler * diff --git a/arch/arm/core/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c index daf1d2345ca0..b6916706d6f5 100644 --- a/arch/arm/core/cortex_a_r/fault.c +++ b/arch/arm/core/cortex_a_r/fault.c @@ -100,6 +100,59 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr) reason = K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT; LOG_ERR("Unsupported Exclusive Access Fault @ 0x%08x", addr); break; +#elif defined(CONFIG_ARMV7_A) + case FSR_FS_PERMISSION_FAULT_2ND_LEVEL: + reason = K_ERR_ARM_PERMISSION_FAULT_2ND_LEVEL; + LOG_ERR("2nd Level Permission Fault @ 0x%08x", addr); + break; + case FSR_FS_ACCESS_FLAG_FAULT_1ST_LEVEL: + reason = K_ERR_ARM_ACCESS_FLAG_FAULT_1ST_LEVEL; + LOG_ERR("1st Level Access Flag Fault @ 0x%08x", addr); + break; + case FSR_FS_ACCESS_FLAG_FAULT_2ND_LEVEL: + reason = K_ERR_ARM_ACCESS_FLAG_FAULT_2ND_LEVEL; + LOG_ERR("2nd Level Access Flag Fault @ 0x%08x", addr); + break; + case FSR_FS_CACHE_MAINTENANCE_INSTRUCTION_FAULT: + reason = K_ERR_ARM_CACHE_MAINTENANCE_INSTRUCTION_FAULT; + LOG_ERR("Cache Maintenance Instruction Fault @ 0x%08x", addr); + break; + case FSR_FS_TRANSLATION_FAULT: + reason = K_ERR_ARM_TRANSLATION_FAULT; + LOG_ERR("1st Level Translation Fault @ 0x%08x", addr); + break; + case FSR_FS_TRANSLATION_FAULT_2ND_LEVEL: + reason = K_ERR_ARM_TRANSLATION_FAULT_2ND_LEVEL; + LOG_ERR("2nd Level Translation Fault @ 0x%08x", addr); + break; + case FSR_FS_DOMAIN_FAULT_1ST_LEVEL: + reason = K_ERR_ARM_DOMAIN_FAULT_1ST_LEVEL; + LOG_ERR("1st Level Domain Fault @ 0x%08x", addr); + break; + case FSR_FS_DOMAIN_FAULT_2ND_LEVEL: + reason = K_ERR_ARM_DOMAIN_FAULT_2ND_LEVEL; + LOG_ERR("2nd Level Domain Fault @ 0x%08x", addr); + break; + case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL: + reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL; + LOG_ERR("1st Level Synchronous External Abort Translation Table @ 0x%08x", addr); + break; + case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL: + reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL; + LOG_ERR("2nd Level Synchronous External Abort Translation Table @ 0x%08x", addr); + break; + case FSR_FS_TLB_CONFLICT_ABORT: + reason = K_ERR_ARM_TLB_CONFLICT_ABORT; + LOG_ERR("TLB Conflict Abort @ 0x%08x", addr); + break; + case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL: + reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL; + LOG_ERR("1st Level Synchronous Parity Error Translation Table @ 0x%08x", addr); + break; + case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL: + reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL; + LOG_ERR("2nd Level Synchronous Parity Error Translation Table @ 0x%08x", addr); + break; #else case FSR_FS_BACKGROUND_FAULT: reason = K_ERR_ARM_BACKGROUND_FAULT; diff --git a/arch/arm/core/cortex_a_r/irq_manage.c b/arch/arm/core/cortex_a_r/irq_manage.c index 48c9ede3327b..5303d1d71785 100644 --- a/arch/arm/core/cortex_a_r/irq_manage.c +++ b/arch/arm/core/cortex_a_r/irq_manage.c @@ -33,6 +33,14 @@ extern void z_arm_reserved(void); * Generic Interrupt Controller (GIC) and therefore the architecture interrupt * control functions are mapped to the GIC driver interface. * + * When GIC is used together with other interrupt controller for + * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS + * is enabled), the architecture interrupt control functions are mapped + * to the SoC layer in `include/arch/arm/irq.h`. + * The exported arm interrupt control functions which are wrappers of + * GIC control could be used for SoC to do level 1 irq control to implement SoC + * layer interrupt control functions. + * * When a custom interrupt controller is used (i.e. * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture * interrupt control functions are mapped to the SoC layer in @@ -40,17 +48,17 @@ extern void z_arm_reserved(void); */ #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) -void arch_irq_enable(unsigned int irq) +void arm_irq_enable(unsigned int irq) { arm_gic_irq_enable(irq); } -void arch_irq_disable(unsigned int irq) +void arm_irq_disable(unsigned int irq) { arm_gic_irq_disable(irq); } -int arch_irq_is_enabled(unsigned int irq) +int arm_irq_is_enabled(unsigned int irq) { return arm_gic_irq_is_enabled(irq); } @@ -65,10 +73,11 @@ int arch_irq_is_enabled(unsigned int irq) * priority levels which are reserved: three for various types of exceptions, * and possibly one additional to support zero latency interrupts. */ -void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) { arm_gic_irq_set_priority(irq, prio, flags); } + #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); diff --git a/arch/arm/core/cortex_a_r/reboot.c b/arch/arm/core/cortex_a_r/reboot.c index b5cea619f093..d721baceda23 100644 --- a/arch/arm/core/cortex_a_r/reboot.c +++ b/arch/arm/core/cortex_a_r/reboot.c @@ -28,16 +28,13 @@ static inline void relocate_vector_table(void) #else -#if defined(__GNUC__) /* * GCC can detect if memcpy is passed a NULL argument, however one of * the cases of relocate_vector_table() it is valid to pass NULL, so we * suppress the warning for this case. We need to do this before * string.h is included to get the declaration of memcpy. */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wnonnull" -#endif /* __GNUC__ */ +TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_NONNULL) #include @@ -53,9 +50,7 @@ void __weak relocate_vector_table(void) #endif } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif +TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_NONNULL) #endif /* !CONFIG_AARCH32_ARMV8_R */ diff --git a/arch/arm/core/cortex_a_r/semihost.c b/arch/arm/core/cortex_a_r/semihost.c index ff5e443759ba..1467dbca3a4b 100644 --- a/arch/arm/core/cortex_a_r/semihost.c +++ b/arch/arm/core/cortex_a_r/semihost.c @@ -19,10 +19,10 @@ long semihost_exec(enum semihost_instr instr, void *args) register long ret __asm__ ("r0"); if (IS_ENABLED(CONFIG_ISA_THUMB2)) { - __asm__ __volatile__ ("svc 0xab" + __asm__ volatile ("svc 0xab" : "=r" (ret) : "r" (r0), "r" (r1) : "memory"); } else { - __asm__ __volatile__ ("svc 0x123456" + __asm__ volatile ("svc 0x123456" : "=r" (ret) : "r" (r0), "r" (r1) : "memory"); } return ret; diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index d0e31acb1ed8..170a5943f39b 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S index a41e1ab5942f..04b19f0b046b 100644 --- a/arch/arm/core/cortex_a_r/swap_helper.S +++ b/arch/arm/core/cortex_a_r/swap_helper.S @@ -423,5 +423,9 @@ valid_syscall_id: GTEXT(z_arm_cortex_r_svc) SECTION_FUNC(TEXT, z_arm_cortex_r_svc) + .cfi_sections .debug_frame + .cfi_startproc simple + .cfi_def_cfa 13, 0x0 svc #_SVC_CALL_CONTEXT_SWITCH bx lr + .cfi_endproc diff --git a/arch/arm/core/cortex_a_r/vector_table.S b/arch/arm/core/cortex_a_r/vector_table.S index e74b6a41c8d6..d5d95272548f 100644 --- a/arch/arm/core/cortex_a_r/vector_table.S +++ b/arch/arm/core/cortex_a_r/vector_table.S @@ -35,27 +35,3 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) #else ldr pc,=z_irq_spurious #endif - - -#ifdef CONFIG_USE_SWITCH -GTEXT(z_arm_cortex_ar_exit_exc) -SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc) - - /* Note: - * This function is expected to be *always* called with - * processor mode set to MODE_SYS. - */ - - /* decrement exception depth */ - get_cpu r2 - ldrb r1, [r2, #_cpu_offset_to_exc_depth] - sub r1, r1, #1 - strb r1, [r2, #_cpu_offset_to_exc_depth] - - /* - * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack - * and return to the current thread. - */ - pop {r0-r3, r12, lr} - rfeia sp! -#endif diff --git a/arch/arm/core/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt index 05723811929a..3de8e544bc12 100644 --- a/arch/arm/core/cortex_m/CMakeLists.txt +++ b/arch/arm/core/cortex_m/CMakeLists.txt @@ -2,6 +2,23 @@ zephyr_library() +if(CONFIG_ARMV8_1_M_PACBTI_STANDARD) + zephyr_compile_options(-mbranch-protection=standard) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET) + zephyr_compile_options(-mbranch-protection=pac-ret) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF) + zephyr_compile_options(-mbranch-protection=pac-ret+leaf) +elseif(CONFIG_ARMV8_1_M_PACBTI_BTI) + zephyr_compile_options(-mbranch-protection=bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_BTI) + zephyr_compile_options(-mbranch-protection=pac-ret+bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF_BTI) + zephyr_compile_options(-mbranch-protection=pac-ret+leaf+bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_NONE) + #TODO: Enable this after Zephyr SDK updates to GCC version >=14.2 + # zephyr_compile_options(-mbranch-protection=none) +endif() + zephyr_library_sources( exc_exit.c fault.c @@ -61,3 +78,13 @@ zephyr_linker_sources( vt_pointer_section.ld ) endif() + +if (CONFIG_CPU_CORTEX_M_HAS_VTOR) +zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE + RAM_SECTIONS + # Maybe need to be changed in order to be placed at the beginning of RAM + # (conflict with code relocation script) + SORT_KEY 0 + ram_vector_table.ld +) +endif() diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index c018574429a5..eb54301c30c5 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -1,6 +1,7 @@ # ARM Cortex-M platform configuration options # Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright 2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 # NOTE: We have the specific core implementations first and outside of the @@ -298,6 +299,60 @@ config ARMV8_1_M_PMU This option is enabled when the CPU implements ARMv8-M Performance Monitoring Unit (PMU). +choice ARMV8_1_M_PACBTI + prompt "Pointer Authentication and Branch Target Identification" + default ARMV8_1_M_PACBTI_NONE + depends on ARMV8_1_M_MAINLINE + +config ARMV8_1_M_PACBTI_STANDARD + bool "Standard (PACRET + LEAF + BTI)" + help + This option instructs the compiler to generate code with all branch protection features + enabled at their standard level. + +config ARMV8_1_M_PACBTI_PACRET + bool "PACRET only" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory. + +config ARMV8_1_M_PACBTI_PACRET_LEAF + bool "PACRET + Leaf" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory. + +config ARMV8_1_M_PACBTI_BTI + bool "BTI only" + help + This option enables Branch Target Identification (BTI), which inserts special landing + pad instructions at valid indirect branch targets. This option does not enable Pointer + Authentication (PAC). + +config ARMV8_1_M_PACBTI_PACRET_BTI + bool "PACRET + BTI" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARMV8_1_M_PACBTI_PACRET_LEAF_BTI + bool "PACRET + Leaf + BTI" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARMV8_1_M_PACBTI_NONE + bool "None" + help + This option instructs the compiler to generate code without branch protection or return + address signing + +endchoice + config ARMV8_M_PMU_EVENTCNT int "Number of event counters in the Performance Monitoring Unit" depends on ARMV8_1_M_PMU diff --git a/arch/arm/core/cortex_m/cmse/arm_core_cmse.c b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c index aac96472ecf4..163a9d0cdd20 100644 --- a/arch/arm/core/cortex_m/cmse/arm_core_cmse.c +++ b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c @@ -9,7 +9,7 @@ int arm_cmse_mpu_region_get(uint32_t addr) { - cmse_address_info_t addr_info = cmse_TT((void *)addr); + cmse_address_info_t addr_info = cmse_TT((void *)addr); if (addr_info.flags.mpu_region_valid) { return addr_info.flags.mpu_region; @@ -40,8 +40,7 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv) return arm_cmse_addr_read_write_ok(addr, force_npriv, 1); } -static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, - int force_npriv, int rw) +static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw) { int flags = 0; @@ -74,10 +73,10 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr int arm_cmse_mpu_nonsecure_region_get(uint32_t addr) { - cmse_address_info_t addr_info = cmse_TTA((void *)addr); + cmse_address_info_t addr_info = cmse_TTA((void *)addr); if (addr_info.flags.mpu_region_valid) { - return addr_info.flags.mpu_region; + return addr_info.flags.mpu_region; } return -EINVAL; @@ -85,7 +84,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr) int arm_cmse_sau_region_get(uint32_t addr) { - cmse_address_info_t addr_info = cmse_TT((void *)addr); + cmse_address_info_t addr_info = cmse_TT((void *)addr); if (addr_info.flags.sau_region_valid) { return addr_info.flags.sau_region; @@ -96,7 +95,7 @@ int arm_cmse_sau_region_get(uint32_t addr) int arm_cmse_idau_region_get(uint32_t addr) { - cmse_address_info_t addr_info = cmse_TT((void *)addr); + cmse_address_info_t addr_info = cmse_TT((void *)addr); if (addr_info.flags.idau_region_valid) { return addr_info.flags.idau_region; @@ -107,13 +106,12 @@ int arm_cmse_idau_region_get(uint32_t addr) int arm_cmse_addr_is_secure(uint32_t addr) { - cmse_address_info_t addr_info = cmse_TT((void *)addr); + cmse_address_info_t addr_info = cmse_TT((void *)addr); return addr_info.flags.secure; } -static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, - int force_npriv, int rw) +static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw) { cmse_address_info_t addr_info; if (force_npriv) { @@ -122,8 +120,7 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, addr_info = cmse_TTA((void *)addr); } - return rw ? addr_info.flags.nonsecure_readwrite_ok : - addr_info.flags.nonsecure_read_ok; + return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok; } int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv) @@ -137,7 +134,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv) } static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t size, - int force_npriv, int rw) + int force_npriv, int rw) { int flags = CMSE_NONSECURE; @@ -156,18 +153,14 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s } } -int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, - int force_npriv) +int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv) { - return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, - force_npriv, 0); + return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0); } -int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, - int force_npriv) +int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv) { - return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, - force_npriv, 1); + return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1); } #endif /* CONFIG_ARM_SECURE_FIRMWARE */ diff --git a/arch/arm/core/cortex_m/coredump.c b/arch/arm/core/cortex_m/coredump.c index c688c91d9819..787cfcdf4a75 100644 --- a/arch/arm/core/cortex_m/coredump.c +++ b/arch/arm/core/cortex_m/coredump.c @@ -6,32 +6,33 @@ #include #include +#include -#define ARCH_HDR_VER 2 +#define ARCH_HDR_VER 2 uint32_t z_arm_coredump_fault_sp; struct arm_arch_block { struct { - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r12; - uint32_t lr; - uint32_t pc; - uint32_t xpsr; - uint32_t sp; + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t xpsr; + uint32_t sp; /* callee registers - optionally collected in V2 */ - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; } r; } __packed; @@ -76,12 +77,12 @@ void arch_coredump_info_dump(const struct arch_esf *esf) #if defined(CONFIG_EXTRA_EXCEPTION_INFO) if (esf->extra_info.callee) { - arch_blk.r.r4 = esf->extra_info.callee->v1; - arch_blk.r.r5 = esf->extra_info.callee->v2; - arch_blk.r.r6 = esf->extra_info.callee->v3; - arch_blk.r.r7 = esf->extra_info.callee->v4; - arch_blk.r.r8 = esf->extra_info.callee->v5; - arch_blk.r.r9 = esf->extra_info.callee->v6; + arch_blk.r.r4 = esf->extra_info.callee->v1; + arch_blk.r.r5 = esf->extra_info.callee->v2; + arch_blk.r.r6 = esf->extra_info.callee->v3; + arch_blk.r.r7 = esf->extra_info.callee->v4; + arch_blk.r.r8 = esf->extra_info.callee->v5; + arch_blk.r.r9 = esf->extra_info.callee->v6; arch_blk.r.r10 = esf->extra_info.callee->v7; arch_blk.r.r11 = esf->extra_info.callee->v8; } @@ -96,3 +97,8 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_ARM_CORTEX_M; } + +uintptr_t arch_coredump_stack_ptr_get(const struct k_thread *thread) +{ + return (thread == _current) ? z_arm_coredump_fault_sp : thread->callee_saved.psp; +} diff --git a/arch/arm/core/cortex_m/cpu_idle.c b/arch/arm/core/cortex_m/cpu_idle.c index 5f373a88c9d5..47eff95090a8 100644 --- a/arch/arm/core/cortex_m/cpu_idle.c +++ b/arch/arm/core/cortex_m/cpu_idle.c @@ -30,27 +30,31 @@ void z_arm_cpu_idle_init(void) #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE) #define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE #else -#define ON_EXIT_IDLE_HOOK do {} while (false) +#define ON_EXIT_IDLE_HOOK \ + do { \ + } while (false) #endif #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) -#define SLEEP_IF_ALLOWED(wait_instr) do { \ - /* Skip the wait instr if on_enter_cpu_idle returns false */ \ - if (z_arm_on_enter_cpu_idle()) { \ - /* Wait for all memory transaction to complete */ \ - /* before entering low power state. */ \ - __DSB(); \ - wait_instr(); \ - /* Inline the macro provided by SoC-specific code */ \ - ON_EXIT_IDLE_HOOK; \ - } \ -} while (false) +#define SLEEP_IF_ALLOWED(wait_instr) \ + do { \ + /* Skip the wait instr if on_enter_cpu_idle returns false */ \ + if (z_arm_on_enter_cpu_idle()) { \ + /* Wait for all memory transaction to complete */ \ + /* before entering low power state. */ \ + __DSB(); \ + wait_instr(); \ + /* Inline the macro provided by SoC-specific code */ \ + ON_EXIT_IDLE_HOOK; \ + } \ + } while (false) #else -#define SLEEP_IF_ALLOWED(wait_instr) do { \ - __DSB(); \ - wait_instr(); \ - ON_EXIT_IDLE_HOOK; \ -} while (false) +#define SLEEP_IF_ALLOWED(wait_instr) \ + do { \ + __DSB(); \ + wait_instr(); \ + ON_EXIT_IDLE_HOOK; \ + } while (false) #endif #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE @@ -94,6 +98,9 @@ void arch_cpu_idle(void) SLEEP_IF_ALLOWED(__WFI); +#if defined(CONFIG_TRACING) + sys_trace_idle_exit(); +#endif __enable_irq(); __ISB(); } @@ -133,6 +140,10 @@ void arch_cpu_atomic_idle(unsigned int key) SLEEP_IF_ALLOWED(__WFE); +#if defined(CONFIG_TRACING) + sys_trace_idle_exit(); +#endif + arch_irq_unlock(key); #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) __enable_irq(); diff --git a/arch/arm/core/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c index 61fb68145350..47141d913dd1 100644 --- a/arch/arm/core/cortex_m/debug.c +++ b/arch/arm/core/cortex_m/debug.c @@ -35,7 +35,7 @@ bool z_arm_debug_monitor_event_error_check(void) printk("Null-pointer exception?\n"); } __ASSERT((DWT->FUNCTION0 & DWT_FUNCTION_MATCHED_Msk) == 0, - "MATCHED flag should have been cleared on read."); + "MATCHED flag should have been cleared on read."); return true; } @@ -55,8 +55,8 @@ bool z_arm_debug_monitor_event_error_check(void) * so we add a build assert that catches it. */ BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE & - (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)), - "the size of the partition must be power of 2"); + (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)), + "the size of the partition must be power of 2"); int z_arm_debug_enable_null_pointer_detection(void) { @@ -81,20 +81,12 @@ int z_arm_debug_enable_null_pointer_detection(void) DWT->COMP0 = 0; DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1; - DWT->FUNCTION0 = - ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) - | - ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) - | - ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk) - ; - DWT->FUNCTION1 = - ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) - | - ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) - | - ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk) - ; + DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) | + ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) | + ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk); + DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) | + ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) | + ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk); #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* ASSERT that we have the comparator needed for the implementation */ @@ -106,13 +98,10 @@ int z_arm_debug_enable_null_pointer_detection(void) /* Use comparator 0, R/W access check */ DWT->COMP0 = 0; - DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & - DWT_FUNCTION_FUNCTION_Msk; - + DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk; /* Set mask according to the desired size */ - DWT->MASK0 = 32 - __builtin_clzl( - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1); + DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1); #endif return 0; diff --git a/arch/arm/core/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c index 56d5be60f4cc..27ce260dad53 100644 --- a/arch/arm/core/cortex_m/fault.c +++ b/arch/arm/core/cortex_m/fault.c @@ -22,7 +22,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) -#define PR_EXC(...) LOG_ERR(__VA_ARGS__) +#define PR_EXC(...) LOG_ERR(__VA_ARGS__) #define STORE_xFAR(reg_var, reg) uint32_t reg_var = (uint32_t)reg #else #define PR_EXC(...) @@ -36,8 +36,8 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #endif #if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU) -#define EMN(edr) (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT) -#define EACD(edr) (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT) +#define EMN(edr) (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT) +#define EACD(edr) (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT) #endif /* Integrity signature for an ARMv8-M implementation */ @@ -54,15 +54,12 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* helpers to access memory/bus/usage faults */ -#define SCB_CFSR_MEMFAULTSR \ - (uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) \ - >> SCB_CFSR_MEMFAULTSR_Pos) -#define SCB_CFSR_BUSFAULTSR \ - (uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) \ - >> SCB_CFSR_BUSFAULTSR_Pos) -#define SCB_CFSR_USGFAULTSR \ - (uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) \ - >> SCB_CFSR_USGFAULTSR_Pos) +#define SCB_CFSR_MEMFAULTSR \ + (uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos) +#define SCB_CFSR_BUSFAULTSR \ + (uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos) +#define SCB_CFSR_USGFAULTSR \ + (uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos) #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ /** @@ -103,8 +100,8 @@ static void fault_show(const struct arch_esf *esf, int fault) PR_EXC("Fault! EXC #%d", fault); #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR, - SCB_CFSR_BUSFAULTSR, SCB_CFSR_USGFAULTSR); + PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR, SCB_CFSR_BUSFAULTSR, + SCB_CFSR_USGFAULTSR); #if defined(CONFIG_ARM_SECURE_FIRMWARE) PR_EXC("SFSR: 0x%x", SAU->SFSR); #endif /* CONFIG_ARM_SECURE_FIRMWARE */ @@ -127,9 +124,7 @@ static void fault_show(const struct arch_esf *esf, int fault) #ifdef CONFIG_USERSPACE Z_EXC_DECLARE(z_arm_user_string_nlen); -static const struct z_exc_handle exceptions[] = { - Z_EXC_HANDLE(z_arm_user_string_nlen) -}; +static const struct z_exc_handle exceptions[] = {Z_EXC_HANDLE(z_arm_user_string_nlen)}; #endif /* Perform an assessment whether an MPU fault shall be @@ -146,12 +141,12 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous) uint32_t end = (uint32_t)exceptions[i].end & ~0x1U; #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT) - /* Non-synchronous exceptions (e.g. DebugMonitor) may have - * allowed PC to continue to the next instruction. - */ - end += (synchronous) ? 0x0 : 0x4; + /* Non-synchronous exceptions (e.g. DebugMonitor) may have + * allowed PC to continue to the next instruction. + */ + end += (synchronous) ? 0x0 : 0x4; #else - ARG_UNUSED(synchronous); + ARG_UNUSED(synchronous); #endif if (esf->basic.pc >= start && esf->basic.pc < end) { esf->basic.pc = (uint32_t)(exceptions[i].fixup); @@ -168,8 +163,7 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) -uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, - const uint32_t psp); +uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp); #endif /* CONFIG_MPU_STACK_GUARD || defined(CONFIG_USERSPACE) */ /** @@ -180,8 +174,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, * * @return error code to identify the fatal error reason */ -static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, - bool *recoverable) +static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverable) { uint32_t reason = K_ERR_ARM_MEM_GENERIC; uint32_t mmfar = -EINVAL; @@ -191,7 +184,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) { reason = K_ERR_ARM_MEM_STACKING; PR_FAULT_INFO(" Stacking error (context area might be" - " not valid)"); + " not valid)"); } if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) { reason = K_ERR_ARM_MEM_UNSTACKING; @@ -226,8 +219,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, #if defined(CONFIG_ARMV7_M_ARMV8_M_FP) if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) { reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION; - PR_FAULT_INFO( - " Floating-point lazy state preservation error"); + PR_FAULT_INFO(" Floating-point lazy state preservation error"); } #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */ @@ -244,8 +236,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, * Data Access Violation errors may or may not be caused by * thread stack overflows. */ - if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) || - (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) { + if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) || (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) { #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) /* MemManage Faults are always banked between security * states. Therefore, we can safely assume the fault @@ -265,8 +256,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, * handle the case of 'mmfar' holding the -EINVAL value. */ if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) { - uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar, - ((uint32_t) &esf[0])); + uint32_t min_stack_ptr = + z_check_thread_stack_fail(mmfar, ((uint32_t)&esf[0])); if (min_stack_ptr) { /* When MemManage Stacking Error has occurred, @@ -299,14 +290,14 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, reason = K_ERR_STACK_CHK_FAIL; } else { __ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk), - "Stacking error not a stack fail\n"); + "Stacking error not a stack fail\n"); } } #else - (void)mmfar; - __ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk), - "Stacking or Data Access Violation error " - "without stack guard, user-mode or null-pointer detection\n"); + (void)mmfar; + __ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk), + "Stacking or Data Access Violation error " + "without stack guard, user-mode or null-pointer detection\n"); #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */ } @@ -408,13 +399,10 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl PR_FAULT_INFO(" NXP MPU error, port %d", i); PR_FAULT_INFO(" Mode: %s, %s Address: 0x%x", - edr & BIT(2) ? "Supervisor" : "User", - edr & BIT(1) ? "Data" : "Instruction", - ear); - PR_FAULT_INFO( - " Type: %s, Master: %d, Regions: 0x%x", - edr & BIT(0) ? "Write" : "Read", - EMN(edr), EACD(edr)); + edr & BIT(2) ? "Supervisor" : "User", + edr & BIT(1) ? "Data" : "Instruction", ear); + PR_FAULT_INFO(" Type: %s, Master: %d, Regions: 0x%x", + edr & BIT(0) ? "Write" : "Read", EMN(edr), EACD(edr)); /* When stack protection is enabled, we need to assess * if the memory violation error is a stack corruption. @@ -437,8 +425,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl */ if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) { uint32_t min_stack_ptr = - z_check_thread_stack_fail(ear, - ((uint32_t) &esf[0])); + z_check_thread_stack_fail(ear, ((uint32_t)&esf[0])); if (min_stack_ptr) { /* When BusFault Stacking Error @@ -468,16 +455,14 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl */ __set_PSP(min_stack_ptr); - reason = - K_ERR_STACK_CHK_FAIL; + reason = K_ERR_STACK_CHK_FAIL; break; } } #else (void)ear; __ASSERT(0, - "Stacking error without stack guard" - "or User-mode support"); + "Stacking error without stack guard or User-mode support"); #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */ } } @@ -617,8 +602,7 @@ static void debug_monitor(struct arch_esf *esf, bool *recoverable) { *recoverable = false; - PR_FAULT_INFO( - "***** Debug monitor exception *****"); + PR_FAULT_INFO("***** Debug monitor exception *****"); #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT) if (!z_arm_debug_monitor_event_error_check()) { @@ -675,7 +659,7 @@ static inline bool z_arm_is_synchronous_svc(struct arch_esf *esf) #endif /* ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE */ if (((fault_insn & 0xff00) == _SVC_OPCODE) && - ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) { + ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) { return true; } #undef _SVC_OPCODE @@ -759,13 +743,11 @@ static uint32_t hard_fault(struct arch_esf *esf, bool *recoverable) reason = secure_fault(esf); #endif /* CONFIG_ARM_SECURE_FIRMWARE */ } else { - __ASSERT(0, - "Fault escalation without FSR info"); + __ASSERT(0, "Fault escalation without FSR info"); } } else { - __ASSERT(0, - "HardFault without HFSR info" - " Shall never occur"); + __ASSERT(0, "HardFault without HFSR info" + " Shall never occur"); } #else #error Unknown ARM architecture @@ -786,8 +768,7 @@ static void reserved_exception(const struct arch_esf *esf, int fault) ARG_UNUSED(esf); PR_FAULT_INFO("***** %s %d) *****", - fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", - fault - 16); + fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", fault - 16); } /* Handler function for ARM fault conditions. */ @@ -802,7 +783,7 @@ static uint32_t fault_handle(struct arch_esf *esf, int fault, bool *recoverable) reason = hard_fault(esf, recoverable); break; #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - /* HardFault is raised for all fault conditions on ARMv6-M. */ + /* HardFault is raised for all fault conditions on ARMv6-M. */ #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) case 4: reason = mem_manage_fault(esf, 0, recoverable); @@ -860,7 +841,7 @@ static void secure_stack_dump(const struct arch_esf *secure_esf) uint32_t sec_ret_addr; #if defined(CONFIG_ARMV7_M_ARMV8_M_FP) if ((*top_of_sec_stack == INTEGRITY_SIGNATURE_STD) || - (*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) { + (*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) { #else if (*top_of_sec_stack == INTEGRITY_SIGNATURE) { #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */ @@ -879,7 +860,6 @@ static void secure_stack_dump(const struct arch_esf *secure_esf) sec_ret_addr = *top_of_sec_stack; } PR_FAULT_INFO(" S instruction address: 0x%x", sec_ret_addr); - } #define SECURE_STACK_DUMP(esf) secure_stack_dump(esf) #else @@ -900,15 +880,14 @@ static void secure_stack_dump(const struct arch_esf *secure_esf) * @return ESF pointer on success, otherwise return NULL */ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_return, - bool *nested_exc) + bool *nested_exc) { bool alternative_state_exc = false; struct arch_esf *ptr_esf = NULL; *nested_exc = false; - if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) != - EXC_RETURN_INDICATOR_PREFIX) { + if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) != EXC_RETURN_INDICATOR_PREFIX) { /* Invalid EXC_RETURN value. This is a fatal error. */ return NULL; } @@ -988,8 +967,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ /* The processor has a single execution state. * We verify that the Thread mode is using PSP. */ - if ((exc_return & EXC_RETURN_MODE_THREAD) && - (!(exc_return & EXC_RETURN_SPSEL_PROCESS))) { + if ((exc_return & EXC_RETURN_MODE_THREAD) && (!(exc_return & EXC_RETURN_SPSEL_PROCESS))) { PR_EXC("SPSEL in thread mode does not indicate PSP"); return NULL; } @@ -998,7 +976,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ if (!alternative_state_exc) { if (exc_return & EXC_RETURN_MODE_THREAD) { /* Returning to thread mode */ - ptr_esf = (struct arch_esf *)psp; + ptr_esf = (struct arch_esf *)psp; } else { /* Returning to handler mode */ @@ -1041,8 +1019,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ * @param callee_regs Callee-saved registers (R4-R11, PSP) * */ -void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, - _callee_saved_t *callee_regs) +void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_t *callee_regs) { uint32_t reason = K_ERR_CPU_EXCEPTION; int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk; @@ -1060,9 +1037,8 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, /* Retrieve the Exception Stack Frame (ESF) to be supplied * as argument to the remainder of the fault handling process. */ - esf = get_esf(msp, psp, exc_return, &nested_exc); - __ASSERT(esf != NULL, - "ESF could not be retrieved successfully. Shall never occur."); + esf = get_esf(msp, psp, exc_return, &nested_exc); + __ASSERT(esf != NULL, "ESF could not be retrieved successfully. Shall never occur."); z_arm_set_fault_sp(esf, exc_return); @@ -1080,11 +1056,8 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, * so we only copy the fields before those. */ memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info)); - esf_copy.extra_info = (struct __extra_esf_info) { - .callee = callee_regs, - .exc_return = exc_return, - .msp = msp - }; + esf_copy.extra_info = (struct __extra_esf_info){ + .callee = callee_regs, .exc_return = exc_return, .msp = msp}; #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ /* Overwrite stacked IPSR to mark a nested exception, diff --git a/arch/arm/core/cortex_m/fpu.c b/arch/arm/core/cortex_m/fpu.c index a9c964d14d1a..b937d725c283 100644 --- a/arch/arm/core/cortex_m/fpu.c +++ b/arch/arm/core/cortex_m/fpu.c @@ -23,11 +23,10 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer) if (CONTROL & CONTROL_FPCA_Msk) { /* Store caller-saved and callee-saved FP registers. */ - __asm__ volatile( - "vstmia %0, {s0-s15}\n" - "vstmia %1, {s16-s31}\n" - :: "r" (buffer->caller_saved), "r" (buffer->callee_saved) : - ); + __asm__ volatile("vstmia %0, {s0-s15}\n" + "vstmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved), + "r"(buffer->callee_saved) + :); buffer->fpscr = __get_FPSCR(); buffer->ctx_saved = true; @@ -55,11 +54,10 @@ void z_arm_restore_fp_context(const struct fpu_ctx_full *buffer) /* Restore FP state. */ __set_FPSCR(buffer->fpscr); - __asm__ volatile( - "vldmia %0, {s0-s15}\n" - "vldmia %1, {s16-s31}\n" - :: "r" (buffer->caller_saved), "r" (buffer->callee_saved) : - ); + __asm__ volatile("vldmia %0, {s0-s15}\n" + "vldmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved), + "r"(buffer->callee_saved) + :); } #endif } diff --git a/arch/arm/core/cortex_m/irq_init.c b/arch/arm/core/cortex_m/irq_init.c index b6b128e3368f..edd1f519677c 100644 --- a/arch/arm/core/cortex_m/irq_init.c +++ b/arch/arm/core/cortex_m/irq_init.c @@ -27,7 +27,12 @@ void z_arm_interrupt_init(void) { int irq = 0; +/* CONFIG_2ND_LVL_ISR_TBL_OFFSET could be treated as total number of level1 interrupts */ +#if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) && defined(CONFIG_2ND_LVL_ISR_TBL_OFFSET) + for (; irq < CONFIG_2ND_LVL_ISR_TBL_OFFSET; irq++) { +#else for (; irq < CONFIG_NUM_IRQS; irq++) { +#endif NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); } } diff --git a/arch/arm/core/cortex_m/irq_manage.c b/arch/arm/core/cortex_m/irq_manage.c index cc62386e8aca..6d1c8917c4dc 100644 --- a/arch/arm/core/cortex_m/irq_manage.c +++ b/arch/arm/core/cortex_m/irq_manage.c @@ -28,23 +28,42 @@ extern void z_arm_reserved(void); -#define NUM_IRQS_PER_REG 32 +#define NUM_IRQS_PER_REG 32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) +/* + * For Cortex-M core, the default interrupt controller is the ARM + * NVIC and therefore the architecture interrupt control functions + * are mapped to the NVIC driver interface. + * + * When NVIC is used together with other interrupt controller for + * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS + * is enabled), the architecture interrupt control functions are mapped + * to the SoC layer in `include/arch/arm/irq.h`. + * The exported arm interrupt control functions which are wrappers of + * NVIC control could be used for SoC to do level 1 irq control to implement SoC + * layer interrupt control functions. + * + * When a custom interrupt controller is used (i.e. + * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture + * interrupt control functions are mapped to the SoC layer in + * `include/arch/arm/irq.h`. + */ + #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) -void arch_irq_enable(unsigned int irq) +void arm_irq_enable(unsigned int irq) { NVIC_EnableIRQ((IRQn_Type)irq); } -void arch_irq_disable(unsigned int irq) +void arm_irq_disable(unsigned int irq) { NVIC_DisableIRQ((IRQn_Type)irq); } -int arch_irq_is_enabled(unsigned int irq) +int arm_irq_is_enabled(unsigned int irq) { return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); } @@ -58,7 +77,7 @@ int arch_irq_is_enabled(unsigned int irq) * of priority levels is a little complex, as there are some hardware * priority levels which are reserved. */ -void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) { /* The kernel may reserve some of the highest priority levels. * So we offset the requested priority level with the number @@ -87,8 +106,7 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) */ __ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1), "invalid priority %d for %d irq! values must be less than %lu\n", - prio - _IRQ_PRIO_OFFSET, irq, - BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); + prio - _IRQ_PRIO_OFFSET, irq, BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); NVIC_SetPriority((IRQn_Type)irq, prio); } @@ -141,7 +159,6 @@ void _arch_isr_direct_pm(void) #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ - } #endif @@ -165,8 +182,7 @@ void _arch_isr_direct_pm(void) * * @return The resulting target state of the given IRQ */ -irq_target_state_t irq_target_state_set(unsigned int irq, - irq_target_state_t irq_target_state) +irq_target_state_t irq_target_state_set(unsigned int irq, irq_target_state_t irq_target_state) { uint32_t result; @@ -217,7 +233,7 @@ int irq_target_state_is_secure(unsigned int irq) * - Bits corresponding to un-implemented interrupts are RES0, so writes * will be ignored. * -*/ + */ void irq_target_state_set_all_non_secure(void) { int i; @@ -241,8 +257,8 @@ void irq_target_state_set_all_non_secure(void) #ifdef CONFIG_DYNAMIC_INTERRUPTS #ifdef CONFIG_GEN_ISR_TABLES int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), - const void *parameter, uint32_t flags) + void (*routine)(const void *parameter), const void *parameter, + uint32_t flags) { z_isr_install(irq, routine, parameter); z_arm_irq_priority_set(irq, priority, flags); diff --git a/arch/arm/core/cortex_m/isr_wrapper.c b/arch/arm/core/cortex_m/isr_wrapper.c index 46aac160c3bf..cb72797e2ec0 100644 --- a/arch/arm/core/cortex_m/isr_wrapper.c +++ b/arch/arm/core/cortex_m/isr_wrapper.c @@ -68,9 +68,12 @@ void _isr_wrapper(void) #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) int32_t irq_number = z_soc_irq_get_active(); #else - /* _sw_isr_table does not map the expections, only the interrupts. */ int32_t irq_number = __get_IPSR(); #endif + /* _sw_isr_table does not map the core system exceptions, + * which take first 16 interrupt numbers, only the external + * interrupts. + */ irq_number -= 16; struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index 4b43fb8d74f9..530fc65835e3 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -178,9 +178,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) /* * Mark entering suspend to RAM. */ - mov r1, lr - bl pm_s2ram_mark_set - mov lr, r1 + bl pm_s2ram_mark_set /* * Call the system_off function passed as parameter. This should never @@ -199,9 +197,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) /* * Reset the marking of suspend to RAM, return is ignored. */ - mov r1, lr - bl pm_s2ram_mark_check_and_clear - mov lr, r1 + bl pm_s2ram_mark_check_and_clear /* Move the stored return value of system_off back to r0, * setting it as return value for this function. @@ -216,17 +212,24 @@ GTEXT(arch_pm_s2ram_resume) SECTION_FUNC(TEXT, arch_pm_s2ram_resume) /* * Check if reset occurred after suspending to RAM. + * Store LR to ensure we can continue boot when we are not suspended + * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0", + * as stated by ARM rule 6.2.1.2 for AAPCS32. */ - mov r1, lr - bl pm_s2ram_mark_check_and_clear - mov lr, r1 - cmp r0, #0x1 - beq .L_resume - bx lr + push {r0, lr} + bl pm_s2ram_mark_check_and_clear + cmp r0, #0x1 + beq .L_resume + pop {r0, pc} .L_resume: /* - * Restore the CPU context + * Switch to the stack used to execute "arch_pm_s2ram_suspend" + * and restore CPU context backed up by that function, then + * return to the call site of "arch_pm_s2ram_suspend". + * + * Note: the "push {r0, lr}" performed earlier doesn't + * need to be balanced out since we are switching stacks. */ ldr r0, =_cpu_context diff --git a/arch/arm/core/cortex_m/pm_s2ram.c b/arch/arm/core/cortex_m/pm_s2ram.c index b7fe5d9b6260..2657d48dc32a 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.c +++ b/arch/arm/core/cortex_m/pm_s2ram.c @@ -22,44 +22,20 @@ __noinit _cpu_context_t _cpu_context; */ static __noinit uint32_t marker; -void __attribute__((naked)) pm_s2ram_mark_set(void) +void pm_s2ram_mark_set(void) { - __asm__ volatile( - /* Set the marker to MAGIC value */ - "str %[_magic_val], [%[_marker]]\n" - - "bx lr\n" - : - : [_magic_val] "r"(MAGIC), [_marker] "r"(&marker) - : "r1", "r4", "memory"); + marker = MAGIC; } -bool __attribute__((naked)) pm_s2ram_mark_check_and_clear(void) +bool pm_s2ram_mark_check_and_clear(void) { - __asm__ volatile( - /* Set return value to 0 */ - "mov r0, #0\n" - - /* Check the marker */ - "ldr r3, [%[_marker]]\n" - "cmp r3, %[_magic_val]\n" - "bne exit\n" - - /* - * Reset the marker - */ - "str r0, [%[_marker]]\n" + if (marker == MAGIC) { + marker = 0; - /* - * Set return value to 1 - */ - "mov r0, #1\n" + return true; + } - "exit:\n" - "bx lr\n" - : - : [_magic_val] "r"(MAGIC), [_marker] "r"(&marker) - : "r0", "r1", "r3", "r4", "memory"); + return false; } #endif /* CONFIG_PM_S2RAM_CUSTOM_MARKING */ diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index ae59960584ce..632fc1420034 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -23,27 +23,27 @@ #include #include -#if defined(__GNUC__) /* * GCC can detect if memcpy is passed a NULL argument, however one of * the cases of relocate_vector_table() it is valid to pass NULL, so we * suppress the warning for this case. We need to do this before * string.h is included to get the declaration of memcpy. */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wnonnull" -#endif +TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_NONNULL) #include #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) -Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) -void *_vector_table_pointer; +Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) void *_vector_table_pointer; #endif #ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR +#ifdef CONFIG_SRAM_VECTOR_TABLE +#define VECTOR_ADDRESS ((uintptr_t)_sram_vector_start) +#else #define VECTOR_ADDRESS ((uintptr_t)_vector_start) +#endif /* In some Cortex-M3 implementations SCB_VTOR bit[29] is called the TBLBASE bit */ #ifdef SCB_VTOR_TBLBASE_Msk @@ -52,8 +52,14 @@ void *_vector_table_pointer; #define VTOR_MASK SCB_VTOR_TBLOFF_Msk #endif -static inline void relocate_vector_table(void) +void __weak relocate_vector_table(void) { +#ifdef CONFIG_SRAM_VECTOR_TABLE + /* Copy vector table to its location in SRAM */ + size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; + + z_early_memcpy(_sram_vector_start, _vector_start, vector_size); +#endif SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK; barrier_dsync_fence_full(); barrier_isync_fence_full(); @@ -64,8 +70,8 @@ static inline void relocate_vector_table(void) void __weak relocate_vector_table(void) { -#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ - !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) +#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ + !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); #elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) @@ -73,9 +79,7 @@ void __weak relocate_vector_table(void) #endif } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif +TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_NONNULL) #endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */ @@ -100,7 +104,7 @@ static inline void z_arm_floating_point_init(void) #else /* Privileged access only */ SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS; -#endif /* CONFIG_USERSPACE */ +#endif /* CONFIG_USERSPACE */ /* * Upon reset, the FPU Context Control Register is 0xC0000000 * (both Automatic and Lazy state preservation is enabled). @@ -170,7 +174,7 @@ static inline void z_arm_floating_point_init(void) * * If CONFIG_INIT_ARCH_HW_AT_BOOT is set, CONTROL is cleared at reset. */ -#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) && \ +#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) && \ (!defined(CONFIG_INIT_ARCH_HW_AT_BOOT)) __set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk))); diff --git a/arch/arm/core/cortex_m/ram_vector_table.ld b/arch/arm/core/cortex_m/ram_vector_table.ld new file mode 100644 index 000000000000..0c2353ab114b --- /dev/null +++ b/arch/arm/core/cortex_m/ram_vector_table.ld @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Vector table is not necessarily at the start of the RAM region: in the case where Zephyr code + * relocation is used, the vector table is placed after the relocated code. + * Relocated code is always placed at the start of the RAM SECTION because of the hard-coded value + * generated by "gen_relocate_app.py" in the file. It can create quite a big gap and lose about the + * size of alignment in RAM space. + */ + +SECTION_PROLOGUE(.sram_vt,,) +{ + /* Heritage of vector table alignment in flash (see vector_table.ld in arch/arm/core/) */ +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + . = ALIGN( 1 << LOG2CEIL(4 * 64) ); +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + . = ALIGN( 1 << LOG2CEIL(4 * 32) ); +#else +#error "Unsupported architecture variant" +#endif + + . = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) ); + + _sram_vector_start = .; + . += _vector_end - _vector_start; + MPU_ALIGN(_sram_vector_size); + _sram_vector_end = .; +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +_sram_vector_size = _sram_vector_end - _sram_vector_start; diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index 742a3fe3d650..c3f9362eca85 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -21,6 +21,7 @@ _ASM_FILE_PROLOGUE GTEXT(z_arm_reset) GTEXT(z_early_memset) GDATA(z_interrupt_stacks) +GDATA(z_main_stack) #if defined(CONFIG_DEBUG_THREAD_INFO) GDATA(z_sys_post_kernel) #endif @@ -29,7 +30,6 @@ GTEXT(soc_reset_hook) #endif #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) GTEXT(z_arm_init_arch_hw_at_boot) -GDATA(z_main_stack) #endif #if defined(CONFIG_PM_S2RAM) GTEXT(arch_pm_s2ram_resume) @@ -83,9 +83,44 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) #endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */ #if defined(CONFIG_PM_S2RAM) + /* + * Temporarily set MSP to interrupt stack so that arch_pm_s2ram_resume can + * use stack for calling pm_s2ram_mark_check_and_clear. + * This is safe because suspend never being called from an ISR ensures that + * interrupt stack was not live during suspend. + * Note: + * if resuming from suspend, MSP is restored from cpu context + * if not resuming, MSP will be set back to z_main_stack for proper init + * And, apart from arch_pm_s2ram_resume being able to use the stack for + * a short while, there is no change in behavior in either of the paths. + */ + ldr r0, =z_interrupt_stacks + CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE + msr msp, r0 + bl arch_pm_s2ram_resume #endif /* CONFIG_PM_S2RAM */ + /* + * MSP needs to be set to main stack for following scenarios: + * - If CONFIG_PM_S2RAM is enabled, MSP is set to z_interrupt_stacks + * for resume functions to make use of a stack. However, + * if the device was not suspended and if resume functions return, + * MSP needs to be set back to z_main_stack to ensure proper + * initialization. + * - If CONFIG_PM_S2RAM is not enabled but CONFIG_INIT_ARCH_HW_AT_BOOT is, + * MSP needs to be set to z_main_stack for proper initialization in case + * device was loaded through chain loading or a debugger, as the initial + * value of MSP would be anything that the previous image loaded. + * - If CONFIG_INIT_STACKS is enabled, we need to ensure MSP is not set + * to z_interrupt_stacks, so we set it to z_main_stack. + * + * Since these scenarios cover most of the cases, we set MSP to + * z_main_stack here. + * + */ + ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE + msr msp, r0 + /* Note: Make sure that variables like z_sys_post_kernel * are set after the call to arch_pm_s2ram_resume * to avoid any issues with suspend/resume path. @@ -110,8 +145,6 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) str r0, [r1] dsb #endif /* CONFIG_CPU_HAS_ARM_MPU */ - ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE - msr msp, r0 /* Initialize core architecture registers and system blocks */ bl z_arm_init_arch_hw_at_boot diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index a511a8de9b1b..957c66dcc9f5 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -55,8 +55,7 @@ void z_arm_clear_arm_mpu_config(void) { int i; - int num_regions = - ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); + int num_regions = ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); for (i = 0; i < num_regions; i++) { ARM_MPU_ClrRegion(i); @@ -90,7 +89,7 @@ void z_arm_clear_arm_mpu_config(void) */ void z_arm_init_arch_hw_at_boot(void) { - /* Disable interrupts */ + /* Disable interrupts */ __disable_irq(); #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) diff --git a/arch/arm/core/cortex_m/semihost.c b/arch/arm/core/cortex_m/semihost.c index 2a8c6d55a051..51ecd1f478c1 100644 --- a/arch/arm/core/cortex_m/semihost.c +++ b/arch/arm/core/cortex_m/semihost.c @@ -9,11 +9,10 @@ long semihost_exec(enum semihost_instr instr, void *args) { - register unsigned int r0 __asm__ ("r0") = instr; - register void *r1 __asm__ ("r1") = args; - register int ret __asm__ ("r0"); + register unsigned int r0 __asm__("r0") = instr; + register void *r1 __asm__("r1") = args; + register int ret __asm__("r0"); - __asm__ __volatile__ ("bkpt 0xab" - : "=r" (ret) : "r" (r0), "r" (r1) : "memory"); + __asm__ volatile("bkpt 0xab" : "=r"(ret) : "r"(r0), "r"(r1) : "memory"); return ret; } diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index c88fd8e41a0f..f1fc2019d9c4 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -22,15 +22,14 @@ #include #if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE) -#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \ - MPU_GUARD_ALIGN_AND_SIZE) +#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - MPU_GUARD_ALIGN_AND_SIZE) #else -#define FP_GUARD_EXTRA_SIZE 0 +#define FP_GUARD_EXTRA_SIZE 0 #endif #ifndef EXC_RETURN_FTYPE /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_FTYPE (0x00000010UL) +#define EXC_RETURN_FTYPE (0x00000010UL) #endif /* Default last octet of EXC_RETURN, for threads that have not run yet. @@ -58,9 +57,8 @@ K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE); * addresses, we have to unset it manually before storing it in the 'pc' field * of the ESF. */ -void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, - char *stack_ptr, k_thread_entry_t entry, - void *p1, void *p2, void *p3) +void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, + k_thread_entry_t entry, void *p1, void *p2, void *p3) { struct __basic_sf *iframe; @@ -105,8 +103,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, iframe->a3 = (uint32_t)p2; iframe->a4 = (uint32_t)p3; - iframe->xpsr = - 0x01000000UL; /* clear all, thumb bit is 1, even if RO */ + iframe->xpsr = 0x01000000UL; /* clear all, thumb bit is 1, even if RO */ thread->callee_saved.psp = (uint32_t)iframe; thread->arch.basepri = 0; @@ -131,52 +128,42 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, */ } -#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) \ - && defined(CONFIG_FPU_SHARING) +#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) -static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, - bool use_large_guard) +static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, bool use_large_guard) { if (use_large_guard) { /* Switch to use a large MPU guard if not already. */ - if ((thread->arch.mode & - Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) { + if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) { /* Default guard size is used. Update required. */ thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk; #if defined(CONFIG_USERSPACE) if (thread->arch.priv_stack_start) { /* User thread */ - thread->arch.priv_stack_start += - FP_GUARD_EXTRA_SIZE; + thread->arch.priv_stack_start += FP_GUARD_EXTRA_SIZE; } else #endif /* CONFIG_USERSPACE */ { /* Privileged thread */ - thread->stack_info.start += - FP_GUARD_EXTRA_SIZE; - thread->stack_info.size -= - FP_GUARD_EXTRA_SIZE; + thread->stack_info.start += FP_GUARD_EXTRA_SIZE; + thread->stack_info.size -= FP_GUARD_EXTRA_SIZE; } } } else { /* Switch to use the default MPU guard size if not already. */ - if ((thread->arch.mode & - Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) { + if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) { /* Large guard size is used. Update required. */ thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk; #if defined(CONFIG_USERSPACE) if (thread->arch.priv_stack_start) { /* User thread */ - thread->arch.priv_stack_start -= - FP_GUARD_EXTRA_SIZE; + thread->arch.priv_stack_start -= FP_GUARD_EXTRA_SIZE; } else #endif /* CONFIG_USERSPACE */ { /* Privileged thread */ - thread->stack_info.start -= - FP_GUARD_EXTRA_SIZE; - thread->stack_info.size += - FP_GUARD_EXTRA_SIZE; + thread->stack_info.start -= FP_GUARD_EXTRA_SIZE; + thread->stack_info.size += FP_GUARD_EXTRA_SIZE; } } } @@ -190,7 +177,7 @@ static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread) { if (((thread->base.user_options & K_FP_REGS) != 0) || - ((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) { + ((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) { /* The thread has been pre-tagged (at creation or later) with * K_FP_REGS, i.e. it is expected to be using the FPU registers * (if not already). Activate lazy stacking and program a large @@ -226,13 +213,11 @@ uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread) #endif #ifdef CONFIG_USERSPACE -FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, - void *p1, void *p2, void *p3) +FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3) { /* Set up privileged stack before entering user mode */ - _current->arch.priv_stack_start = - (uint32_t)z_priv_stack_find(_current->stack_obj); + _current->arch.priv_stack_start = (uint32_t)z_priv_stack_find(_current->stack_obj); #if defined(CONFIG_MPU_STACK_GUARD) #if defined(CONFIG_THREAD_STACK_INFO) /* We're dropping to user mode which means the guard area is no @@ -256,21 +241,19 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, */ #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) _current->arch.priv_stack_start += - ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ? - MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE; + ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) + ? MPU_GUARD_ALIGN_AND_SIZE_FLOAT + : MPU_GUARD_ALIGN_AND_SIZE; #else _current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE; #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ #endif /* CONFIG_MPU_STACK_GUARD */ - z_arm_userspace_enter(user_entry, p1, p2, p3, - (uint32_t)_current->stack_info.start, - _current->stack_info.size - - _current->stack_info.delta); + z_arm_userspace_enter(user_entry, p1, p2, p3, (uint32_t)_current->stack_info.start, + _current->stack_info.size - _current->stack_info.delta); CODE_UNREACHABLE; } - bool z_arm_thread_is_in_user_mode(void) { uint32_t value; @@ -311,14 +294,12 @@ void configure_builtin_stack_guard(struct k_thread *thread) * than the default thread stack (ensured by design). */ uint32_t guard_start = - ((thread->arch.priv_stack_start) && - (__get_PSP() >= thread->arch.priv_stack_start)) ? - (uint32_t)thread->arch.priv_stack_start : - (uint32_t)thread->stack_obj; + ((thread->arch.priv_stack_start) && (__get_PSP() >= thread->arch.priv_stack_start)) + ? (uint32_t)thread->arch.priv_stack_start + : (uint32_t)thread->stack_obj; __ASSERT(thread->stack_info.start == ((uint32_t)thread->stack_obj), - "stack_info.start does not point to the start of the" - "thread allocated area."); + "stack_info.start does not point to the start of the thread allocated area."); #else uint32_t guard_start = thread->stack_info.start; #endif @@ -332,13 +313,11 @@ void configure_builtin_stack_guard(struct k_thread *thread) #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) -#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \ - ((fault_addr != -EINVAL) ? \ - ((fault_addr >= guard_start) && \ - (fault_addr < (guard_start + guard_len)) && \ - (stack_ptr < (guard_start + guard_len))) \ - : \ - (stack_ptr < (guard_start + guard_len))) +#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \ + ((fault_addr != -EINVAL) \ + ? ((fault_addr >= guard_start) && (fault_addr < (guard_start + guard_len)) && \ + (stack_ptr < (guard_start + guard_len))) \ + : (stack_ptr < (guard_start + guard_len))) /** * @brief Assess occurrence of current thread's stack corruption @@ -386,11 +365,10 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp } #endif -#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \ - defined(CONFIG_MPU_STACK_GUARD) - uint32_t guard_len = - ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ? - MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE; +#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && defined(CONFIG_MPU_STACK_GUARD) + uint32_t guard_len = ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) + ? MPU_GUARD_ALIGN_AND_SIZE_FLOAT + : MPU_GUARD_ALIGN_AND_SIZE; #else /* If MPU_STACK_GUARD is not enabled, the guard length is * effectively zero. Stack overflows may be detected only @@ -404,10 +382,8 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp /* User thread */ if (z_arm_thread_is_in_user_mode() == false) { /* User thread in privilege mode */ - if (IS_MPU_GUARD_VIOLATION( - thread->arch.priv_stack_start - guard_len, - guard_len, - fault_addr, psp)) { + if (IS_MPU_GUARD_VIOLATION(thread->arch.priv_stack_start - guard_len, + guard_len, fault_addr, psp)) { /* Thread's privilege stack corruption */ return thread->arch.priv_stack_start; } @@ -419,26 +395,21 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp } } else { /* Supervisor thread */ - if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - - guard_len, - guard_len, - fault_addr, psp)) { + if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len, + fault_addr, psp)) { /* Supervisor thread stack corruption */ return thread->stack_info.start; } } #else /* CONFIG_USERSPACE */ #if defined(CONFIG_MULTITHREADING) - if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, - guard_len, - fault_addr, psp)) { + if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len, fault_addr, + psp)) { /* Thread stack corruption */ return thread->stack_info.start; } #else - if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack, - guard_len, - fault_addr, psp)) { + if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack, guard_len, fault_addr, psp)) { /* Thread stack corruption */ return (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack); } @@ -572,23 +543,23 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, * When calling arch_irq_unlock_outlined, LR is lost which is fine since * we do not intend to return after calling z_thread_entry. */ - __asm__ volatile ( - "mov r4, %0\n" /* force _main to be stored in a register */ - "msr PSP, %1\n" /* __set_PSP(stack_ptr) */ - - "movs r0, #0\n" /* arch_irq_unlock(0) */ - "ldr r3, =arch_irq_unlock_outlined\n" - "blx r3\n" - - "mov r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */ - "movs r1, #0\n" - "movs r2, #0\n" - "movs r3, #0\n" - "ldr r4, =z_thread_entry\n" - "bx r4\n" /* We don’t intend to return, so there is no need to link. */ - : - : "r" (_main), "r" (stack_ptr) - : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory"); + __asm__ volatile("mov r4, %0\n" /* force _main to be stored in a register */ + "msr PSP, %1\n" /* __set_PSP(stack_ptr) */ + + "movs r0, #0\n" /* arch_irq_unlock(0) */ + "ldr r3, =arch_irq_unlock_outlined\n" + "blx r3\n" + + "mov r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */ + "movs r1, #0\n" + "movs r2, #0\n" + "movs r3, #0\n" + "ldr r4, =z_thread_entry\n" + /* We don’t intend to return, so there is no need to link. */ + "bx r4\n" + : + : "r"(_main), "r"(stack_ptr) + : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory"); CODE_UNREACHABLE; } @@ -597,7 +568,7 @@ __used void arch_irq_unlock_outlined(unsigned int key) { #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) __enable_fault_irq(); /* alters FAULTMASK */ - __enable_irq(); /* alters PRIMASK */ + __enable_irq(); /* alters PRIMASK */ #endif arch_irq_unlock(key); } @@ -609,14 +580,13 @@ __used unsigned int arch_irq_lock_outlined(void) #if !defined(CONFIG_MULTITHREADING) -FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( - k_thread_entry_t main_entry, void *p1, void *p2, void *p3) +FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_entry, void *p1, + void *p2, void *p3) { z_arm_prepare_switch_to_main(); /* Set PSP to the highest address of the main stack. */ - char *psp = K_THREAD_STACK_BUFFER(z_main_stack) + - K_THREAD_STACK_SIZEOF(z_main_stack); + char *psp = K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack); #if defined(CONFIG_BUILTIN_STACK_GUARD) char *psplim = (K_THREAD_STACK_BUFFER(z_main_stack)); @@ -636,31 +606,31 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( * with the thread entry process. */ - __asm__ volatile ( + __asm__ volatile( #ifdef CONFIG_BUILTIN_STACK_GUARD - "msr PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */ + "msr PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */ #endif - "msr PSP, %[_psp]\n" /* __set_PSP(psp) */ - "mov r0, #0\n" - "ldr r1, =arch_irq_unlock_outlined\n" - "blx r1\n" - - "mov r0, %[_p1]\n" - "mov r1, %[_p2]\n" - "mov r2, %[_p3]\n" - "blx %[_main_entry]\n" /* main_entry(p1, p2, p3) */ - - "ldr r0, =arch_irq_lock_outlined\n" - "blx r0\n" - "loop: b loop\n\t" /* while (true); */ - : - : [_p1]"r" (p1), [_p2]"r" (p2), [_p3]"r" (p3), - [_psp]"r" (psp), [_main_entry]"r" (main_entry) + "msr PSP, %[_psp]\n" /* __set_PSP(psp) */ + "movs r0, #0\n" + "ldr r1, =arch_irq_unlock_outlined\n" + "blx r1\n" + + "mov r0, %[_p1]\n" + "mov r1, %[_p2]\n" + "mov r2, %[_p3]\n" + "blx %[_main_entry]\n" /* main_entry(p1, p2, p3) */ + + "ldr r0, =arch_irq_lock_outlined\n" + "blx r0\n" + "loop: b loop\n\t" /* while (true); */ + : + : [_p1] "r"(p1), [_p2] "r"(p2), [_p3] "r"(p3), [_psp] "r"(psp), + [_main_entry] "r"(main_entry) #ifdef CONFIG_BUILTIN_STACK_GUARD - , [_psplim]"r" (psplim) + , + [_psplim] "r"(psplim) #endif - : "r0", "r1", "r2", "ip", "lr" - ); + : "r0", "r1", "r2", "ip", "lr"); CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ } diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c index 6cb157552ace..2ce7f64552ba 100644 --- a/arch/arm/core/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -73,7 +73,6 @@ static inline uint64_t z_arm_dwt_freq_get(void) } while ((dcyc == 0) || (ddwt == 0)); dwt_frequency = (cyc_freq * ddwt) / dcyc; - } return dwt_frequency; #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ @@ -100,8 +99,7 @@ timing_t arch_timing_counter_get(void) return (timing_t)z_arm_dwt_get_cycles(); } -uint64_t arch_timing_cycles_get(volatile timing_t *const start, - volatile timing_t *const end) +uint64_t arch_timing_cycles_get(volatile timing_t *const start, volatile timing_t *const end) { return ((uint32_t)*end - (uint32_t)*start); } diff --git a/arch/arm/core/cortex_m/tz/CMakeLists.txt b/arch/arm/core/cortex_m/tz/CMakeLists.txt index 19c67476e40e..aac4f6516194 100644 --- a/arch/arm/core/cortex_m/tz/CMakeLists.txt +++ b/arch/arm/core/cortex_m/tz/CMakeLists.txt @@ -2,7 +2,10 @@ # '-mcmse' enables the generation of code for the Secure state of the ARMv8-M # Security Extensions. This option is required when building a Secure firmware. -zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE -mcmse) + +zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$:$>) +zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$:$>) +zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$:$>) if(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS) diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index 5fdc5471a6bb..d44e7dd2e2c2 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -7,6 +7,7 @@ #include #include +#include #include #include @@ -316,11 +317,32 @@ static void thm_movs_handler(elf_word reloc_type, uint32_t loc, * Do NOT mix them with not 'Thumb instructions' in the below switch/case: they are not * intended to work together. */ -int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, - const char *sym_name, uintptr_t load_bias) +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) { int ret = 0; elf_word reloc_type = ELF32_R_TYPE(rel->r_info); + const uintptr_t load_bias = (uintptr_t)ext->mem[LLEXT_MEM_TEXT]; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } LOG_DBG("%d %lx %lx %s", reloc_type, loc, sym_base_addr, sym_name); diff --git a/arch/arm/core/mmu/arm_mmu.c b/arch/arm/core/mmu/arm_mmu.c index 4b398eb2d16e..62ef1492557c 100644 --- a/arch/arm/core/mmu/arm_mmu.c +++ b/arch/arm/core/mmu/arm_mmu.c @@ -805,10 +805,10 @@ int z_arm_mmu_init(void) } /* Clear TTBR1 */ - __asm__ __volatile__("mcr p15, 0, %0, c2, c0, 1" : : "r"(reg_val)); + __asm__ volatile("mcr p15, 0, %0, c2, c0, 1" : : "r"(reg_val)); /* Write TTBCR: EAE, security not yet relevant, N[2:0] = 0 */ - __asm__ __volatile__("mcr p15, 0, %0, c2, c0, 2" + __asm__ volatile("mcr p15, 0, %0, c2, c0, 2" : : "r"(reg_val)); /* Write TTBR0 */ diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig index 67baee979c9b..698b2bb270a8 100644 --- a/arch/arm/core/mpu/Kconfig +++ b/arch/arm/core/mpu/Kconfig @@ -1,6 +1,7 @@ # Memory Protection Unit (MPU) configuration options # Copyright (c) 2017 Linaro Limited +# Copyright 2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 if CPU_HAS_MPU @@ -68,6 +69,16 @@ config CUSTOM_SECTION_MIN_ALIGN_SIZE size is configured by users, it must also respect the power of two regulation if hardware requires. +config ARM_MPU_PXN + bool + default y + depends on ARMV8_1_M_MAINLINE + help + Enable support for Armv8.1-m MPU's Privileged Execute Never (PXN) attr. + An MPU region marked with PXN attribute can only be executed from an + unprivileged mode and executing such region from privileged mode will + result in a Memory Management fault. + endif # ARM_MPU endif # CPU_HAS_MPU diff --git a/arch/arm/core/mpu/arm_core_mpu.c b/arch/arm/core/mpu/arm_core_mpu.c index dde98c0b07fa..2426b85aacbf 100644 --- a/arch/arm/core/mpu/arm_core_mpu.c +++ b/arch/arm/core/mpu/arm_core_mpu.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Linaro Limited. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -62,55 +63,80 @@ extern char __ram_text_reloc_start[]; extern char __ram_text_reloc_size[]; #endif +#if defined(CONFIG_SRAM_VECTOR_TABLE) +extern char _sram_vector_start[]; +extern char _sram_vector_size[]; +#endif + static const struct z_arm_mpu_partition static_regions[] = { #if defined(CONFIG_COVERAGE_GCOV) && defined(CONFIG_USERSPACE) - { + { /* GCOV code coverage accounting area. Needs User permissions * to function */ .start = (uint32_t)&__gcov_bss_start, .size = (uint32_t)&__gcov_bss_size, .attr = K_MEM_PARTITION_P_RW_U_RW, - }, + }, #endif /* CONFIG_COVERAGE_GCOV && CONFIG_USERSPACE */ #if defined(CONFIG_NOCACHE_MEMORY) - { + { /* Special non-cacheable RAM area */ .start = (uint32_t)&_nocache_ram_start, .size = (uint32_t)&_nocache_ram_size, .attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE, - }, + }, #endif /* CONFIG_NOCACHE_MEMORY */ #if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT) - { + { /* Special RAM area for program text */ .start = (uint32_t)&__ramfunc_start, .size = (uint32_t)&__ramfunc_size, +#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE) + .attr = K_MEM_PARTITION_P_R_U_RX, +#else .attr = K_MEM_PARTITION_P_RX_U_RX, - }, +#endif + }, #endif /* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT */ #if defined(CONFIG_CODE_DATA_RELOCATION_SRAM) - { + { /* RAM area for relocated text */ .start = (uint32_t)&__ram_text_reloc_start, .size = (uint32_t)&__ram_text_reloc_size, +#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE) + .attr = K_MEM_PARTITION_P_R_U_RX, +#else .attr = K_MEM_PARTITION_P_RX_U_RX, - }, +#endif + }, #endif /* CONFIG_CODE_DATA_RELOCATION_SRAM */ +#if defined(CONFIG_SRAM_VECTOR_TABLE) + { + /* Vector table in SRAM */ + .start = (uint32_t)&_sram_vector_start, + .size = (uint32_t)&_sram_vector_size, +#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE) + .attr = K_MEM_PARTITION_P_R_U_RX, +#else + .attr = K_MEM_PARTITION_P_RO_U_RO, +#endif + }, +#endif /* CONFIG_SRAM_VECTOR_TABLE */ #if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_MPU_STACK_GUARD) - /* Main stack MPU guard to detect overflow. - * Note: - * FPU_SHARING and USERSPACE are not supported features - * under CONFIG_MULTITHREADING=n, so the MPU guard (if - * exists) is reserved aside of CONFIG_MAIN_STACK_SIZE - * and there is no requirement for larger guard area (FP - * context is not stacked). - */ - { - .start = (uint32_t)z_main_stack, - .size = (uint32_t)MPU_GUARD_ALIGN_AND_SIZE, - .attr = K_MEM_PARTITION_P_RO_U_NA, - }, + /* Main stack MPU guard to detect overflow. + * Note: + * FPU_SHARING and USERSPACE are not supported features + * under CONFIG_MULTITHREADING=n, so the MPU guard (if + * exists) is reserved aside of CONFIG_MAIN_STACK_SIZE + * and there is no requirement for larger guard area (FP + * context is not stacked). + */ + { + .start = (uint32_t)z_main_stack, + .size = (uint32_t)MPU_GUARD_ALIGN_AND_SIZE, + .attr = K_MEM_PARTITION_P_RO_U_NA, + }, #endif /* !CONFIG_MULTITHREADING && CONFIG_MPU_STACK_GUARD */ }; diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c index bec7b18a4f2c..f9a5397da464 100644 --- a/arch/arm/core/mpu/arm_mpu.c +++ b/arch/arm/core/mpu/arm_mpu.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Linaro Limited. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -93,7 +94,7 @@ static int region_allocate_and_init(const uint8_t index, (reg).dt_addr, \ (reg).dt_size, \ _ATTR) - +#ifdef CONFIG_MEM_ATTR /* This internal function programs the MPU regions defined in the DT when using * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property. */ @@ -111,6 +112,11 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index) case DT_MEM_ARM_MPU_RAM: region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_ATTR); break; +#ifdef CONFIG_ARM_MPU_PXN + case DT_MEM_ARM_MPU_RAM_PXN: + region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_ATTR_PXN); + break; +#endif #ifdef REGION_RAM_NOCACHE_ATTR case DT_MEM_ARM_MPU_RAM_NOCACHE: region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_NOCACHE_ATTR); @@ -158,7 +164,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index) return 0; } - +#endif /* CONFIG_MEM_ATTR */ /* This internal function programs an MPU region * of a given configuration at a given MPU index. */ @@ -459,13 +465,13 @@ int z_arm_mpu_init(void) /* Update the number of programmed MPU regions. */ static_regions_num = mpu_config.num_regions; - +#ifdef CONFIG_MEM_ATTR /* DT-defined MPU regions. */ if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) { __ASSERT(0, "Failed to allocate MPU regions from DT\n"); return -EINVAL; } - +#endif /* CONFIG_MEM_ATTR */ /* Clear all regions before enabling MPU */ for (int i = static_regions_num; i < get_num_regions(); i++) { mpu_clear_region(i); diff --git a/arch/arm/core/mpu/arm_mpu_v7_internal.h b/arch/arm/core/mpu/arm_mpu_v7_internal.h index 9641ab250003..40d03865d07c 100644 --- a/arch/arm/core/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v7_internal.h @@ -145,7 +145,7 @@ static inline int get_dyn_region_min_index(void) /* Only a single bit is set for all user accessible permissions. * In ARMv7-M MPU this is bit AP[1]. */ -#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO & RO) +#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO) /** * This internal function checks if the region is user accessible or not. diff --git a/arch/arm/core/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h index 51ab093d17c5..0716c017ff96 100644 --- a/arch/arm/core/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h @@ -1,6 +1,7 @@ /* * Copyright (c) 2017 Linaro Limited. * Copyright (c) 2018 Nordic Semiconductor ASA. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -158,6 +159,7 @@ static void mpu_set_region(uint32_t rnr, uint32_t rbar, uint32_t rlar) static void region_init(const uint32_t index, const struct arm_mpu_region *region_conf) { + /* clang-format off */ mpu_set_region( /* RNR */ index, @@ -170,7 +172,11 @@ static void region_init(const uint32_t index, | ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | MPU_RLAR_EN_Msk +#ifdef CONFIG_ARM_MPU_PXN + | ((region_conf->attr.pxn << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) +#endif ); + /* clang-format on */ LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x", index, region_conf->base, region_conf->attr.rbar, @@ -279,6 +285,9 @@ static inline void mpu_region_get_access_attr(const uint32_t index, (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk); attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >> MPU_RLAR_AttrIndx_Pos; +#ifdef CONFIG_ARM_MPU_PXN + attr->pxn = (mpu_get_rlar() & MPU_RLAR_PXN_Msk) >> MPU_RLAR_PXN_Pos; +#endif } static inline void mpu_region_get_conf(const uint32_t index, @@ -313,6 +322,9 @@ static inline void get_region_attr_from_mpu_partition_info( (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk); p_attr->mair_idx = attr->mair_idx; p_attr->r_limit = REGION_LIMIT_ADDR(base, size); +#ifdef CONFIG_ARM_MPU_PXN + p_attr->pxn = attr->pxn; +#endif } #if defined(CONFIG_USERSPACE) diff --git a/arch/arm/core/mpu/nxp_mpu.c b/arch/arm/core/mpu/nxp_mpu.c index b0fe24c6bf61..ae893086901c 100644 --- a/arch/arm/core/mpu/nxp_mpu.c +++ b/arch/arm/core/mpu/nxp_mpu.c @@ -151,7 +151,7 @@ static int region_allocate_and_init(const uint8_t index, .end = (reg).dt_addr + (reg).dt_size, \ .attr = _ATTR, \ } - +#ifdef CONFIG_MEM_ATTR /* This internal function programs the MPU regions defined in the DT when using * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property. */ @@ -198,7 +198,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index) return 0; } - +#endif /* CONFIG_MEM_ATTR */ /** * This internal function is utilized by the MPU driver to combine a given * region attribute configuration and size and fill-in a driver-specific @@ -700,13 +700,13 @@ int z_arm_mpu_init(void) /* Update the number of programmed MPU regions. */ static_regions_num = mpu_config.num_regions; - +#ifdef CONFIG_MEM_ATTR /* DT-defined MPU regions. */ if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) { __ASSERT(0, "Failed to allocate MPU regions from DT\n"); return -EINVAL; } - +#endif /* CONFIG_MEM_ATTR */ arm_core_mpu_enable(); return 0; diff --git a/arch/arm/core/tls.c b/arch/arm/core/tls.c index 9b731286c7da..0dc21285a916 100644 --- a/arch/arm/core/tls.c +++ b/arch/arm/core/tls.c @@ -40,8 +40,10 @@ size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr) stack_ptr -= z_tls_data_size(); z_tls_copy(stack_ptr); +#ifndef __IAR_SYSTEMS_ICC__ /* Skip two pointers due to toolchain */ stack_ptr -= sizeof(uintptr_t) * 2; +#endif /* * Set thread TLS pointer which is used in diff --git a/arch/arm/include/cortex_m/cmse.h b/arch/arm/include/cortex_m/cmse.h index ff5e5120d8d3..ca997220dbd1 100644 --- a/arch/arm/include/cortex_m/cmse.h +++ b/arch/arm/include/cortex_m/cmse.h @@ -139,7 +139,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * where typeof is used instead of __typeof__) */ #ifndef typeof -#define typeof __typeof__ +#define typeof __typeof__ #endif /** @@ -157,8 +157,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * * @return p_obj if object is readable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_READ_OK(p_obj) \ - cmse_check_pointed_object(p_obj, CMSE_MPU_READ) +#define ARM_CMSE_OBJECT_READ_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READ) /** * @brief Read accessibility of an object (nPRIV mode) @@ -175,7 +174,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * * @return p_obj if object is readable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj) \ +#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj) \ cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READ) /** @@ -193,8 +192,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * * @return p_obj if object is Read and Writable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) \ - cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE) +#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE) /** * @brief Read and Write accessibility of an object (nPRIV mode) @@ -211,7 +209,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * * @return p_obj if object is Read and Writable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj) \ +#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj) \ cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE) #if defined(CONFIG_ARM_SECURE_FIRMWARE) @@ -231,7 +229,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr * @param addr The address for which the MPU region is requested * * @return a valid MPU region number or -EINVAL - */ + */ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr); /** @@ -249,7 +247,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr); * @param addr The address for which the SAU region is requested * * @return a valid SAU region number or -EINVAL - */ + */ int arm_cmse_sau_region_get(uint32_t addr); /** @@ -267,7 +265,7 @@ int arm_cmse_sau_region_get(uint32_t addr); * @param addr The address for which the IDAU region is requested * * @return a valid IDAU region number or -EINVAL - */ + */ int arm_cmse_idau_region_get(uint32_t addr); /** @@ -342,8 +340,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv); * * @return 1 if address range is readable, 0 otherwise. */ -int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, - int force_npriv); +int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv); /** * @brief Non-Secure Read and Write accessibility of an address range @@ -365,8 +362,7 @@ int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, * * @return 1 if address range is readable, 0 otherwise. */ -int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, - int force_npriv); +int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv); /** * @brief Non-Secure Read accessibility of an object @@ -383,7 +379,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, * * @return p_obj if object is readable from Non-Secure state, NULL otherwise. */ -#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj) \ +#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj) \ cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READ) /** @@ -401,9 +397,8 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, * * @return p_obj if object is readable from Non-Secure state, NULL otherwise. */ -#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj) \ - cmse_check_pointed_object(p_obj, \ - CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ) +#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj) \ + cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ) /** * @brief Non-Secure Read and Write accessibility of an object @@ -420,7 +415,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, * * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj) \ +#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj) \ cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READWRITE) /** @@ -438,9 +433,8 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, * * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise. */ -#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj) \ - cmse_check_pointed_object(p_obj, \ - CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE) +#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj) \ + cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE) #endif /* CONFIG_ARM_SECURE_FIRMWARE */ diff --git a/arch/arm/include/cortex_m/dwt.h b/arch/arm/include/cortex_m/dwt.h index ed0df44dfde5..fe946ecb590e 100644 --- a/arch/arm/include/cortex_m/dwt.h +++ b/arch/arm/include/cortex_m/dwt.h @@ -32,12 +32,18 @@ extern "C" { /* Define DWT LSR masks which are currently not defined by the CMSIS V5.1.2. * (LSR register is defined but not its bitfields). * Reuse ITM LSR mask as it is the same offset than DWT LSR one. + * TODO: update these to use only CMSIS_6 when all of zephyr and modules have + * update to CMSIS_6. */ #if !defined DWT_LSR_Present_Msk -#define DWT_LSR_Present_Msk ITM_LSR_Present_Msk +#define DWT_LSR_Present_Msk \ + IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Present_Msk)) \ + IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_PRESENT_Msk)) #endif #if !defined DWT_LSR_Access_Msk -#define DWT_LSR_Access_Msk ITM_LSR_Access_Msk +#define DWT_LSR_Access_Msk \ + IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Access_Msk)) \ + IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_ACCESS_Msk)) #endif static inline void dwt_access(bool ena) @@ -64,7 +70,7 @@ static inline void dwt_access(bool ena) } } } -#else /* CONFIG_CPU_CORTEX_M7 */ +#else /* CONFIG_CPU_CORTEX_M7 */ ARG_UNUSED(ena); #endif /* CONFIG_CPU_CORTEX_M7 */ } @@ -103,9 +109,8 @@ static inline int z_arm_dwt_init_cycle_counter(void) /* Assert that the cycle counter is indeed implemented. * The field is called NOCYCCNT. So 1 means there is no cycle counter. */ - __ASSERT((DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk) == 0, - "DWT implements no cycle counter. " - "Cannot be used for cycle counting\n"); + __ASSERT((DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk) == 0, "DWT implements no cycle counter. " + "Cannot be used for cycle counting\n"); return 0; } @@ -148,7 +153,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void) * assert that the CPU is in normal mode. */ __ASSERT((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == 0, - "Cannot enable DBM when CPU is in Debug mode\n"); + "Cannot enable DBM when CPU is in Debug mode\n"); #if defined(CONFIG_ARMV8_M_SE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE) /* @@ -158,8 +163,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void) * when enabling the DebugMonitor exception, assert that * it is not targeting the Non Secure domain. */ - __ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0, - "DebugMonitor targets Non-Secure\n"); + __ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n"); #endif /* The DebugMonitor handler priority is set already diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index c021d59d7641..cbac2724587a 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -37,7 +37,7 @@ extern volatile irq_offload_routine_t offload_routine; /* Writes to the AIRCR must be accompanied by a write of the value 0x05FA * to the Vector Key field, otherwise the writes are ignored. */ -#define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL +#define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL /* Exception Return (EXC_RETURN) is provided in LR upon exception entry. * It is used to perform an exception return and to detect possible state @@ -47,45 +47,44 @@ extern volatile irq_offload_routine_t offload_routine; /* Prefix. Indicates that this is an EXC_RETURN value. * This field reads as 0b11111111. */ -#define EXC_RETURN_INDICATOR_PREFIX (0xFF << 24) +#define EXC_RETURN_INDICATOR_PREFIX (0xFFU << 24) /* bit[0]: Exception Secure. The security domain the exception was taken to. */ -#define EXC_RETURN_EXCEPTION_SECURE_Pos 0 -#define EXC_RETURN_EXCEPTION_SECURE_Msk \ - BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) +#define EXC_RETURN_EXCEPTION_SECURE_Pos 0 +#define EXC_RETURN_EXCEPTION_SECURE_Msk BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) #define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0 -#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk +#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk /* bit[2]: Stack Pointer selection. */ -#define EXC_RETURN_SPSEL_Pos 2 -#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos) -#define EXC_RETURN_SPSEL_MAIN 0 -#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk +#define EXC_RETURN_SPSEL_Pos 2 +#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos) +#define EXC_RETURN_SPSEL_MAIN 0 +#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk /* bit[3]: Mode. Indicates the Mode that was stacked from. */ -#define EXC_RETURN_MODE_Pos 3 -#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk +#define EXC_RETURN_MODE_Pos 3 +#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk /* bit[4]: Stack frame type. Indicates whether the stack frame is a standard * integer only stack frame or an extended floating-point stack frame. */ -#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4 -#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos) -#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0 -#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk +#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4 +#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos) +#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0 +#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk /* bit[5]: Default callee register stacking. Indicates whether the default * stacking rules apply, or whether the callee registers are already on the * stack. */ -#define EXC_RETURN_CALLEE_STACK_Pos 5 -#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos) -#define EXC_RETURN_CALLEE_STACK_SKIPPED 0 -#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk +#define EXC_RETURN_CALLEE_STACK_Pos 5 +#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos) +#define EXC_RETURN_CALLEE_STACK_SKIPPED 0 +#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk /* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or * Non-secure stack is used to restore stack frame on exception return. */ -#define EXC_RETURN_RETURN_STACK_Pos 6 -#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos) -#define EXC_RETURN_RETURN_STACK_Non_Secure 0 -#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk +#define EXC_RETURN_RETURN_STACK_Pos 6 +#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos) +#define EXC_RETURN_RETURN_STACK_Non_Secure 0 +#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk /* * The current executing vector is found in the IPSR register. All @@ -170,8 +169,8 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) #endif /* CONFIG_ARM_SECURE_FIRMWARE */ /* Enable Usage, Mem, & Bus Faults */ - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk | - SCB_SHCSR_BUSFAULTENA_Msk; + SCB->SHCSR |= + SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk; #if defined(CONFIG_ARM_SECURE_FIRMWARE) /* Enable Secure Fault */ SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk; @@ -180,25 +179,21 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) #endif /* CONFIG_ARM_SECURE_FIRMWARE */ #endif /* CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS */ -#if defined(CONFIG_ARM_SECURE_FIRMWARE) && \ - !defined(CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI) +#if defined(CONFIG_ARM_SECURE_FIRMWARE) && !defined(CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI) /* Set NMI, Hard, and Bus Faults as Non-Secure. * NMI and Bus Faults targeting the Secure state will * escalate to a SecureFault or SecureHardFault. */ SCB->AIRCR = - (SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk))) - | SCB_AIRCR_BFHFNMINS_Msk - | ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) & - SCB_AIRCR_VECTKEY_Msk); + (SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk))) | SCB_AIRCR_BFHFNMINS_Msk | + ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk); /* Note: Fault conditions that would generate a SecureFault * in a PE with the Main Extension instead generate a * SecureHardFault in a PE without the Main Extension. */ #endif /* ARM_SECURE_FIRMWARE && !ARM_SECURE_BUSFAULT_HARDFAULT_NMI */ -#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && \ - !defined(CONFIG_CORTEX_M_SYSTICK) +#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && !defined(CONFIG_CORTEX_M_SYSTICK) /* SoC implements SysTick, but the system does not use it * as driver for system timing. However, the SysTick IRQ is * always enabled, so we must ensure the interrupt priority @@ -208,7 +203,6 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) */ NVIC_SetPriority(SysTick_IRQn, _EXC_IRQ_DEFAULT_PRIO); #endif /* CPU_CORTEX_M_HAS_SYSTICK && ! CORTEX_M_SYSTICK */ - } /** @@ -221,9 +215,7 @@ static ALWAYS_INLINE void z_arm_clear_faults(void) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* Reset all faults */ - SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk | - SCB_CFSR_MEMFAULTSR_Msk | - SCB_CFSR_BUSFAULTSR_Msk; + SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk | SCB_CFSR_MEMFAULTSR_Msk | SCB_CFSR_BUSFAULTSR_Msk; /* Clear all Hard Faults - HFSR is write-one-to-clear */ SCB->HFSR = 0xffffffff; @@ -253,7 +245,7 @@ static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_ * registers if necessary */ if ((exc_return & EXC_RETURN_STACK_FRAME_TYPE_STANDARD) == - EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) { + EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) { z_arm_coredump_fault_sp += sizeof(esf->fpu); } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ diff --git a/arch/arm/include/cortex_m/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h index 2a24103a32de..5abe5870762c 100644 --- a/arch/arm/include/cortex_m/kernel_arch_func.h +++ b/arch/arm/include/cortex_m/kernel_arch_func.h @@ -61,26 +61,21 @@ static ALWAYS_INLINE void arch_kernel_init(void) #endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } -static ALWAYS_INLINE void -arch_thread_return_value_set(struct k_thread *thread, unsigned int value) +static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value) { thread->arch.swap_return_value = value; } #if !defined(CONFIG_MULTITHREADING) -extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( - k_thread_entry_t main_func, - void *p1, void *p2, void *p3); +extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_func, + void *p1, void *p2, void *p3); -#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \ - z_arm_switch_to_main_no_multithreading +#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING z_arm_switch_to_main_no_multithreading #endif /* !CONFIG_MULTITHREADING */ -extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, - void *p1, void *p2, void *p3, - uint32_t stack_end, - uint32_t stack_start); +extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, void *p1, void *p2, + void *p3, uint32_t stack_end, uint32_t stack_start); extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); @@ -102,7 +97,6 @@ static ALWAYS_INLINE int arch_swap(unsigned int key) return _current->arch.swap_return_value; } - #endif /* _ASMLANGUAGE */ #ifdef __cplusplus diff --git a/arch/arm/include/cortex_m/stack.h b/arch/arm/include/cortex_m/stack.h index feeaf719a88e..6b534a3ea5b1 100644 --- a/arch/arm/include/cortex_m/stack.h +++ b/arch/arm/include/cortex_m/stack.h @@ -26,8 +26,7 @@ extern "C" { #endif -K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, - CONFIG_ISR_STACK_SIZE); +K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE); /** * @@ -39,9 +38,8 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, */ static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) { - uint32_t msp = - (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + - K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); + uint32_t msp = (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); __set_MSP(msp); #if defined(CONFIG_BUILTIN_STACK_GUARD) diff --git a/arch/arm/include/cortex_m/tz_ns.h b/arch/arm/include/cortex_m/tz_ns.h index 51ed5eb1ca9f..dd6dcb4c22e5 100644 --- a/arch/arm/include/cortex_m/tz_ns.h +++ b/arch/arm/include/cortex_m/tz_ns.h @@ -46,24 +46,18 @@ * the functions have been called. This instruction must leave * r0-r3 unmodified. */ -#define __TZ_WRAP_FUNC_RAW(preface, name, postface, store_lr, load_lr) \ - __asm__ volatile( \ - ".global "#preface"; .type "#preface", %function"); \ - __asm__ volatile( \ - ".global "#name"; .type "#name", %function"); \ - __asm__ volatile( \ - ".global "#postface"; .type "#postface", %function"); \ - __asm__ volatile( \ - store_lr "\n\t" \ - "push {r0-r3}\n\t" \ - "bl " #preface "\n\t" \ - "pop {r0-r3}\n\t" \ - "bl " #name " \n\t" \ - "push {r0-r3}\n\t" \ - "bl " #postface "\n\t" \ - "pop {r0-r3}\n\t" \ - load_lr "\n\t" \ - ::); +#define __TZ_WRAP_FUNC_RAW(preface, name, postface, store_lr, load_lr) \ + __asm__ volatile(".global " #preface "; .type " #preface ", %function"); \ + __asm__ volatile(".global " #name "; .type " #name ", %function"); \ + __asm__ volatile(".global " #postface "; .type " #postface ", %function"); \ + __asm__ volatile(store_lr "\n\t" \ + "push {r0-r3}\n\t" \ + "bl " #preface "\n\t" \ + "pop {r0-r3}\n\t" \ + "bl " #name "\n\t" \ + "push {r0-r3}\n\t" \ + "bl " #postface "\n\t" \ + "pop {r0-r3}\n\t" load_lr "\n\t" ::); /** * @brief Macro for "sandwiching" a function call (@p name) in two other calls @@ -98,10 +92,8 @@ * * See @ref __TZ_WRAP_FUNC_RAW for more information. */ -#define __TZ_WRAP_FUNC(preface, name, postface) \ - __TZ_WRAP_FUNC_RAW(preface, name, postface, "push {r4, lr}", \ - "pop {r4, pc}") - +#define __TZ_WRAP_FUNC(preface, name, postface) \ + __TZ_WRAP_FUNC_RAW(preface, name, postface, "push {r4, lr}", "pop {r4, pc}") #ifdef CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS /** @@ -130,10 +122,10 @@ * @param ... The rest of the signature of the function. This must be the same * signature as the corresponding NS entry function. */ -#define TZ_THREAD_SAFE_NONSECURE_ENTRY_FUNC(name, ret, nsc_name, ...) \ - ret __attribute__((naked)) name(__VA_ARGS__) \ - { \ - __TZ_WRAP_FUNC(k_sched_lock, nsc_name, k_sched_unlock); \ +#define TZ_THREAD_SAFE_NONSECURE_ENTRY_FUNC(name, ret, nsc_name, ...) \ + ret __attribute__((naked)) name(__VA_ARGS__) \ + { \ + __TZ_WRAP_FUNC(k_sched_lock, nsc_name, k_sched_unlock); \ } #endif /* CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS */ diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 35a480a24fde..21327f62c1ba 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -126,6 +126,7 @@ config PRIVILEGED_STACK_SIZE default 4096 config KOBJECT_TEXT_AREA + default 1024 if UBSAN default 512 if TEST config WAIT_AT_RESET_VECTOR diff --git a/arch/arm64/core/cortex_r/arm_mpu.c b/arch/arm64/core/cortex_r/arm_mpu.c index 2bd6d265c9a9..3053d90cb75f 100644 --- a/arch/arm64/core/cortex_r/arm_mpu.c +++ b/arch/arm64/core/cortex_r/arm_mpu.c @@ -196,7 +196,7 @@ static ALWAYS_INLINE void region_init(const uint32_t index, .limit = (reg).dt_addr + (reg).dt_size, \ .attr = _ATTR, \ } - +#ifdef CONFIG_MEM_ATTR /* This internal function programs the MPU regions defined in the DT when using * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property. */ @@ -247,7 +247,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index) return 0; } - +#endif /* CONFIG_MEM_ATTR */ /* * @brief MPU default configuration * @@ -303,13 +303,13 @@ FUNC_NO_STACK_PROTECTOR void z_arm64_mm_init(bool is_primary_core) /* Update the number of programmed MPU regions. */ tmp_static_num = mpu_config.num_regions; - +#ifdef CONFIG_MEM_ATTR /* DT-defined MPU regions. */ if (mpu_configure_regions_from_dt(&tmp_static_num) == -EINVAL) { __ASSERT(0, "Failed to allocate MPU regions from DT\n"); return; } - +#endif arm_core_mpu_enable(); if (!is_primary_core) { diff --git a/arch/arm64/core/elf.c b/arch/arm64/core/elf.c index 66e9f21fc06f..c60c99fad46a 100644 --- a/arch/arm64/core/elf.c +++ b/arch/arm64/core/elf.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -430,12 +431,32 @@ static int imm_reloc_handler(elf_rela_t *rel, elf_word reloc_type, uintptr_t loc * @retval -ENOTSUP Unsupported relocation * @retval -ENOEXEC Invalid relocation */ -int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name, - uintptr_t load_bias) +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) { int ret = 0; bool overflow_check = true; elf_word reloc_type = ELF_R_TYPE(rel->r_info); + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } switch (reloc_type) { case R_ARM_NONE: diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index 7955b6f7d6d1..cb5f485c0d52 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -17,9 +17,11 @@ #include #include #include +#include #include #include #include +#include #include "paging.h" @@ -201,6 +203,37 @@ static void esf_dump(const struct arch_esf *esf) #ifdef CONFIG_ARCH_STACKWALK typedef bool (*arm64_stacktrace_cb)(void *cookie, unsigned long addr, void *fp); +static bool is_address_mapped(uint64_t *addr) +{ + uintptr_t *phys = NULL; + + if (*addr == 0U) { + return false; + } + + /* Check alignment. */ + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { + return false; + } + + return !arch_page_phys_get((void *) addr, phys); +} + +static bool is_valid_jump_address(uint64_t *addr) +{ + if (*addr == 0U) { + return false; + } + + /* Check alignment. */ + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { + return false; + } + + return ((*addr >= (uint64_t)__text_region_start) && + (*addr <= (uint64_t)(__text_region_end))); +} + static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct arch_esf *esf, int max_frames) { @@ -234,7 +267,12 @@ static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct a } for (int i = 0; (fp != NULL) && (i < max_frames); i++) { + if (!is_address_mapped(fp)) + break; lr = fp[1]; + if (!is_valid_jump_address(&lr)) { + break; + } if (!cb(cookie, lr, fp)) { break; } @@ -414,8 +452,6 @@ void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf) #endif /* CONFIG_EXCEPTION_DEBUG */ z_fatal_error(reason, esf); - - CODE_UNREACHABLE; } /** diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S index a01139ad7009..235156f9a1c8 100644 --- a/arch/arm64/core/reset.S +++ b/arch/arm64/core/reset.S @@ -58,9 +58,10 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c) b out #endif /* CONFIG_ARMV8_R */ 2: - /* Disable alignment fault checking */ + /* Disable alignment fault checking, disable D-Cache, I-Cache, MMU for safety */ mrs x0, sctlr_el2 - bic x0, x0, SCTLR_A_BIT + mov x1, #(SCTLR_A_BIT | SCTLR_C_BIT | SCTLR_M_BIT | SCTLR_I_BIT) + bic x0, x0, x1 msr sctlr_el2, x0 isb diff --git a/arch/arm64/core/switch.S b/arch/arm64/core/switch.S index 333b8f0b21e3..06a95d37b7a0 100644 --- a/arch/arm64/core/switch.S +++ b/arch/arm64/core/switch.S @@ -74,6 +74,13 @@ SECTION_FUNC(TEXT, z_arm64_context_switch) ldp x0, x1, [sp], #16 #endif +#ifdef CONFIG_SMP + /* Write barrier: ensure all preceding writes are executed + * before writing the switch handle + */ + dmb sy +#endif + /* save old thread into switch handle which is required by * z_sched_switch_spin() */ diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index 18f49945eda4..c48672a5f076 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -30,7 +30,7 @@ * privileged portion of the user stack without touching SP_EL0. This portion * is marked as not user accessible in the MMU/MPU. * - * - a stack guard region will be added bellow the kernel stack when + * - a stack guard region will be added below the kernel stack when * ARM64_STACK_PROTECTION is enabled. In this case, SP_EL0 will always point * to the safe exception stack in the kernel space. For the kernel thread, * SP_EL0 will not change always pointing to safe exception stack. For the diff --git a/arch/arm64/core/vector_table.S b/arch/arm64/core/vector_table.S index 632304b70299..1c2f4218ff1a 100644 --- a/arch/arm64/core/vector_table.S +++ b/arch/arm64/core/vector_table.S @@ -63,7 +63,7 @@ _ASM_FILE_PROLOGUE stp x12, x13, [sp, ___esf_t_x12_x13_OFFSET] stp x14, x15, [sp, ___esf_t_x14_x15_OFFSET] #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK - /* The expection from el1 does not need to save x16, x17, x18 and lr */ + /* The exception from el1 does not need to save x16, x17, x18 and lr */ .if \el == el0 #endif stp x16, x17, [sp, ___esf_t_x16_x17_OFFSET] diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index e79b7cd0abfa..6f84bb963512 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -56,12 +56,21 @@ zephyr_linker_sources_ifdef(CONFIG_GEN_IRQ_VECTOR_TABLE ) if(CONFIG_GEN_ISR_TABLES) - zephyr_linker_section(NAME .intList VMA IDT_LIST LMA IDT_LIST NOINPUT PASS NOT LINKER_ZEPHYR_FINAL) - zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST) - zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList") - - zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".irq_info" PASS LINKER_ZEPHYR_FINAL) - zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".intList" PASS LINKER_ZEPHYR_FINAL) + # IAR Toolchain is having problems with discarding .intList + # This will always keep .intList in a harmless location + # until we can implement a proper DISCARD. + if(ZEPHYR_TOOLCHAIN_VARIANT STREQUAL "iar") + zephyr_linker_section(NAME .intList GROUP RODATA_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList") + else() + zephyr_linker_section(NAME .intList VMA IDT_LIST LMA IDT_LIST NOINPUT PASS NOT LINKER_ZEPHYR_FINAL) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList") + + zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".irq_info" PASS LINKER_ZEPHYR_FINAL) + zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".intList" PASS LINKER_ZEPHYR_FINAL) + endif() endif() zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld index a4e500e8b17b..749e88c9aed6 100644 --- a/arch/common/nocache.ld +++ b/arch/common/nocache.ld @@ -8,7 +8,7 @@ /* Copied from linker.ld */ /* Non-cached region of RAM */ -SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) +SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,,) { #if defined(CONFIG_MMU) MMU_ALIGN; @@ -27,5 +27,6 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) MPU_ALIGN(_nocache_ram_size); #endif _nocache_ram_end = .; -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) _nocache_ram_size = _nocache_ram_end - _nocache_ram_start; +_nocache_load_start = LOADADDR(_NOCACHE_SECTION_NAME); diff --git a/arch/nios2/CMakeLists.txt b/arch/nios2/CMakeLists.txt deleted file mode 100644 index f0424b169b6f..000000000000 --- a/arch/nios2/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_GP_NONE) -set(gpopt none) -elseif(CONFIG_GP_LOCAL) -set(gpopt local) -elseif(CONFIG_GP_GLOBAL) -set(gpopt global) -elseif(CONFIG_GP_ALL_DATA) -set(gpopt data) -endif() - -# Set Global Pointer option based on Kconfig. -zephyr_cc_option(-mgpopt=${gpopt}) - -# TODO Find a way to pull this out of system.h somehow -# instead of having Kconfig for it - -if(CONFIG_HAS_MUL_INSTRUCTION) -zephyr_cc_option(-mhw-mul) -else() -zephyr_cc_option(-mno-hw-mul) -endif() - -if(CONFIG_HAS_MULX_INSTRUCTION) -zephyr_cc_option(-mhw-mulx) -else() -zephyr_cc_option(-mno-hw-mulx) -endif() - -if(CONFIG_HAS_DIV_INSTRUCTION) -zephyr_cc_option(-mhw-div) -else() -zephyr_cc_option(-mno-hw-div) -endif() - -add_subdirectory(core) diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig deleted file mode 100644 index 6e147119421a..000000000000 --- a/arch/nios2/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -menu "Nios II Options" - depends on NIOS2 - -config ARCH - string - default "nios2" - -menu "Nios II Gen 2 Processor Options" - -config CPU_NIOS2_GEN2 - bool - default y - select BUILD_OUTPUT_HEX - select ARCH_HAS_EXTRA_EXCEPTION_INFO - help - This option signifies the use of a Nios II Gen 2 CPU - -endmenu - -menu "Nios II Family Options" - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config NUM_IRQS - int - default 32 - -config HAS_MUL_INSTRUCTION - bool - -config HAS_DIV_INSTRUCTION - bool - -config HAS_MULX_INSTRUCTION - bool - -config INCLUDE_RESET_VECTOR - bool "Include Reset vector" - default y - help - Include the reset vector stub, which enables instruction/data caches - and then jumps to __start. This code is typically located at the very - beginning of flash memory. You may need to omit this if using the - nios2-download tool since it refuses to load data anywhere other than - RAM. - -config EXTRA_EXCEPTION_INFO - bool "Extra exception debug information" - help - Have exceptions print additional useful debugging information in - human-readable form, at the expense of code size. For example, - the cause code for an exception will be supplemented by a string - describing what that cause code means. - -choice - prompt "Global Pointer options" - default GP_GLOBAL - -config GP_NONE - bool "No global pointer" - help - Do not use global pointer relative offsets at all - -config GP_LOCAL - bool "Local data global pointer references" - help - Use global pointer relative offsets for small globals declared in the - same C file as the code that uses it. - -config GP_GLOBAL - bool "Global data global pointer references" - help - Use global pointer relative offsets for small globals declared - anywhere in the executable. Note that if any small globals that are put - in alternate sections they must be declared - in headers with proper __attribute__((section)) or the linker will - error out. - -config GP_ALL_DATA - bool "All data global pointer references" - help - Use GP relative access for all data in the program, not just - small data. Use this if your board has 64K or less of RAM. - -endchoice - -endmenu - -endmenu diff --git a/arch/nios2/core/CMakeLists.txt b/arch/nios2/core/CMakeLists.txt deleted file mode 100644 index 84fa0b49b3f3..000000000000 --- a/arch/nios2/core/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - thread.c - cpu_idle.c - fatal.c - irq_manage.c - swap.S - prep_c.c - reset.S - cache.c - exception.S - crt0.S - ) - -zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) -zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) diff --git a/arch/nios2/core/cache.c b/arch/nios2/core/cache.c deleted file mode 100644 index c13c43c7188d..000000000000 --- a/arch/nios2/core/cache.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - - -/** - * Flush the entire instruction cache and pipeline. - * - * You will need to call this function if the application writes new program - * text to memory, such as a boot copier or runtime synthesis of code. If the - * new text was written with instructions that do not bypass cache memories, - * this should immediately be followed by an invocation of - * z_nios2_dcache_flush_all() so that cached instruction data is committed to - * RAM. - * - * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more - * information on cache considerations. - */ -#if ALT_CPU_ICACHE_SIZE > 0 -void z_nios2_icache_flush_all(void) -{ - uint32_t i; - - for (i = 0U; i < ALT_CPU_ICACHE_SIZE; i += ALT_CPU_ICACHE_LINE_SIZE) { - z_nios2_icache_flush(i); - } - - /* Get rid of any stale instructions in the pipeline */ - z_nios2_pipeline_flush(); -} -#endif - -/** - * Flush the entire data cache. - * - * This will be typically needed after writing new program text to memory - * after flushing the instruction cache. - * - * The Nios II does not support hardware cache coherency for multi-master - * or multi-processor systems and software coherency must be implemented - * when communicating with shared memory. If support for this is introduced - * in Zephyr additional APIs for flushing ranges of the data cache will need - * to be implemented. - * - * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more - * information on cache considerations. - */ -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_all(void) -{ - uint32_t i; - - for (i = 0U; i < ALT_CPU_DCACHE_SIZE; i += ALT_CPU_DCACHE_LINE_SIZE) { - z_nios2_dcache_flush(i); - } -} -#endif - -/* - * z_nios2_dcache_flush_no_writeback() is called to flush the data cache for a - * memory region of length "len" bytes, starting at address "start". - * - * Any dirty lines in the data cache are NOT written back to memory. - * Make sure you really want this behavior. If you aren't 100% sure, - * use the z_nios2_dcache_flush() routine instead. - */ -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len) -{ - uint8_t *i; - uint8_t *end = ((char *) start) + len; - - for (i = start; i < end; i += ALT_CPU_DCACHE_LINE_SIZE) { - __asm__ volatile ("initda (%0)" :: "r" (i)); - } - - /* - * For an unaligned flush request, we've got one more line left. - * Note that this is dependent on ALT_CPU_DCACHE_LINE_SIZE to be a - * multiple of 2 (which it always is). - */ - - if (((uint32_t) start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) { - __asm__ volatile ("initda (%0)" :: "r" (i)); - } -} -#endif diff --git a/arch/nios2/core/cpu_idle.c b/arch/nios2/core/cpu_idle.c deleted file mode 100644 index b201ecfa84ea..000000000000 --- a/arch/nios2/core/cpu_idle.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE -void arch_cpu_idle(void) -{ - /* Do nothing but unconditionally unlock interrupts and return to the - * caller. This CPU does not have any kind of power saving instruction. - */ - irq_unlock(NIOS2_STATUS_PIE_MSK); -} -#endif - -#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE -void arch_cpu_atomic_idle(unsigned int key) -{ - /* Do nothing but restore IRQ state. This CPU does not have any - * kind of power saving instruction. - */ - irq_unlock(key); -} -#endif diff --git a/arch/nios2/core/crt0.S b/arch/nios2/core/crt0.S deleted file mode 100644 index 2f708bf26f4a..000000000000 --- a/arch/nios2/core/crt0.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/* exports */ -GTEXT(__start) -GTEXT(__reset) - -/* imports */ -GTEXT(z_prep_c) -GTEXT(z_interrupt_stacks) - - /* Allow use of r1/at (the assembler temporary register) in this - * code, normally reserved for internal assembler use - */ - .set noat - - -#if CONFIG_INCLUDE_RESET_VECTOR -/* - * Reset vector entry point into the system. Placed into special 'reset' - * section so that the linker puts this at ALT_CPU_RESET_ADDR defined in - * system.h - * - * This code can be at most 0x20 bytes, since the exception vector for Nios II - * is usually configured to be 0x20 past the reset vector. - */ -SECTION_FUNC(reset, __reset) - -#if ALT_CPU_ICACHE_SIZE > 0 - /* Aside from the instruction cache line associated with the reset - * vector, the contents of the cache memories are indeterminate after - * reset. To ensure cache coherency after reset, the reset handler - * located at the reset vector must immediately initialize the - * instruction cache. Next, either the reset handler or a subsequent - * routine should proceed to initialize the data cache. - * - * The cache memory sizes are *always* a power of 2. - */ -#if ALT_CPU_ICACHE_SIZE > 0x8000 - movhi r2, %hi(ALT_CPU_ICACHE_SIZE) -#else - movui r2, ALT_CPU_ICACHE_SIZE -#endif -0: - /* If ECC present, need to execute initd for each word address - * to ensure ECC parity bits in data RAM get initialized - */ -#ifdef ALT_CPU_ECC_PRESENT - subi r2, r2, 4 -#else - subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE -#endif - initi r2 - bgt r2, zero, 0b -#endif /* ALT_CPU_ICACHE_SIZE > 0 */ - - /* Done all we need to do here, jump to __text_start */ - movhi r1, %hi(__start) - ori r1, r1, %lo(__start) - jmp r1 -#endif /* CONFIG_INCLUDE_RESET_VECTOR */ - -/* Remainder of asm-land initialization code before we can jump into - * the C domain - */ -SECTION_FUNC(TEXT, __start) - - /* TODO if shadow register sets enabled, ensure we are in set 0 - * GH-1821 - */ - - /* Initialize the data cache if booting from bare metal. If - * we're not booting from our reset vector, either by a bootloader - * or JTAG, assume caches already initialized. - */ -#if ALT_CPU_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR) - /* Per documentation data cache size is always a power of two. */ -#if ALT_CPU_DCACHE_SIZE > 0x8000 - movhi r2, %hi(ALT_CPU_DCACHE_SIZE) -#else - movui r2, ALT_CPU_DCACHE_SIZE -#endif -0: - /* If ECC present, need to execute initd for each word address - * to ensure ECC parity bits in data RAM get initialized - */ -#ifdef ALT_CPU_ECC_PRESENT - subi r2, r2, 4 -#else - subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE -#endif - initd 0(r2) - bgt r2, zero, 0b -#endif /* ALT_CPU_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */ - -#ifdef CONFIG_INIT_STACKS - /* Pre-populate all bytes in z_interrupt_stacks with 0xAA - * init.c enforces that the z_interrupt_stacks pointer - * and CONFIG_ISR_STACK_SIZE are a multiple of ARCH_STACK_PTR_ALIGN (4) - */ - movhi r1, %hi(z_interrupt_stacks) - ori r1, r1, %lo(z_interrupt_stacks) - movhi r2, %hi(CONFIG_ISR_STACK_SIZE) - ori r2, r2, %lo(CONFIG_ISR_STACK_SIZE) - /* Put constant 0xaaaaaaaa in r3 */ - movhi r3, 0xaaaa - ori r3, r3, 0xaaaa -1: - /* Loop through the z_interrupt_stacks treating it as an array of - * uint32_t, setting each element to r3 */ - stw r3, (r1) - subi r2, r2, 4 - addi r1, r1, 4 - blt r0, r2, 1b -#endif - - /* Set up the initial stack pointer to the interrupt stack, safe - * to use this as the CPU boots up with interrupts disabled and we - * don't turn them on until much later, when the kernel is on - * the main stack */ - movhi sp, %hi(z_interrupt_stacks) - ori sp, sp, %lo(z_interrupt_stacks) - addi sp, sp, CONFIG_ISR_STACK_SIZE - -#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL) || \ - defined(CONFIG_GP_ALL_DATA) - /* Initialize global pointer with the linker variable we set */ - movhi gp, %hi(_gp) - ori gp, gp, %lo(_gp) -#endif - - /* TODO if shadow register sets enabled, interate through them to set - * up. Need to clear r0, write gp, set the exception stack pointer - * GH-1821 - */ - - /* Jump into C domain. z_prep_c zeroes BSS, copies rw data into RAM, - * and then enters z_cstart */ - call z_prep_c - diff --git a/arch/nios2/core/exception.S b/arch/nios2/core/exception.S deleted file mode 100644 index 8dd7e0b9b9b8..000000000000 --- a/arch/nios2/core/exception.S +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -/* exports */ -GTEXT(_exception) - -/* import */ -GTEXT(z_nios2_fault) -GTEXT(arch_swap) -#ifdef CONFIG_IRQ_OFFLOAD -GTEXT(z_irq_do_offload) -GTEXT(_offload_routine) -#endif - -/* Allows use of r1/at register, otherwise reserved for assembler use */ -.set noat - -/* Placed into special 'exception' section so that the linker can put this code - * at ALT_CPU_EXCEPTION_ADDR defined in system.h - * - * This is the common entry point for processor exceptions and interrupts from - * the Internal Interrupt Controller (IIC). - * - * If the External (EIC) controller is in use, then we will never get here on - * behalf of an interrupt, instead the EIC driver will have set up a vector - * table and the processor will jump directly into the appropriate table - * entry. - */ -SECTION_FUNC(exception.entry, _exception) - /* Reserve thread stack space for saving context */ - subi sp, sp, __struct_arch_esf_SIZEOF - - /* Preserve all caller-saved registers onto the thread's stack */ - stw ra, __struct_arch_esf_ra_OFFSET(sp) - stw r1, __struct_arch_esf_r1_OFFSET(sp) - stw r2, __struct_arch_esf_r2_OFFSET(sp) - stw r3, __struct_arch_esf_r3_OFFSET(sp) - stw r4, __struct_arch_esf_r4_OFFSET(sp) - stw r5, __struct_arch_esf_r5_OFFSET(sp) - stw r6, __struct_arch_esf_r6_OFFSET(sp) - stw r7, __struct_arch_esf_r7_OFFSET(sp) - stw r8, __struct_arch_esf_r8_OFFSET(sp) - stw r9, __struct_arch_esf_r9_OFFSET(sp) - stw r10, __struct_arch_esf_r10_OFFSET(sp) - stw r11, __struct_arch_esf_r11_OFFSET(sp) - stw r12, __struct_arch_esf_r12_OFFSET(sp) - stw r13, __struct_arch_esf_r13_OFFSET(sp) - stw r14, __struct_arch_esf_r14_OFFSET(sp) - stw r15, __struct_arch_esf_r15_OFFSET(sp) - - /* Store value of estatus control register */ - rdctl et, estatus - stw et, __struct_arch_esf_estatus_OFFSET(sp) - - /* ea-4 is the address of the instruction when the exception happened, - * put this in the stack frame as well - */ - addi r15, ea, -4 - stw r15, __struct_arch_esf_instr_OFFSET(sp) - - /* Figure out whether we are here because of an interrupt or an - * exception. If an interrupt, switch stacks and enter IRQ handling - * code. If an exception, remain on current stack and enter exception - * handing code. From the CPU manual, ipending must be nonzero and - * estatis.PIE must be enabled for this to be considered an interrupt. - * - * Stick ipending in r4 since it will be an arg for _enter_irq - */ - rdctl r4, ipending - beq r4, zero, not_interrupt - /* We stashed estatus in et earlier */ - andi r15, et, 1 - beq r15, zero, not_interrupt - -is_interrupt: - /* If we get here, this is an interrupt */ - - /* Grab a reference to _kernel in r10 so we can determine the - * current irq stack pointer - */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - - /* Stash a copy of thread's sp in r12 so that we can put it on the IRQ - * stack - */ - mov r12, sp - - /* Switch to interrupt stack */ - ldw sp, _kernel_offset_to_irq_stack(r10) - - /* Store thread stack pointer onto IRQ stack */ - addi sp, sp, -4 - stw r12, 0(sp) - -on_irq_stack: - - /* Enter C interrupt handling code. Value of ipending will be the - * function parameter since we put it in r4 - */ - call _enter_irq - - /* Interrupt handler finished and the interrupt should be serviced - * now, the appropriate bits in ipending should be cleared */ - - /* Get a reference to _kernel again in r10 */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - -#ifdef CONFIG_PREEMPT_ENABLED - ldw r11, _kernel_offset_to_current(r10) - /* Determine whether the exception of the ISR requires context - * switch - */ - - /* Call into the kernel to see if a scheduling decision is necessary */ - ldw r2, _kernel_offset_to_ready_q_cache(r10) - beq r2, r11, no_reschedule - - /* - * A context reschedule is required: keep the volatile registers of - * the interrupted thread on the context's stack. Utilize - * the existing arch_swap() primitive to save the remaining - * thread's registers (including floating point) and perform - * a switch to the new thread. - */ - - /* We put the thread stack pointer on top of the IRQ stack before - * we switched stacks. Restore it to go back to thread stack - */ - ldw sp, 0(sp) - - /* Argument to Swap() is estatus since that's the state of the - * status register before the exception happened. When coming - * out of the context switch we need this info to restore - * IRQ lock state. We put this value in et earlier. - */ - mov r4, et - - call arch_swap - jmpi _exception_exit -#else - jmpi no_reschedule -#endif /* CONFIG_PREEMPT_ENABLED */ - -not_interrupt: - - /* Since this wasn't an interrupt we're not going to restart the - * faulting instruction. - * - * We earlier put ea - 4 in the stack frame, replace it with just ea - */ - stw ea, __struct_arch_esf_instr_OFFSET(sp) - -#ifdef CONFIG_IRQ_OFFLOAD - /* Check the contents of _offload_routine. If non-NULL, jump into - * the interrupt code anyway. - */ - movhi r10, %hi(_offload_routine) - ori r10, r10, %lo(_offload_routine) - ldw r11, (r10) - bne r11, zero, is_interrupt -#endif - -_exception_enter_fault: - /* If we get here, the exception wasn't in interrupt or an - * invocation of irq_offload(). Let z_nios2_fault() handle it in - * C domain - */ - - mov r4, sp - call z_nios2_fault - jmpi _exception_exit - -no_reschedule: - - /* We put the thread stack pointer on top of the IRQ stack before - * we switched stacks. Restore it to go back to thread stack - */ - ldw sp, 0(sp) - - /* Fall through */ - -_exception_exit: - /* We are on the thread stack. Restore all saved registers - * and return to the interrupted context */ - - /* Return address from the exception */ - ldw ea, __struct_arch_esf_instr_OFFSET(sp) - - /* Restore estatus - * XXX is this right??? */ - ldw r5, __struct_arch_esf_estatus_OFFSET(sp) - wrctl estatus, r5 - - /* Restore caller-saved registers */ - ldw ra, __struct_arch_esf_ra_OFFSET(sp) - ldw r1, __struct_arch_esf_r1_OFFSET(sp) - ldw r2, __struct_arch_esf_r2_OFFSET(sp) - ldw r3, __struct_arch_esf_r3_OFFSET(sp) - ldw r4, __struct_arch_esf_r4_OFFSET(sp) - ldw r5, __struct_arch_esf_r5_OFFSET(sp) - ldw r6, __struct_arch_esf_r6_OFFSET(sp) - ldw r7, __struct_arch_esf_r7_OFFSET(sp) - ldw r8, __struct_arch_esf_r8_OFFSET(sp) - ldw r9, __struct_arch_esf_r9_OFFSET(sp) - ldw r10, __struct_arch_esf_r10_OFFSET(sp) - ldw r11, __struct_arch_esf_r11_OFFSET(sp) - ldw r12, __struct_arch_esf_r12_OFFSET(sp) - ldw r13, __struct_arch_esf_r13_OFFSET(sp) - ldw r14, __struct_arch_esf_r14_OFFSET(sp) - ldw r15, __struct_arch_esf_r15_OFFSET(sp) - - /* Put the stack pointer back where it was when we entered - * exception state - */ - addi sp, sp, __struct_arch_esf_SIZEOF - - /* All done, copy estatus into status and transfer to ea */ - eret diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c deleted file mode 100644 index 3f34c1e8fc7e..000000000000 --- a/arch/nios2/core/fatal.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); - -FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const struct arch_esf *esf) -{ -#if CONFIG_EXCEPTION_DEBUG - if (esf != NULL) { - /* Subtract 4 from EA since we added 4 earlier so that the - * faulting instruction isn't retried. - * - * TODO: Only caller-saved registers get saved upon exception - * entry. We may want to introduce a config option to save and - * dump all registers, at the expense of some stack space. - */ - LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4); - LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x", - esf->r1, esf->r2, esf->r3, esf->r4); - LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x", - esf->r5, esf->r6, esf->r7, esf->r8); - LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x", - esf->r9, esf->r10, esf->r11, esf->r12); - LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x", - esf->r13, esf->r14, esf->r15, esf->ra); - LOG_ERR("estatus: %08x", esf->estatus); - } -#endif /* CONFIG_EXCEPTION_DEBUG */ - - z_fatal_error(reason, esf); - CODE_UNREACHABLE; -} - -#if defined(CONFIG_EXTRA_EXCEPTION_INFO) && \ - (defined(CONFIG_PRINTK) || defined(CONFIG_LOG)) \ - && defined(ALT_CPU_HAS_EXTRA_EXCEPTION_INFO) -static char *cause_str(uint32_t cause_code) -{ - switch (cause_code) { - case 0: - return "reset"; - case 1: - return "processor-only reset request"; - case 2: - return "interrupt"; - case 3: - return "trap"; - case 4: - return "unimplemented instruction"; - case 5: - return "illegal instruction"; - case 6: - return "misaligned data address"; - case 7: - return "misaligned destination address"; - case 8: - return "division error"; - case 9: - return "supervisor-only instruction address"; - case 10: - return "supervisor-only instruction"; - case 11: - return "supervisor-only data address"; - case 12: - return "TLB miss"; - case 13: - return "TLB permission violation (execute)"; - case 14: - return "TLB permission violation (read)"; - case 15: - return "TLB permission violation (write)"; - case 16: - return "MPU region violation (instruction)"; - case 17: - return "MPU region violation (data)"; - case 18: - return "ECC TLB error"; - case 19: - return "ECC fetch error (instruction)"; - case 20: - return "ECC register file error"; - case 21: - return "ECC data error"; - case 22: - return "ECC data cache writeback error"; - case 23: - return "bus instruction fetch error"; - case 24: - return "bus data region violation"; - default: - return "unknown"; - } -} -#endif - -FUNC_NORETURN void z_nios2_fault(const struct arch_esf *esf) -{ -#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) - /* Unfortunately, completely unavailable on Nios II/e cores */ -#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO - uint32_t exc_reg, badaddr_reg, eccftl; - enum nios2_exception_cause cause; - - exc_reg = z_nios2_creg_read(NIOS2_CR_EXCEPTION); - - /* Bit 31 indicates potentially fatal ECC error */ - eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0U; - - /* Bits 2-6 contain the cause code */ - cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK) - >> NIOS2_EXCEPTION_REG_CAUSE_OFST; - - LOG_ERR("Exception cause: %d ECCFTL: 0x%x", cause, eccftl); -#if CONFIG_EXTRA_EXCEPTION_INFO - LOG_ERR("reason: %s", cause_str(cause)); -#endif - if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) { - badaddr_reg = z_nios2_creg_read(NIOS2_CR_BADADDR); - LOG_ERR("Badaddr: 0x%x", badaddr_reg); - } -#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */ -#endif /* CONFIG_PRINTK || CONFIG_LOG */ - - z_nios2_fatal_error(K_ERR_CPU_EXCEPTION, esf); -} - -#ifdef ALT_CPU_HAS_DEBUG_STUB -FUNC_NORETURN void arch_system_halt(unsigned int reason) -{ - ARG_UNUSED(reason); - - z_nios2_break(); - CODE_UNREACHABLE; -} -#endif diff --git a/arch/nios2/core/irq_manage.c b/arch/nios2/core/irq_manage.c deleted file mode 100644 index 6f4b2bdf10cf..000000000000 --- a/arch/nios2/core/irq_manage.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Nios II C-domain interrupt management code for use with Internal - * Interrupt Controller (IIC) - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); - -FUNC_NORETURN void z_irq_spurious(const void *unused) -{ - ARG_UNUSED(unused); - LOG_ERR("Spurious interrupt detected! ipending: %x", - z_nios2_creg_read(NIOS2_CR_IPENDING)); - z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); -} - - -void arch_irq_enable(unsigned int irq) -{ - uint32_t ienable; - unsigned int key; - - key = irq_lock(); - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - ienable |= BIT(irq); - z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); - - irq_unlock(key); -}; - - - -void arch_irq_disable(unsigned int irq) -{ - uint32_t ienable; - unsigned int key; - - key = irq_lock(); - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - ienable &= ~BIT(irq); - z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); - - irq_unlock(key); -}; - -int arch_irq_is_enabled(unsigned int irq) -{ - uint32_t ienable; - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - return ienable & BIT(irq); -} - -/** - * @brief Interrupt demux function - * - * Given a bitfield of pending interrupts, execute the appropriate handler - * - * @param ipending Bitfield of interrupts - */ -void _enter_irq(uint32_t ipending) -{ - int index; - - _kernel.cpus[0].nested++; - -#ifdef CONFIG_IRQ_OFFLOAD - z_irq_do_offload(); -#endif - - while (ipending) { - struct _isr_table_entry *ite; - -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_enter(); -#endif - - index = find_lsb_set(ipending) - 1; - ipending &= ~BIT(index); - - ite = &_sw_isr_table[index]; - - ite->isr(ite->arg); -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_exit(); -#endif - } - - _kernel.cpus[0].nested--; -#ifdef CONFIG_STACK_SENTINEL - z_check_stack_sentinel(); -#endif -} - -#ifdef CONFIG_DYNAMIC_INTERRUPTS -int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), - const void *parameter, uint32_t flags) -{ - ARG_UNUSED(flags); - ARG_UNUSED(priority); - - z_isr_install(irq, routine, parameter); - return irq; -} -#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/nios2/core/irq_offload.c b/arch/nios2/core/irq_offload.c deleted file mode 100644 index 0c918896be95..000000000000 --- a/arch/nios2/core/irq_offload.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -volatile irq_offload_routine_t _offload_routine; -static volatile const void *offload_param; - -/* Called by _enter_irq if it was passed 0 for ipending. - * Just in case the offload routine itself generates an unhandled - * exception, clear the offload_routine global before executing. - */ -void z_irq_do_offload(void) -{ - irq_offload_routine_t tmp; - - if (!_offload_routine) { - return; - } - - tmp = _offload_routine; - _offload_routine = NULL; - - tmp((const void *)offload_param); -} - -void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) -{ - unsigned int key; - - key = irq_lock(); - _offload_routine = routine; - offload_param = parameter; - - __asm__ volatile ("trap"); - - irq_unlock(key); -} - -void arch_irq_offload_init(void) -{ -} diff --git a/arch/nios2/core/offsets/offsets.c b/arch/nios2/core/offsets/offsets.c deleted file mode 100644 index 9d381d87446c..000000000000 --- a/arch/nios2/core/offsets/offsets.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Nios II kernel structure member offset definition file - * - * This module is responsible for the generation of the absolute symbols whose - * value represents the member offsets for various Nios II kernel - * structures. - * - * All of the absolute symbols defined by this module will be present in the - * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms - * symbol). - * - * INTERNAL - * It is NOT necessary to define the offset for every member of a structure. - * Typically, only those members that are accessed by assembly language routines - * are defined; however, it doesn't hurt to define all fields for the sake of - * completeness. - */ - - -#include -#include -#include -#include - -/* struct coop member offsets */ -GEN_OFFSET_SYM(_callee_saved_t, r16); -GEN_OFFSET_SYM(_callee_saved_t, r17); -GEN_OFFSET_SYM(_callee_saved_t, r18); -GEN_OFFSET_SYM(_callee_saved_t, r19); -GEN_OFFSET_SYM(_callee_saved_t, r20); -GEN_OFFSET_SYM(_callee_saved_t, r21); -GEN_OFFSET_SYM(_callee_saved_t, r22); -GEN_OFFSET_SYM(_callee_saved_t, r23); -GEN_OFFSET_SYM(_callee_saved_t, r28); -GEN_OFFSET_SYM(_callee_saved_t, ra); -GEN_OFFSET_SYM(_callee_saved_t, sp); -GEN_OFFSET_SYM(_callee_saved_t, key); -GEN_OFFSET_SYM(_callee_saved_t, retval); - -GEN_OFFSET_STRUCT(arch_esf, ra); -GEN_OFFSET_STRUCT(arch_esf, r1); -GEN_OFFSET_STRUCT(arch_esf, r2); -GEN_OFFSET_STRUCT(arch_esf, r3); -GEN_OFFSET_STRUCT(arch_esf, r4); -GEN_OFFSET_STRUCT(arch_esf, r5); -GEN_OFFSET_STRUCT(arch_esf, r6); -GEN_OFFSET_STRUCT(arch_esf, r7); -GEN_OFFSET_STRUCT(arch_esf, r8); -GEN_OFFSET_STRUCT(arch_esf, r9); -GEN_OFFSET_STRUCT(arch_esf, r10); -GEN_OFFSET_STRUCT(arch_esf, r11); -GEN_OFFSET_STRUCT(arch_esf, r12); -GEN_OFFSET_STRUCT(arch_esf, r13); -GEN_OFFSET_STRUCT(arch_esf, r14); -GEN_OFFSET_STRUCT(arch_esf, r15); -GEN_OFFSET_STRUCT(arch_esf, estatus); -GEN_OFFSET_STRUCT(arch_esf, instr); -GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); - -GEN_ABS_SYM_END diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c deleted file mode 100644 index c59962059568..000000000000 --- a/arch/nios2/core/prep_c.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Full C support initialization - * - * - * Initialization of full C support: zero the .bss, copy the .data if XIP, - * call z_cstart(). - * - * Stack is available in this module, but not the global data/bss until their - * initialization is performed. - */ - -#include -#include -#include -#include -#include -#include -#include - -/** - * @brief Prepare to and run C code - * - * This routine prepares for the execution of and runs C code. - */ - -void z_prep_c(void) -{ -#if defined(CONFIG_SOC_PREP_HOOK) - soc_prep_hook(); -#endif - - z_bss_zero(); - z_data_copy(); - /* In most XIP scenarios we copy the exception code into RAM, so need - * to flush instruction cache. - */ -#ifdef CONFIG_XIP - z_nios2_icache_flush_all(); -#if ALT_CPU_ICACHE_SIZE > 0 - /* Only need to flush the data cache here if there actually is an - * instruction cache, so that the cached instruction data written is - * actually committed. - */ - z_nios2_dcache_flush_all(); -#endif -#endif -#if CONFIG_ARCH_CACHE - arch_cache_init(); -#endif - z_cstart(); - CODE_UNREACHABLE; -} diff --git a/arch/nios2/core/reset.S b/arch/nios2/core/reset.S deleted file mode 100644 index 6ec3ff3044dd..000000000000 --- a/arch/nios2/core/reset.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -GTEXT(__start) - diff --git a/arch/nios2/core/swap.S b/arch/nios2/core/swap.S deleted file mode 100644 index fa1cd597bc46..000000000000 --- a/arch/nios2/core/swap.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -/* exports */ -GTEXT(arch_swap) -GTEXT(z_thread_entry_wrapper) - -/* imports */ -GTEXT(_k_neg_eagain) - -/* unsigned int arch_swap(unsigned int key) - * - * Always called with interrupts locked - */ -SECTION_FUNC(exception.other, arch_swap) - -#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) - /* Need to preserve r4 as it has the function argument. */ - addi sp, sp, -12 - stw ra, 8(sp) - stw fp, 4(sp) - stw r4, 0(sp) - - call z_thread_mark_switched_out - - ldw r4, 0(sp) - ldw fp, 4(sp) - ldw ra, 8(sp) - addi sp, sp, 12 -#endif - - /* Get a reference to _kernel in r10 */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - - /* Get the pointer to kernel->current */ - ldw r11, _kernel_offset_to_current(r10) - - /* Store all the callee saved registers. We either got here via - * an exception or from a cooperative invocation of arch_swap() from C - * domain, so all the caller-saved registers have already been - * saved by the exception asm or the calling C code already. - */ - stw r16, _thread_offset_to_r16(r11) - stw r17, _thread_offset_to_r17(r11) - stw r18, _thread_offset_to_r18(r11) - stw r19, _thread_offset_to_r19(r11) - stw r20, _thread_offset_to_r20(r11) - stw r21, _thread_offset_to_r21(r11) - stw r22, _thread_offset_to_r22(r11) - stw r23, _thread_offset_to_r23(r11) - stw r28, _thread_offset_to_r28(r11) - stw ra, _thread_offset_to_ra(r11) - stw sp, _thread_offset_to_sp(r11) - - /* r4 has the 'key' argument which is the result of irq_lock() - * before this was called - */ - stw r4, _thread_offset_to_key(r11) - - /* Populate default return value */ - movhi r5, %hi(_k_neg_eagain) - ori r5, r5, %lo(_k_neg_eagain) - ldw r4, (r5) - stw r4, _thread_offset_to_retval(r11) - - /* get cached thread to run */ - ldw r2, _kernel_offset_to_ready_q_cache(r10) - - /* At this point r2 points to the next thread to be swapped in */ - - /* the thread to be swapped in is now the current thread */ - stw r2, _kernel_offset_to_current(r10) - - /* Restore callee-saved registers and switch to the incoming - * thread's stack - */ - ldw r16, _thread_offset_to_r16(r2) - ldw r17, _thread_offset_to_r17(r2) - ldw r18, _thread_offset_to_r18(r2) - ldw r19, _thread_offset_to_r19(r2) - ldw r20, _thread_offset_to_r20(r2) - ldw r21, _thread_offset_to_r21(r2) - ldw r22, _thread_offset_to_r22(r2) - ldw r23, _thread_offset_to_r23(r2) - ldw r28, _thread_offset_to_r28(r2) - ldw ra, _thread_offset_to_ra(r2) - ldw sp, _thread_offset_to_sp(r2) - - /* We need to irq_unlock(current->coopReg.key); - * key was supplied as argument to arch_swap(). Fetch it. - */ - ldw r3, _thread_offset_to_key(r2) - - /* - * Load return value into r2 (return value register). -EAGAIN unless - * someone previously called arch_thread_return_value_set(). Do this - * before we potentially unlock interrupts. - */ - ldw r2, _thread_offset_to_retval(r2) - - /* Now do irq_unlock(current->coopReg.key) */ -#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \ - (defined ALT_CPU_EIC_PRESENT) || \ - (defined ALT_CPU_MMU_PRESENT) || \ - (defined ALT_CPU_MPU_PRESENT) - andi r3, r3, NIOS2_STATUS_PIE_MSK - beq r3, zero, no_unlock - rdctl r3, status - ori r3, r3, NIOS2_STATUS_PIE_MSK - wrctl status, r3 - -no_unlock: -#else - wrctl status, r3 -#endif - -#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) - /* Also need to preserve r2, r3 as return values */ - addi sp, sp, -20 - stw ra, 16(sp) - stw fp, 12(sp) - stw r4, 8(sp) - stw r3, 4(sp) - stw r2, 0(sp) - - call z_thread_mark_switched_in - - ldw r2, 0(sp) - ldw r3, 4(sp) - ldw r4, 8(sp) - ldw fp, 12(sp) - ldw ra, 16(sp) - addi sp, sp, 20 -#endif - ret - - -/* void z_thread_entry_wrapper(void) - */ -SECTION_FUNC(TEXT, z_thread_entry_wrapper) - /* This all corresponds to struct init_stack_frame defined in - * thread.c. We need to take this stuff off the stack and put - * it in the appropriate registers - */ - - /* Can't return from here, just put NULL in ra */ - movi ra, 0 - - /* Calling convention has first 4 arguments in registers r4-r7. */ - ldw r4, 0(sp) - ldw r5, 4(sp) - ldw r6, 8(sp) - ldw r7, 12(sp) - - /* pop all the stuff that we just loaded into registers */ - addi sp, sp, 16 - - call z_thread_entry - diff --git a/arch/nios2/core/thread.c b/arch/nios2/core/thread.c deleted file mode 100644 index c2f674a3fb05..000000000000 --- a/arch/nios2/core/thread.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/* forward declaration to asm function to adjust setup the arguments - * to z_thread_entry() since this arch puts the first four arguments - * in r4-r7 and not on the stack - */ -void z_thread_entry_wrapper(k_thread_entry_t, void *, void *, void *); - -struct init_stack_frame { - /* top of the stack / most recently pushed */ - - /* Used by z_thread_entry_wrapper. pulls these off the stack and - * into argument registers before calling z_thread_entry() - */ - k_thread_entry_t entry_point; - void *arg1; - void *arg2; - void *arg3; - - /* least recently pushed */ -}; - - -void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, - char *stack_ptr, k_thread_entry_t entry, - void *arg1, void *arg2, void *arg3) -{ - struct init_stack_frame *iframe; - - /* Initial stack frame data, stored at the base of the stack */ - iframe = Z_STACK_PTR_TO_FRAME(struct init_stack_frame, stack_ptr); - - /* Setup the initial stack frame */ - iframe->entry_point = entry; - iframe->arg1 = arg1; - iframe->arg2 = arg2; - iframe->arg3 = arg3; - - thread->callee_saved.sp = (uint32_t)iframe; - thread->callee_saved.ra = (uint32_t)z_thread_entry_wrapper; - thread->callee_saved.key = NIOS2_STATUS_PIE_MSK; - /* Leave the rest of thread->callee_saved junk */ -} diff --git a/arch/nios2/core/timing.c b/arch/nios2/core/timing.c deleted file mode 100644 index 80ee73c6f069..000000000000 --- a/arch/nios2/core/timing.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2020 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include "altera_avalon_timer_regs.h" - -#define NIOS2_SUBTRACT_CLOCK_CYCLES(val) \ - ((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) << 16 | \ - (IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) - \ - ((uint32_t)val)) - -#define TIMING_INFO_OS_GET_TIME() \ - (NIOS2_SUBTRACT_CLOCK_CYCLES( \ - ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) \ - << 16) | \ - ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))) - -void arch_timing_init(void) -{ -} - -void arch_timing_start(void) -{ -} - -void arch_timing_stop(void) -{ -} - -timing_t arch_timing_counter_get(void) -{ - IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10); - return TIMING_INFO_OS_GET_TIME(); -} - -uint64_t arch_timing_cycles_get(volatile timing_t *const start, - volatile timing_t *const end) -{ - timing_t start_ = *start; - timing_t end_ = *end; - - if (end_ >= start_) { - return (end_ - start_); - } - return (end_ + NIOS2_SUBTRACT_CLOCK_CYCLES(start_)); -} - -uint64_t arch_timing_freq_get(void) -{ - return sys_clock_hw_cycles_per_sec(); -} - -uint64_t arch_timing_cycles_to_ns(uint64_t cycles) -{ - return k_cyc_to_ns_floor64(cycles); -} - -uint64_t arch_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count) -{ - return arch_timing_cycles_to_ns(cycles) / count; -} - -uint32_t arch_timing_freq_get_mhz(void) -{ - return (uint32_t)(arch_timing_freq_get() / 1000000U); -} diff --git a/arch/nios2/include/kernel_arch_data.h b/arch/nios2/include/kernel_arch_data.h deleted file mode 100644 index 2f1dbdd1f91e..000000000000 --- a/arch/nios2/include/kernel_arch_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Private kernel definitions - * - * This file contains private kernel structures definitions and various - * other definitions for the Nios II processor architecture. - * - * This file is also included by assembly language files which must #define - * _ASMLANGUAGE before including this header file. Note that kernel - * assembly source files obtains structure offset values via "absolute - * symbols" in the offsets.o module. - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ - -#include -#include -#include - -#ifndef _ASMLANGUAGE - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _ASMLANGUAGE */ - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/nios2/include/kernel_arch_func.h b/arch/nios2/include/kernel_arch_func.h deleted file mode 100644 index c325ea49b49b..000000000000 --- a/arch/nios2/include/kernel_arch_func.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Private kernel definitions - * - * This file contains private kernel function/macro definitions and various - * other definitions for the Nios II processor architecture. - * - * This file is also included by assembly language files which must #define - * _ASMLANGUAGE before including this header file. Note that kernel - * assembly source files obtains structure offset values via "absolute - * symbols" in the offsets.o module. - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef _ASMLANGUAGE - -static ALWAYS_INLINE void arch_kernel_init(void) -{ -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK - soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ -} - -static ALWAYS_INLINE void -arch_thread_return_value_set(struct k_thread *thread, unsigned int value) -{ - thread->callee_saved.retval = value; -} - -FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const struct arch_esf *esf); - -static inline bool arch_is_in_isr(void) -{ - return _kernel.cpus[0].nested != 0U; -} - -int arch_swap(unsigned int key); - -#ifdef CONFIG_IRQ_OFFLOAD -void z_irq_do_offload(void); -#endif - -#if ALT_CPU_ICACHE_SIZE > 0 -void z_nios2_icache_flush_all(void); -#else -#define z_nios2_icache_flush_all() do { } while (false) -#endif - -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_all(void); -void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len); -#else -#define z_nios2_dcache_flush_all() do { } while (false) -#define z_nios2_dcache_flush_no_writeback(x, y) do { } while (false) -#endif - -#endif /* _ASMLANGUAGE */ - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/nios2/include/offsets_short_arch.h b/arch/nios2/include/offsets_short_arch.h deleted file mode 100644 index 3b961e1fcb92..000000000000 --- a/arch/nios2/include/offsets_short_arch.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ - -#include - -/* kernel */ - -/* nothing for now */ - -/* end - kernel */ - -/* threads */ - -#define _thread_offset_to_r16 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r16_OFFSET) - -#define _thread_offset_to_r17 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r17_OFFSET) - -#define _thread_offset_to_r18 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r18_OFFSET) - -#define _thread_offset_to_r19 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r19_OFFSET) - -#define _thread_offset_to_r20 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r20_OFFSET) - -#define _thread_offset_to_r21 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r21_OFFSET) - -#define _thread_offset_to_r22 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r22_OFFSET) - -#define _thread_offset_to_r23 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r23_OFFSET) - -#define _thread_offset_to_r28 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r28_OFFSET) - -#define _thread_offset_to_ra \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_ra_OFFSET) - -#define _thread_offset_to_sp \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET) - -#define _thread_offset_to_key \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_key_OFFSET) - -#define _thread_offset_to_retval \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) - -/* end - threads */ - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/posix/CMakeLists.txt b/arch/posix/CMakeLists.txt index 8dfc696bc6d5..21b6bf7f197d 100644 --- a/arch/posix/CMakeLists.txt +++ b/arch/posix/CMakeLists.txt @@ -75,6 +75,10 @@ if (CONFIG_NATIVE_APPLICATION) zephyr_compile_options( -include ${ZEPHYR_BASE}/arch/posix/include/posix_cheats.h ) + # About this -include directive: The reason to do it this way, is because in this + # manner it is transparent to the application. Otherwise posix_cheats.h needs to + # be included in all the applications' files which define main( ), and in any + # app file which uses any of the APIs renamed in that header. elseif (CONFIG_NATIVE_LIBRARY) zephyr_compile_options( -fvisibility=hidden @@ -146,14 +150,6 @@ if (CONFIG_NATIVE_APPLICATION) ) endif() -# About the -include directive: The reason to do it this way, is because in this -# manner it is transparent to the application. Otherwise posix_cheats.h needs to -# be included in all the applications' files which define main( ), and in any -# app file which uses the pthreads like API provided by Zephyr -# ( include/posix/pthread.h / kernel/pthread.c ) [And any future API added to -# Zephyr which will clash with the native POSIX API] . It would also need to -# be included in a few zephyr kernel files. - # # Support for the LLVM Sanitizer toolchain instrumentation frameworks # (supported by current gcc's as well) @@ -199,4 +195,5 @@ if(NOT ${LLVM_SANITIZERS_ARG} STREQUAL "") target_compile_options(native_simulator INTERFACE ${LLVM_SANITIZERS_ARG}) endif() +include(natsim_optional.cmake) add_subdirectory(core) diff --git a/arch/posix/Kconfig b/arch/posix/Kconfig index 1ed79b38976d..f7ed30cf175e 100644 --- a/arch/posix/Kconfig +++ b/arch/posix/Kconfig @@ -3,7 +3,7 @@ # Copyright (c) 2017 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -menu "POSIX (native) Options" +menu "Native (POSIX) Architecture Options" depends on ARCH_POSIX config ARCH @@ -27,7 +27,7 @@ config ARCH_POSIX_LIBFUZZER help Build as an LLVM libfuzzer target. Requires support from the toolchain (currently only clang works, and - only on native_{posix,sim}[//64]), and should normally be used in + only on native_sim[//64]), and should normally be used in concert with some of CONFIG_ASAN/UBSAN/MSAN for validation. The application needs to implement the LLVMFuzzerTestOneInput() entry point, which runs in the host @@ -41,4 +41,6 @@ config ARCH_POSIX_TRAP_ON_FATAL Raise a SIGTRAP signal on fatal error before exiting. This automatically suspends the target if a debugger is attached. +rsource "Kconfig.natsim_optional" + endmenu diff --git a/arch/posix/Kconfig.natsim_optional b/arch/posix/Kconfig.natsim_optional new file mode 100644 index 000000000000..4ec8dcdc4a55 --- /dev/null +++ b/arch/posix/Kconfig.natsim_optional @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config NATIVE_USE_NSI_ERRNO + bool + help + Build the native simulator nsi_errno component with the Zephyr embedded code. + This component allows translating errno values from/to the embedded libC to/from the host libC. diff --git a/arch/posix/core/irq.c b/arch/posix/core/irq.c index a1d3568c154e..eba9cda41d25 100644 --- a/arch/posix/core/irq.c +++ b/arch/posix/core/irq.c @@ -17,6 +17,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) void arch_irq_offload_init(void) { + /* Nothing to be done for this architecture */ } #endif diff --git a/arch/posix/include/posix_cheats.h b/arch/posix/include/posix_cheats.h index d8307df0ef8d..fa62dc2a2aaa 100644 --- a/arch/posix/include/posix_cheats.h +++ b/arch/posix/include/posix_cheats.h @@ -16,8 +16,8 @@ * If you do see a link error telling you that zap_something is undefined, it is * likely that you forgot to select the corresponding Zephyr POSIX API. * - * This header is included automatically when targeting some POSIX ARCH boards - * (for ex. native_posix). + * This header is included automatically when targeting old POSIX ARCH boards + * based on the CONFIG_NATIVE_APPLICATION architecture. * It will be included in _all_ Zephyr and application source files * (it is passed with the option "-include" to the compiler call) * @@ -34,7 +34,7 @@ /* * Normally main() is the main entry point of a C executable. - * When compiling for native_posix, the Zephyr "application" is not the actual + * When compiling using CONFIG_NATIVE_APPLICATION, the Zephyr "application" is not the actual * entry point of the executable but something the Zephyr OS calls during * boot. * Therefore we need to rename this application main something else, so @@ -58,7 +58,7 @@ extern "C" int _posix_zephyr_main(void); /* * The defines below in this header exist only to enable the Zephyr POSIX API * (include/posix/), and applications using it, to be compiled on top of - * native_posix. + * the deprecated CONFIG_NATIVE_APPLICATION targets. * * Without this header, both the Zephyr POSIX API functions and the equivalent * host OS functions would have the same name. This would result in the linker @@ -72,8 +72,8 @@ extern "C" int _posix_zephyr_main(void); * into something which is unlikely to collide with other real functions * (Any unlikely string would have done) * - * If you want to link an external library together with Zephyr code for the - * native_posix target, where that external library calls into the Zephyr + * If you want to link an external library together with Zephyr code for a + * CONFIG_NATIVE_APPLICATION based target, where that external library calls into the Zephyr * POSIX API, you may want to include this header when compiling that library, * or rename the calls to match the ones in the defines below. */ diff --git a/arch/posix/include/posix_core.h b/arch/posix/include/posix_core.h index 983f80a3abd2..8f72a267389b 100644 --- a/arch/posix/include/posix_core.h +++ b/arch/posix/include/posix_core.h @@ -31,10 +31,9 @@ typedef struct { * Note: If more elements are added to this structure, remember to * update ARCH_POSIX_RECOMMENDED_STACK_SIZE in the configuration. * - * Currently there are 4 pointers + 2 ints, on a 32-bit native posix - * implementation this will result in 24 bytes ( 4*4 + 2*4). - * For a 64-bit implementation the recommended stack size will be - * 40 bytes ( 4*8 + 2*4 ). + * Currently there are 4 pointers + 2 ints, on a 32-bit build this will result in 24 bytes + * (4*4 + 2*4). + * For a 64-bit build the recommended stack size will be 40 bytes ( 4*8 + 2*4 ). */ } posix_thread_status_t; diff --git a/arch/posix/natsim_optional.cmake b/arch/posix/natsim_optional.cmake new file mode 100644 index 000000000000..e2f3d5f0eb3a --- /dev/null +++ b/arch/posix/natsim_optional.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Selection of optional components provided by the native simulator + +if(CONFIG_NATIVE_USE_NSI_ERRNO) + zephyr_library() + + zephyr_library_sources(${NSI_DIR}/common/src/nsi_errno.c) +endif() diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 72907a41fee4..7f4f57eb283a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -428,6 +428,7 @@ config MAIN_STACK_SIZE default 2048 if PMP_STACK_GUARD config TEST_EXTRA_STACK_SIZE + default 4096 if CPP_EXCEPTIONS default 1536 config CMSIS_THREAD_MAX_STACK_SIZE diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 7ac915865d15..29fc8cf9225d 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -162,3 +162,11 @@ config RISCV_ISA_EXT_ZBS The Zbs instructions can be used for single-bit instructions that provide a mechanism to set, clear, invert, or extract a single bit in a register. + +config RISCV_ISA_EXT_ZMMUL + bool + help + (Zmmul) - Zmmul Extension for Integer Multiplication + + The Zmmul extension implements the multiplication subset of the M + extension. diff --git a/arch/riscv/core/cpu_idle.c b/arch/riscv/core/cpu_idle.c index 413b911a53e3..6991da409052 100644 --- a/arch/riscv/core/cpu_idle.c +++ b/arch/riscv/core/cpu_idle.c @@ -12,6 +12,7 @@ void arch_cpu_idle(void) { sys_trace_idle(); __asm__ volatile("wfi"); + sys_trace_idle_exit(); irq_unlock(MSTATUS_IEN); } #endif @@ -21,6 +22,7 @@ void arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); __asm__ volatile("wfi"); + sys_trace_idle_exit(); irq_unlock(key); } #endif diff --git a/arch/riscv/core/elf.c b/arch/riscv/core/elf.c index e0630876dd4c..2ae4b50d132b 100644 --- a/arch/riscv/core/elf.c +++ b/arch/riscv/core/elf.c @@ -8,6 +8,9 @@ */ #include #include +#include +#include + #include #include @@ -59,7 +62,133 @@ static inline int riscv_relocation_fits(long long jump_target, long long max_dis return 0; } -static long long last_u_type_jump_target; +static size_t riscv_last_rel_idx; + +/** + * @brief On RISC-V, PC-relative relocations (PCREL_LO12_I, PCREL_LO12_S) do not refer to + * the actual symbol. Instead, they refer to the location of a different instruction in the + * same section, which has a PCREL_HI20 relocation. The relocation offset is then computed based + * on the location and symbol from the HI20 relocation. 20 bits from the offset go into the + * instruction that has the HI20 relocation, and 12 bits go into the PCREL_LO12 instruction. + * + * @param[in] ldr llext loader + * @param[in] ext current extension + * @param[in] pcrel_lo12 the elf relocation structure for the PCREL_LO12I/S relocation. + * @param[in] shdr ELF section header for the relocation + * @param[in] sym ELF symbol for PCREL_LO12I + * @param[out] link_addr_out computed link address + * + */ +static int llext_riscv_find_sym_pcrel(struct llext_loader *ldr, struct llext *ext, + const elf_rela_t *pcrel_lo12, const elf_shdr_t *shdr, + const elf_sym_t *sym, intptr_t *link_addr_out) +{ + int ret; + elf_rela_t candidate; + uintptr_t candidate_loc; + elf_word reloc_type; + elf_sym_t candidate_sym; + uintptr_t link_addr; + const char *symbol_name; + int iteration_start = riscv_last_rel_idx; + bool is_first = true; + const elf_word rel_cnt = shdr->sh_size / shdr->sh_entsize; + const uintptr_t sect_base = (uintptr_t)llext_loaded_sect_ptr(ldr, ext, shdr->sh_info); + bool found_candidate = false; + + if (iteration_start >= rel_cnt) { + /* value left over from a different section */ + iteration_start = 0; + } + + reloc_type = ELF32_R_TYPE(pcrel_lo12->r_info); + + if (reloc_type != R_RISCV_PCREL_LO12_I && reloc_type != R_RISCV_PCREL_LO12_S) { + /* this function does not apply - the symbol is already correct */ + return 0; + } + + for (int i = iteration_start; i != iteration_start || is_first; i++) { + + is_first = false; + + /* get each relocation entry */ + ret = llext_seek(ldr, shdr->sh_offset + i * shdr->sh_entsize); + if (ret != 0) { + return ret; + } + + ret = llext_read(ldr, &candidate, shdr->sh_entsize); + if (ret != 0) { + return ret; + } + + /* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */ + reloc_type = ELF32_R_TYPE(candidate.r_info); + + candidate_loc = sect_base + candidate.r_offset; + + /* + * RISC-V ELF specification: "value" of the symbol for the PCREL_LO12 relocation + * is actually the offset of the PCREL_HI20 relocation instruction from section + * start + */ + if (candidate.r_offset == sym->st_value && reloc_type == R_RISCV_PCREL_HI20) { + found_candidate = true; + + /* + * start here in next iteration + * it is fairly likely (albeit not guaranteed) that we require PCREL_HI20 + * relocations in order + * we can safely write this even if an error occurs after the loop - + * in that case,we can safely abort the execution anyway + */ + riscv_last_rel_idx = i; + + break; + } + + if (i + 1 >= rel_cnt) { + /* wrap around and search in previously processed indices as well */ + i = -1; + } + } + + if (!found_candidate) { + LOG_ERR("Could not find R_RISCV_PCREL_HI20 relocation for " + "R_RISCV_PCREL_LO12 relocation!"); + return -ENOEXEC; + } + + /* we found a match - need to compute the relocation for this instruction */ + /* lower 12 bits go to the PCREL_LO12 relocation */ + + /* get corresponding / "actual" symbol */ + ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset + + ELF_R_SYM(candidate.r_info) * sizeof(elf_sym_t)); + if (ret != 0) { + return ret; + } + + ret = llext_read(ldr, &candidate_sym, sizeof(elf_sym_t)); + if (ret != 0) { + return ret; + } + + symbol_name = llext_symbol_name(ldr, ext, &candidate_sym); + + ret = llext_lookup_symbol(ldr, ext, &link_addr, &candidate, &candidate_sym, + symbol_name, shdr); + + if (ret != 0) { + return ret; + } + + *link_addr_out = (intptr_t)(link_addr + candidate.r_addend - candidate_loc); /* S + A - P */ + + /* found the matching entry */ + return 0; +} /** * @brief RISC-V specific function for relocating partially linked ELF binaries @@ -68,11 +197,32 @@ static long long last_u_type_jump_target; * https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc * */ -int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_base_addr_unsigned, - const char *sym_name, uintptr_t load_bias) +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) { /* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */ elf_word reloc_type = ELF32_R_TYPE(rel->r_info); + const uintptr_t load_bias = (uintptr_t)ext->mem[LLEXT_MEM_TEXT]; + const uintptr_t loc_unsigned = llext_get_reloc_instruction_location(ldr, ext, + shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr_unsigned; + const char *sym_name; + int ret; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr_unsigned, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } /* * The RISC-V specification uses the following symbolic names for the relocations: * @@ -99,7 +249,22 @@ int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_bas long long original_imm8, jump_target; int16_t compressed_imm8; __typeof__(rel->r_addend) target_alignment = 1; - const intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned; + intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned; + + /* + * For HI20/LO12 ("PCREL") relocation pairs, we need a helper function to + * determine the address for the LO12 relocation, as it depends on the + * value in the HI20 relocation. + */ + ret = llext_riscv_find_sym_pcrel(ldr, ext, rel, shdr, &sym, &sym_base_addr); + + if (ret != 0) { + LOG_ERR("Failed to resolve RISC-V PCREL relocation for symbol %s at %p " + "with base address %p load address %p type %" PRIu64, + sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias, + (uint64_t)reloc_type); + return ret; + } LOG_DBG("Relocating symbol %s at %p with base address %p load address %p type %" PRIu64, sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias, @@ -176,43 +341,32 @@ int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_bas UNALIGNED_PUT(modified_operand, loc32); } - last_u_type_jump_target = jump_target; - return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, reloc_type); case R_RISCV_PCREL_LO12_I: - /* need the same jump target as preceding U-type relocation */ - if (last_u_type_jump_target == 0) { - LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type " - "relocation!"); - return -ENOEXEC; - } + /* + * Jump target is resolved in llext_riscv_find_sym_pcrel in llext_link.c + * as it depends on other relocations. + */ modified_operand = UNALIGNED_GET(loc32); - jump_target = last_u_type_jump_target; /* S - P */ - last_u_type_jump_target = 0; - imm8 = jump_target; + imm8 = (int32_t)sym_base_addr; /* already computed */ modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand); modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8); UNALIGNED_PUT(modified_operand, loc32); - return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, - reloc_type); + /* we have checked that this fits with the associated relocation */ break; case R_RISCV_PCREL_LO12_S: - /* need the same jump target as preceding U-type relocation */ - if (last_u_type_jump_target == 0) { - LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type " - "relocation!"); - return -ENOEXEC; - } + /* + * Jump target is resolved in llext_riscv_find_sym_pcrel in llext_link.c + * as it depends on other relocations. + */ modified_operand = UNALIGNED_GET(loc32); - jump_target = last_u_type_jump_target; /* S - P */ - last_u_type_jump_target = 0; - imm8 = jump_target; + imm8 = (int32_t)sym_base_addr; /* already computed */ modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand); modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8); UNALIGNED_PUT(modified_operand, loc32); - return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, - reloc_type); + /* we have checked that this fits with the associated relocation */ + break; case R_RISCV_HI20: jump_target = sym_base_addr + rel->r_addend; /* S + A */ modified_operand = UNALIGNED_GET(loc32); diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index e29c8abd76d6..f6784d282010 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -204,6 +204,7 @@ static bool set_pmp_entry(unsigned int *index_p, uint8_t perm, return ok; } +#ifdef CONFIG_PMP_STACK_GUARD static inline bool set_pmp_mprv_catchall(unsigned int *index_p, unsigned long *pmp_addr, unsigned long *pmp_cfg, unsigned int index_limit) @@ -231,6 +232,7 @@ static inline bool set_pmp_mprv_catchall(unsigned int *index_p, return ok; } +#endif /* CONFIG_PMP_STACK_GUARD */ /** * @brief Write a range of PMP entries to corresponding PMP registers @@ -447,6 +449,7 @@ void z_riscv_pmp_init(void) /** * @Brief Initialize the per-thread PMP register copy with global values. */ +#if (defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)) || defined(CONFIG_USERSPACE) static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr, unsigned long *pmp_cfg, unsigned int index_limit) @@ -466,6 +469,7 @@ static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr, return global_pmp_end_index; } +#endif #ifdef CONFIG_PMP_STACK_GUARD diff --git a/arch/riscv/core/stacktrace.c b/arch/riscv/core/stacktrace.c index 361e152f00ca..74f94d4eb869 100644 --- a/arch/riscv/core/stacktrace.c +++ b/arch/riscv/core/stacktrace.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -90,9 +91,7 @@ static bool in_stack_bound(uintptr_t addr, const struct k_thread *const thread, static inline bool in_text_region(uintptr_t addr) { - extern uintptr_t __text_region_start, __text_region_end; - - return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end); + return (addr >= (uintptr_t)__text_region_start) && (addr < (uintptr_t)__text_region_end); } #ifdef CONFIG_FRAME_POINTER diff --git a/arch/rx/CMakeLists.txt b/arch/rx/CMakeLists.txt new file mode 100644 index 000000000000..f7c57ff76b9b --- /dev/null +++ b/arch/rx/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(core) +set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-rx-le) # needed for e.g. objcopy diff --git a/arch/rx/Kconfig b/arch/rx/Kconfig new file mode 100644 index 000000000000..9e34a16ea099 --- /dev/null +++ b/arch/rx/Kconfig @@ -0,0 +1,74 @@ +# Renesas RX architecture configuration options + +# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +menu "Renesas RX Options" + depends on RX + +config ARCH + string + default "rx" + +config CPU_RXV1 + bool + help + Set if the processor supports the Renesas RXv1 instruction set. + +config CPU_RXV2 + bool + help + Set if the processor supports the Renesas RXv2 instruction set. + +config CPU_RXV3 + bool + help + Set if the processor supports the Renesas RXv3 instruction set. + +config HAS_EXCEPT_VECTOR_TABLE + bool + help + Set if the processor has the exception vector table. + +config XIP + default y + +config NUM_IRQ_PRIO_LEVELS + int "Number of supported interrupt priority levels" + range 1 16 + default 16 + help + Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The + minimum value is 1. The BSP must provide a valid default for proper + operation. + +config NUM_IRQS + int + default 256 + +config GEN_ISR_TABLES + default y + +config GEN_SW_ISR_TABLE + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config GEN_IRQ_START_VECTOR + default 16 + +config DYNAMIC_INTERRUPTS + default y + +config MAIN_STACK_SIZE + default 1024 + +config INITIALIZATION_STACK_SIZE + int "Initialization stack size (in bytes)" + default 512 + help + Stack size for initialization process of kernel (in bytes) + +endmenu diff --git a/arch/rx/core/CMakeLists.txt b/arch/rx/core/CMakeLists.txt new file mode 100644 index 000000000000..5b3e888db6a5 --- /dev/null +++ b/arch/rx/core/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources( + switch.S + cpu_idle.c + prep_c.c + irq_manage.c + reset.S + thread.c + vects.c + isr_exit.S +) + +zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) diff --git a/arch/rx/core/cpu_idle.c b/arch/rx/core/cpu_idle.c new file mode 100644 index 000000000000..a109057f88df --- /dev/null +++ b/arch/rx/core/cpu_idle.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void arch_cpu_idle(void) +{ + sys_trace_idle(); + + /* The assembler instruction "wait" switches the processor to sleep mode, + * which stops program execution until an interrupt is triggered. + * All clocks that are not in a stop state continue operating, including + * the system timer. + * + * Also, "wait" sets the PSW I bit, activating + * interrupts (otherwise, the processor would never return from sleep + * mode). This is consistent with the Zephyr API description, according + * to which "In some architectures, before returning, the function + * unmasks interrupts unconditionally." - this is such an architecture. + */ + __asm__ volatile("wait"); +} + +void arch_cpu_atomic_idle(unsigned int key) +{ + sys_trace_idle(); + + /* The assembler instruction "wait" switches the processor to sleep mode, + * which stops program execution until an interrupt is triggered. + * All clocks that are not in a stop state continue operating, including + * the system timer. + */ + __asm__ volatile("wait"); + + /* "wait" unconditionally unlocks interrupts. To restore the interrupt + * lockout state before calling arch_cpu_atomic_idle, interrupts have + * to be locked after returning from "wait" if irq_lock would NOT have + * unlocked interrupts (i.e. if the key indicates nested interrupt + * locks) + */ + if (key == 0) { + irq_lock(); + } +} diff --git a/arch/rx/core/irq_manage.c b/arch/rx/core/irq_manage.c new file mode 100644 index 000000000000..7bbba8907384 --- /dev/null +++ b/arch/rx/core/irq_manage.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include + +#define IR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IR) +#define IER_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IER) +#define IPR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IPR) + +#define NUM_IRQS_PER_REG 8 +#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) +#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) +#define REG(addr) *((uint8_t *)(addr)) + +/** + * @brief Enable an IRQ by setting the corresponding IEN bit. + * + * Note that this will have no effect for IRQs 0-15 as the + * Renesas rx chip ignores write operations on the corresponding + * Registers + * + * @param irq interrupt to enable (16-255) + */ +void arch_irq_enable(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "trying to enable invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to enable reserved interrupt (%u)", + irq); + + uint32_t key = irq_lock(); + + /* reset interrupt before activating */ + WRITE_BIT(REG(IR_BASE_ADDRESS + irq), 0, false); + WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), true); + irq_unlock(key); +} + +/** + * @brief Disable an IRQ by clearing the corresponding IEN bit. + * + * Note that this will have no effect for IRQs 0-15 as the + * Renesas rx chip ignores write operations on the corresponding + * Registers. + * + * @param irq interrupt to disable (16-255) + */ +void arch_irq_disable(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "trying to disable invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to disable reserved interrupt (%u)", + irq); + + uint32_t key = irq_lock(); + + WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), false); + irq_unlock(key); +} + +/** + * @brief Determine if an IRQ is enabled by reading the corresponding IEN bit. + * + * @param irq interrupt number + * + * @return true if the interrupt is enabled + */ +int arch_irq_is_enabled(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "is_enabled on invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "is_enabled on reserved interrupt (%u)", irq); + + return (REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)) & BIT(BIT_FROM_IRQ(irq))) != 0; +} + +/* + * @brief Spurious interrupt handler + * + * Installed in all dynamic interrupt slots at boot time. Throws an error if + * called. + * + * @return N/A + */ + +void z_irq_spurious(const void *unused) +{ + ARG_UNUSED(unused); + z_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); +} + +/* + * @internal + * + * @brief Set an interrupt's priority + * + * Higher values take priority over lower values. + * + * @return N/A + */ + +void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "irq_priority_set on invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "irq_priority_set on reserved interrupt (%u)", + irq); + __ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS, "invalid priority (%u) for interrupt %u", prio, + irq); + + uint32_t key = irq_lock(); + + if (irq >= 34) { + /* for interrupts >= 34, the IPR is regular */ + REG(IPR_BASE_ADDRESS + irq) = prio; + } else { + switch (irq) { + /* 0-15: no IPR */ + case 16: + /* 17: no IPR */ + case 18: + REG(IPR_BASE_ADDRESS) = prio; + break; + /* 19,20: no IPR */ + case 21: + REG(IPR_BASE_ADDRESS + 1) = prio; + break; + /* 22: no IPR */ + case 23: + REG(IPR_BASE_ADDRESS + 2) = prio; + break; + /* 24,25: no IPR */ + case 26: + case 27: + REG(IPR_BASE_ADDRESS + 3) = prio; + break; + case 28: + REG(IPR_BASE_ADDRESS + 4) = prio; + break; + case 29: + REG(IPR_BASE_ADDRESS + 5) = prio; + break; + case 30: + REG(IPR_BASE_ADDRESS + 6) = prio; + break; + case 31: + REG(IPR_BASE_ADDRESS + 7) = prio; + break; + /* 32,33: no IPR */ + } + } + irq_unlock(key); +} + +#ifdef CONFIG_DYNAMIC_INTERRUPTS +/** + * @brief connect a callback function to an interrupt at runtime + * + * @param irq interrupt number + * @param priority priority of the interrupt + * @param routine routine to call when the interrupt is triggered + * @param parameter parameter to supply to the routine on call + * @param flags flags for the interrupt + * + * @return the interrupt number + */ +int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, + void (*routine)(const void *parameter), const void *parameter, + uint32_t flags) +{ + z_isr_install(irq, routine, parameter); + z_irq_priority_set(irq, priority, flags); + return irq; +} +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/rx/core/irq_offload.c b/arch/rx/core/irq_offload.c new file mode 100644 index 000000000000..9845bb4da871 --- /dev/null +++ b/arch/rx/core/irq_offload.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Software interrupts utility code - Renesas rx architecture implementation. + * + * The code is using the first software interrupt (SWINT) of the RX processor + * should this interrupt ever be used for something else, this has to be + * changed - maybe to the second software interrupt (SWINT2). + */ + +#include +#include +#include + +#define SWINT1_IRQ_LINE 27 +#define SWINT1_PRIO 14 +/* Address of the software interrupt trigger register for SWINT1 */ +#define SWINT_REGISTER_ADDRESS 0x872E0 +#define SWINTR_SWINT *(uint8_t *)(SWINT_REGISTER_ADDRESS) + +static irq_offload_routine_t _offload_routine; +static const void *offload_param; + +void z_irq_do_offload(void) +{ + irq_offload_routine_t tmp; + + if (!_offload_routine) { + return; + } + + tmp = _offload_routine; + _offload_routine = NULL; + + tmp((const void *)offload_param); +} + +static void swi0_handler(void) +{ + z_irq_do_offload(); +} + +void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) +{ + _offload_routine = routine; + offload_param = parameter; + + SWINTR_SWINT = 1; +} + +void arch_irq_offload_init(void) +{ + IRQ_CONNECT(SWINT1_IRQ_LINE, SWINT1_PRIO, swi0_handler, NULL, 0); + irq_enable(SWINT1_IRQ_LINE); +} diff --git a/arch/rx/core/isr_exit.S b/arch/rx/core/isr_exit.S new file mode 100644 index 000000000000..69fcd0482d9a --- /dev/null +++ b/arch/rx/core/isr_exit.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +.list +.section .text +GTEXT(_z_rx_irq_exit) + +_z_rx_irq_exit: + mov #__kernel, r1 ; Load the base address of _kernel into r1 + mov r1, r3 ; Load the base address of _kernel into r1 + + add #___cpu_t_current_OFFSET, r1 ; Add the offset for the 'current' field to r1 + mov [r1], r2 ; Load the value of _kernel.cpus[0].current into r2 + + push r2 ; Save old_thread to the stack + + ; Get the next thread to schedule + mov #0,r1 ; Use r1 to pass NULL since we haven't saved the context yet + bsr _z_get_next_switch_handle ; Call the function + + ; The return value of z_get_next_switch_handle will now be in r1 + ; Restore old_thread from the stack + pop r2 ; Restore old_thread from the stack + + ; Check if a switch is necessary + cmp #0, r1 + bz no_switch ; If new_thread (in r1) is NULL, jump to no_switch + + add #___thread_t_switch_handle_OFFSET, r2 + + ; Call arch_switch to perform the context switch + bsr _z_rx_arch_switch ; r1: new_thread->switch_handle, r2: old_thread->switch_handle + +no_switch: + rts diff --git a/arch/rx/core/offsets/offsets.c b/arch/rx/core/offsets/offsets.c new file mode 100644 index 000000000000..b0ac1b4dd5c1 --- /dev/null +++ b/arch/rx/core/offsets/offsets.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief RX Kernel structure member offset definition file + * + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various structures. + * + * All of the absolute symbols defined by this module will be present in the + * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms + * symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. + */ +#ifndef _RX_OFFSETS_INC_ +#define _RX_OFFSETS_INC_ + +#include +#include +#include +#include + +GEN_ABSOLUTE_SYM(__callee_saved_t_SIZEOF, sizeof(_callee_saved_t)); +GEN_ABSOLUTE_SYM(__thread_arch_t_SIZEOF, sizeof(_thread_arch_t)); + +GEN_ABS_SYM_END + +#endif /* _RX_OFFSETS_INC_ */ diff --git a/arch/rx/core/prep_c.c b/arch/rx/core/prep_c.c new file mode 100644 index 000000000000..09d86d10d363 --- /dev/null +++ b/arch/rx/core/prep_c.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Full C support initialization + * + * + * Initialization of full C support: zero the .bss and call z_cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. + */ + +#include +#include +#include +#include +#include + +K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MAX_NUM_CPUS, + CONFIG_INITIALIZATION_STACK_SIZE); +/** + * @brief Prepare to and run C code + * + * This routine prepares for the execution of and runs C code. + * + * @return N/A + */ +void z_prep_c(void) +{ + z_bss_zero(); + + z_data_copy(); + + z_cstart(); + CODE_UNREACHABLE; +} diff --git a/arch/rx/core/reset.S b/arch/rx/core/reset.S new file mode 100644 index 000000000000..80246fe397e3 --- /dev/null +++ b/arch/rx/core/reset.S @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +.list +.section .text +GTEXT(__start) +__start : + +/* during initialization (before the main thread is started), z_initialization_process_stacks + * is used to do the kernel initialization. + */ + mvtc #(_z_initialization_process_stacks + CONFIG_INITIALIZATION_STACK_SIZE),USP + +/* initialise interrupt stack pointer */ + mvtc #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE),ISP + +/* set exception vector address (_ExceptVectors is defined in vects.c) */ +#if CONFIG_HAS_EXCEPT_VECTOR_TABLE + mvtc #_ExceptVectors, extb +#endif + +/* set interrupt vector address (_rvectors_start is defined in vects.c) */ + mvtc #_rvectors_start, intb + +/* load data section from ROM to RAM */ + + mov #_mdata,r2 /* src ROM address of data section in R2 */ + mov #_data,r1 /* dest start RAM address of data section in R1 */ + mov #_edata,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ +#ifdef __RX_ALLOW_STRING_INSNS__ + smovf /* block copy R3 bytes from R2 to R1 */ +#else + cmp #0, r3 + beq 2f + +1: mov.b [r2+], r5 + mov.b r5, [r1+] + sub #1, r3 + bne 1b +2: +#endif + +/* bss initialisation: zero out bss */ + mov #0,r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b + +#ifdef CONFIG_INIT_STACKS + /* initialize the irq stack (it is located in the bss section) */ + mov #0xaa,r2 /* initialization value 0xaa */ + mov #_z_interrupt_stacks, r1 /* start address */ + mov #CONFIG_ISR_STACK_SIZE, r3 /* stack size */ + sstr.b +#endif + +/* setup PSW - use user stack register and lock interrupts during initialization */ + mvtc #0x20000, psw + +#ifdef CPPAPP + bsr __rx_init +#endif + +/* start user program */ + bsr _z_cstart + bsr _exit + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + /* fall through */ + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + mov #next_inilist,r7 + jsr r7 +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + mov #_rx_run_fini_array,r7 + jsr r7 + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + mov #_rx_run_preinit_array,r7 + jsr r7 + mov #_rx_run_init_array,r7 + jsr r7 + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +/* call to exit*/ +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/arch/rx/core/switch.S b/arch/rx/core/switch.S new file mode 100644 index 000000000000..5894530b3af9 --- /dev/null +++ b/arch/rx/core/switch.S @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +GTEXT(_z_rx_arch_switch) +GTEXT(_switch_isr_wrapper) + +/* void z_rx_arch_switch(void *switch_to, void **switched_from) + * + * @brief switch between threads + * + * @param switch_to (r1) pointer to switch handle of the new thread + * @param switched_from (r2) pointer to pointer to switch handle of the old + * thread + * + * Thread-switching is treated differently depending on whether it is a + * cooperative switch triggered by old thread itself or a preemptive switch + * triggered by an interrupt (in this case the function has been called from an + * ISR). + */ +.section .text._z_rx_arch_switch +.align 4 +_z_rx_arch_switch: + + mvfc psw,r3 + tst #0x130000, r3 /* test if PM, U or I bit are set*/ + bz _z_rx_context_switch_isr /* if none of them are set, this is an isr */ + + mov #_coop_switch_to,r3 + mov r1,[r3] + mov #_coop_switched_from,r3 + mov r2,[r3] + + /* trigger unconditional interrupt dedicated to thread switching. The content of r1 and r2 + * will not change by invoking the interrupt so the parameters switch_to and switched_from + * will be available in _z_rx_context_switch_isr, which has been entered into the vector + * table as ISR for interrupt 1 + */ + int #1 + + /* at this point, r0 points to the entry point, so RTS will enter it */ + rts + +/* void switch_isr_wrapper(void) + * + * @brief isr for interrupt 1 as wrapper for _z_rx_context_switch_isr + * + * _z_rx_context_switch_isr ends in rts, so it does not return from the interrupt context + */ +.section .text._switch_isr_wrapper +.align 4 +_switch_isr_wrapper: + pushm r1-r15 + + /* Save the accumulator. */ + mvfachi r15 /* Accumulator high 32 bits. */ + push r15 + mvfacmi r15 /* Accumulator middle 32 bits. */ + shll #16, r15 /* Shifted left as it is restored to the low order word.*/ + push r15 + + mov #_coop_switch_to,r3 + mov [r3],r1 + mov #_coop_switched_from,r3 + mov [r3],r2 + + bsr _z_rx_context_switch_isr + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + pop r15 + mvtaclo r15 /* Accumulator low 32 bits. */ + pop r15 + mvtachi r15 /* Accumulator high 32 bits. */ + + popm r1-r15 + rte + +/* void z_rx_context_switch_isr(void *switch_to, void **switched_from) + * + * @brief switch between threads in the interrupt context + * + * @param switch_to (r1) pointer to switch handle of the new thread + * @param switched_from (r2) pointer to pointer to switch handle of the old thread + * + * since this is part of an ISR, PSW, PC and general registers of the old thread are already + * stored in the interrupt stack, so copy the corresponding part of the interrupt stack to the + * stack of the interrupted thread + */ +_z_rx_context_switch_isr: + + /* store arguments switch_to and switched_from to registers r4 and r5 as + * registers r2 and r3 are needed for the smovf operation */ + mov r1,r4 + mov r2,r5 + + /* set r2 (smovb source address) to the beginning of the interrupt stack */ + mov #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)-1,r2 + + mvfc usp,r1 /* set r1 (smovb dest) to USP */ + + sub #1,r1 /* correct by one byte to use smovb compared to push/pop */ + + /* set r3 to number of bytes to move + * Accumulator 64bit (4byte * 2) + * 15*4 byte for 15 general registers + * + PSW (4 byte) + * + PC (4 byte) + */ + mov #76,r3 + smovb /* block copy from interrupt stack to old thread stack */ + + add #1,r1 /* smovb leaves r1 pointing 1 byte before the stack */ + add #1,r2 /* same with r2 */ + + mov r1,[r5] /* store stack pointer of old thread in *switched_from */ + + mov r2,r1 /* set r1 (smovf dest) to the beginning of the interrupt stack */ + + mov r4,r2 /* set r2 (smovf source) to the sp of the new thread*/ + mov #76,r3 /* set r3 to number of bytes to move */ + + smovf /* block copy from new thread stack to interrupt stack */ + + mvtc r2,usp /* set USP to the new thread stack */ + +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + bsr _z_thread_mark_switched_in +#endif + + rts diff --git a/arch/rx/core/thread.c b/arch/rx/core/thread.c new file mode 100644 index 000000000000..88670bf75dac --- /dev/null +++ b/arch/rx/core/thread.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +/* variables to store the arguments of z_rx_context_switch_isr() (zephyr\arch\rx\core\switch.S) + * when performing a cooperative thread switch. In that case, z_rx_context_switch_isr() triggerss + * unmaskable interrupt 1 to actually perform the switch. The ISR to interrupt 1 + * (switch_isr_wrapper()) reads the arguments from these variables. + */ +void *coop_switch_to; +void **coop_switched_from; + +void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, + k_thread_entry_t entry, void *arg1, void *arg2, void *arg3) +{ + struct arch_esf *iframe; + + iframe = Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr); + + /* initial value for the PSW (bits U and I are set) */ + iframe->psw = 0x30000; + /* the initial entry point is the function z_thread_entry */ + iframe->entry_point = (uint32_t)z_thread_entry; + /* arguments for the call of z_thread_entry (to be written to r1-r4) */ + iframe->r1 = (uint32_t)entry; + iframe->r2 = (uint32_t)arg1; + iframe->r3 = (uint32_t)arg2; + iframe->r4 = (uint32_t)arg3; + /* for debugging: */ + iframe->r5 = 5; + iframe->r6 = 6; + iframe->r7 = 7; + iframe->r8 = 8; + iframe->r9 = 9; + iframe->r10 = 10; + iframe->r11 = 11; + iframe->r12 = 12; + iframe->r13 = 13; + iframe->r14 = 14; + iframe->r15 = 15; + iframe->acc_l = 16; + iframe->acc_h = 17; + + thread->switch_handle = (void *)iframe; +} diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c new file mode 100644 index 000000000000..836e9d3adb2f --- /dev/null +++ b/arch/rx/core/vects.c @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +typedef void (*fp)(void); +extern void _start(void); +extern void z_rx_irq_exit(void); + +/* this is mainly to give Visual Studio Code peace of mind */ +#ifndef CONFIG_GEN_IRQ_START_VECTOR +#define CONFIG_GEN_IRQ_START_VECTOR 0 +#endif + +#define EXVECT_SECT __attribute__((section(".exvectors"))) +#define RVECT_SECT __attribute__((section(".rvectors"))) +#define FVECT_SECT __attribute__((section(".fvectors"))) + +#define __ISR__ __attribute__((interrupt, naked)) + +static ALWAYS_INLINE void REGISTER_SAVE(void) +{ + __asm volatile( + /* Save the Registers to ISP at the top of ISR. */ + /* This code is relate on arch_new_thread() at thread.c */ + /* You should store the registers at the same registers arch_new_thread() */ + /* except PC and PSW. */ + "PUSHM R1-R15\n" + + "MVFACHI R15\n" + "PUSH.L R15\n" + "MVFACMI R15\n" + "SHLL #16, R15\n" + "PUSH.L R15\n"); +} + +static ALWAYS_INLINE void REGISTER_RESTORE_EXIT(void) +{ + __asm volatile( + /* Restore the registers and do the RTE at the End of ISR. */ + "POP R15\n" + "MVTACLO R15\n" + "POP R15\n" + "MVTACHI R15\n" + + "POPM R1-R15\n" + "RTE\n"); +} + +/* Privileged instruction execption */ +static void __ISR__ INT_Excep_SuperVisorInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Access exception */ +static void __ISR__ INT_Excep_AccessInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Undefined instruction exception */ +static void __ISR__ INT_Excep_UndefinedInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* floating point exception */ +static void __ISR__ INT_Excep_FloatingPoint(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Non-maskable interrupt */ +static void __ISR__ INT_NonMaskableInterrupt(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* dummy function */ +static void __ISR__ Dummy(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/** + * @brief select Zephyr ISR and argument from software ISR table and call + * function + * + * @param irq interrupt to handle + */ +static ALWAYS_INLINE void handle_interrupt(uint8_t irq) +{ + ISR_DIRECT_HEADER(); + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + ISR_DIRECT_FOOTER(1); +} + +/** + * @brief isr for reserved interrupts (0-15) that are not handled through + * the zephyr sw isr table + */ +static void __ISR__ reserved_isr(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* wrapper for z_rx_context_switch_isr, defined in switch.S */ +extern void __ISR__ switch_isr_wrapper(void); + +/* this macro is used to define "demuxing" ISRs for all interrupts that are + * handled through Zephyr's software isr table. + */ + +#define INT_DEMUX(irq) \ + static __attribute__((interrupt, naked)) void int_demux_##irq(void) \ + { \ + REGISTER_SAVE(); \ + handle_interrupt(irq - CONFIG_GEN_IRQ_START_VECTOR); \ + REGISTER_RESTORE_EXIT(); \ + } + +INT_DEMUX(16); +INT_DEMUX(17); +INT_DEMUX(18); +INT_DEMUX(19); +INT_DEMUX(20); +INT_DEMUX(21); +INT_DEMUX(22); +INT_DEMUX(23); +INT_DEMUX(24); +INT_DEMUX(25); +INT_DEMUX(27); +INT_DEMUX(26); +INT_DEMUX(28); +INT_DEMUX(29); +INT_DEMUX(30); +INT_DEMUX(31); +INT_DEMUX(32); +INT_DEMUX(33); +INT_DEMUX(34); +INT_DEMUX(35); +INT_DEMUX(36); +INT_DEMUX(37); +INT_DEMUX(38); +INT_DEMUX(39); +INT_DEMUX(40); +INT_DEMUX(41); +INT_DEMUX(42); +INT_DEMUX(43); +INT_DEMUX(44); +INT_DEMUX(45); +INT_DEMUX(46); +INT_DEMUX(47); +INT_DEMUX(48); +INT_DEMUX(49); +INT_DEMUX(50); +INT_DEMUX(51); +INT_DEMUX(52); +INT_DEMUX(53); +INT_DEMUX(54); +INT_DEMUX(55); +INT_DEMUX(56); +INT_DEMUX(57); +INT_DEMUX(58); +INT_DEMUX(59); +INT_DEMUX(60); +INT_DEMUX(61); +INT_DEMUX(62); +INT_DEMUX(63); +INT_DEMUX(64); +INT_DEMUX(65); +INT_DEMUX(66); +INT_DEMUX(67); +INT_DEMUX(68); +INT_DEMUX(69); +INT_DEMUX(70); +INT_DEMUX(71); +INT_DEMUX(72); +INT_DEMUX(73); +INT_DEMUX(74); +INT_DEMUX(75); +INT_DEMUX(76); +INT_DEMUX(77); +INT_DEMUX(78); +INT_DEMUX(79); +INT_DEMUX(80); +INT_DEMUX(81); +INT_DEMUX(82); +INT_DEMUX(83); +INT_DEMUX(84); +INT_DEMUX(85); +INT_DEMUX(86); +INT_DEMUX(87); +INT_DEMUX(88); +INT_DEMUX(89); +INT_DEMUX(90); +INT_DEMUX(91); +INT_DEMUX(92); +INT_DEMUX(93); +INT_DEMUX(94); +INT_DEMUX(95); +INT_DEMUX(96); +INT_DEMUX(97); +INT_DEMUX(98); +INT_DEMUX(99); +INT_DEMUX(100) +INT_DEMUX(101); +INT_DEMUX(102); +INT_DEMUX(103); +INT_DEMUX(104); +INT_DEMUX(105); +INT_DEMUX(106); +INT_DEMUX(107); +INT_DEMUX(108); +INT_DEMUX(109); +INT_DEMUX(110); +INT_DEMUX(111); +INT_DEMUX(112); +INT_DEMUX(113); +INT_DEMUX(114); +INT_DEMUX(115); +INT_DEMUX(116); +INT_DEMUX(117); +INT_DEMUX(118); +INT_DEMUX(119); +INT_DEMUX(120); +INT_DEMUX(121); +INT_DEMUX(122); +INT_DEMUX(123); +INT_DEMUX(124); +INT_DEMUX(125); +INT_DEMUX(126); +INT_DEMUX(127); +INT_DEMUX(128); +INT_DEMUX(129); +INT_DEMUX(130); +INT_DEMUX(131); +INT_DEMUX(132); +INT_DEMUX(133); +INT_DEMUX(134); +INT_DEMUX(135); +INT_DEMUX(136); +INT_DEMUX(137); +INT_DEMUX(138); +INT_DEMUX(139); +INT_DEMUX(140); +INT_DEMUX(141); +INT_DEMUX(142); +INT_DEMUX(143); +INT_DEMUX(144); +INT_DEMUX(145); +INT_DEMUX(146); +INT_DEMUX(147); +INT_DEMUX(148); +INT_DEMUX(149); +INT_DEMUX(150); +INT_DEMUX(151); +INT_DEMUX(152); +INT_DEMUX(153); +INT_DEMUX(154); +INT_DEMUX(155); +INT_DEMUX(156); +INT_DEMUX(157); +INT_DEMUX(158); +INT_DEMUX(159); +INT_DEMUX(160); +INT_DEMUX(161); +INT_DEMUX(162); +INT_DEMUX(163); +INT_DEMUX(164); +INT_DEMUX(165); +INT_DEMUX(166); +INT_DEMUX(167); +INT_DEMUX(168); +INT_DEMUX(169); +INT_DEMUX(170); +INT_DEMUX(171); +INT_DEMUX(172); +INT_DEMUX(173); +INT_DEMUX(174); +INT_DEMUX(175); +INT_DEMUX(176); +INT_DEMUX(177); +INT_DEMUX(178); +INT_DEMUX(179); +INT_DEMUX(180); +INT_DEMUX(181); +INT_DEMUX(182); +INT_DEMUX(183); +INT_DEMUX(184); +INT_DEMUX(185); +INT_DEMUX(186); +INT_DEMUX(187); +INT_DEMUX(188); +INT_DEMUX(189); +INT_DEMUX(190); +INT_DEMUX(191); +INT_DEMUX(192); +INT_DEMUX(193); +INT_DEMUX(194); +INT_DEMUX(195); +INT_DEMUX(196); +INT_DEMUX(197); +INT_DEMUX(198); +INT_DEMUX(199); +INT_DEMUX(200); +INT_DEMUX(201); +INT_DEMUX(202); +INT_DEMUX(203); +INT_DEMUX(204); +INT_DEMUX(205); +INT_DEMUX(206); +INT_DEMUX(207); +INT_DEMUX(208); +INT_DEMUX(209); +INT_DEMUX(210); +INT_DEMUX(211); +INT_DEMUX(212); +INT_DEMUX(213); +INT_DEMUX(214); +INT_DEMUX(215); +INT_DEMUX(216); +INT_DEMUX(217); +INT_DEMUX(218); +INT_DEMUX(219); +INT_DEMUX(220); +INT_DEMUX(221); +INT_DEMUX(222); +INT_DEMUX(223); +INT_DEMUX(224); +INT_DEMUX(225); +INT_DEMUX(226); +INT_DEMUX(227); +INT_DEMUX(228); +INT_DEMUX(229); +INT_DEMUX(230); +INT_DEMUX(231); +INT_DEMUX(232); +INT_DEMUX(233); +INT_DEMUX(234); +INT_DEMUX(235); +INT_DEMUX(236); +INT_DEMUX(237); +INT_DEMUX(238); +INT_DEMUX(239); +INT_DEMUX(240); +INT_DEMUX(241); +INT_DEMUX(242); +INT_DEMUX(243); +INT_DEMUX(244); +INT_DEMUX(245); +INT_DEMUX(246); +INT_DEMUX(247); +INT_DEMUX(248); +INT_DEMUX(249); +INT_DEMUX(250); +INT_DEMUX(251); +INT_DEMUX(252); +INT_DEMUX(253); +INT_DEMUX(254); +INT_DEMUX(255); + +const void *FixedVectors[] FVECT_SECT = { + /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ + /* Reserved for OFSM */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved for ID Code */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* 0x50: Privileged instruction exception */ + INT_Excep_SuperVisorInst, + /* 0x54: Access exception */ + INT_Excep_AccessInst, + /* 0x58: Reserved */ + Dummy, + /* 0x5c: Undefined Instruction Exception */ + INT_Excep_UndefinedInst, + /* 0x60: Reserved */ + Dummy, + /* 0x64: Floating Point Exception */ + INT_Excep_FloatingPoint, + /* 0x68-0x74: Reserved */ + Dummy, + Dummy, + Dummy, + Dummy, + /* 0x78: Non-maskable interrupt */ + INT_NonMaskableInterrupt, + _start, +}; + +const fp RelocatableVectors[] RVECT_SECT = { + reserved_isr, switch_isr_wrapper, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, int_demux_16, int_demux_17, int_demux_18, int_demux_19, + int_demux_20, int_demux_21, int_demux_22, int_demux_23, int_demux_24, + int_demux_25, int_demux_26, int_demux_27, int_demux_28, int_demux_29, + int_demux_30, int_demux_31, int_demux_32, int_demux_33, int_demux_34, + int_demux_35, int_demux_36, int_demux_37, int_demux_38, int_demux_39, + int_demux_40, int_demux_41, int_demux_42, int_demux_43, int_demux_44, + int_demux_45, int_demux_46, int_demux_47, int_demux_48, int_demux_49, + int_demux_50, int_demux_51, int_demux_52, int_demux_53, int_demux_54, + int_demux_55, int_demux_56, int_demux_57, int_demux_58, int_demux_59, + int_demux_60, int_demux_61, int_demux_62, int_demux_63, int_demux_64, + int_demux_65, int_demux_66, int_demux_67, int_demux_68, int_demux_69, + int_demux_70, int_demux_71, int_demux_72, int_demux_73, int_demux_74, + int_demux_75, int_demux_76, int_demux_77, int_demux_78, int_demux_79, + int_demux_80, int_demux_81, int_demux_82, int_demux_83, int_demux_84, + int_demux_85, int_demux_86, int_demux_87, int_demux_88, int_demux_89, + int_demux_90, int_demux_91, int_demux_92, int_demux_93, int_demux_94, + int_demux_95, int_demux_96, int_demux_97, int_demux_98, int_demux_99, + int_demux_100, int_demux_101, int_demux_102, int_demux_103, int_demux_104, + int_demux_105, int_demux_106, int_demux_107, int_demux_108, int_demux_109, + int_demux_110, int_demux_111, int_demux_112, int_demux_113, int_demux_114, + int_demux_115, int_demux_116, int_demux_117, int_demux_118, int_demux_119, + int_demux_120, int_demux_121, int_demux_122, int_demux_123, int_demux_124, + int_demux_125, int_demux_126, int_demux_127, int_demux_128, int_demux_129, + int_demux_130, int_demux_131, int_demux_132, int_demux_133, int_demux_134, + int_demux_135, int_demux_136, int_demux_137, int_demux_138, int_demux_139, + int_demux_140, int_demux_141, int_demux_142, int_demux_143, int_demux_144, + int_demux_145, int_demux_146, int_demux_147, int_demux_148, int_demux_149, + int_demux_150, int_demux_151, int_demux_152, int_demux_153, int_demux_154, + int_demux_155, int_demux_156, int_demux_157, int_demux_158, int_demux_159, + int_demux_160, int_demux_161, int_demux_162, int_demux_163, int_demux_164, + int_demux_165, int_demux_166, int_demux_167, int_demux_168, int_demux_169, + int_demux_170, int_demux_171, int_demux_172, int_demux_173, int_demux_174, + int_demux_175, int_demux_176, int_demux_177, int_demux_178, int_demux_179, + int_demux_180, int_demux_181, int_demux_182, int_demux_183, int_demux_184, + int_demux_185, int_demux_186, int_demux_187, int_demux_188, int_demux_189, + int_demux_190, int_demux_191, int_demux_192, int_demux_193, int_demux_194, + int_demux_195, int_demux_196, int_demux_197, int_demux_198, int_demux_199, + int_demux_200, int_demux_201, int_demux_202, int_demux_203, int_demux_204, + int_demux_205, int_demux_206, int_demux_207, int_demux_208, int_demux_209, + int_demux_210, int_demux_211, int_demux_212, int_demux_213, int_demux_214, + int_demux_215, int_demux_216, int_demux_217, int_demux_218, int_demux_219, + int_demux_220, int_demux_221, int_demux_222, int_demux_223, int_demux_224, + int_demux_225, int_demux_226, int_demux_227, int_demux_228, int_demux_229, + int_demux_230, int_demux_231, int_demux_232, int_demux_233, int_demux_234, + int_demux_235, int_demux_236, int_demux_237, int_demux_238, int_demux_239, + int_demux_240, int_demux_241, int_demux_242, int_demux_243, int_demux_244, + int_demux_245, int_demux_246, int_demux_247, int_demux_248, int_demux_249, + int_demux_250, int_demux_251, int_demux_252, int_demux_253, int_demux_254, + int_demux_255, +}; diff --git a/arch/rx/include/kernel_arch_data.h b/arch/rx/include/kernel_arch_data.h new file mode 100644 index 000000000000..43762032f63a --- /dev/null +++ b/arch/rx/include/kernel_arch_data.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Private kernel definitions (rx) + * + * This file contains private kernel structures definitions and various + * other definitions for the Renesas rx architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ + +#include +#include +#include + +#ifndef _ASMLANGUAGE +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* place C-code here */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/rx/include/kernel_arch_func.h b/arch/rx/include/kernel_arch_func.h new file mode 100644 index 000000000000..70058fb5c96a --- /dev/null +++ b/arch/rx/include/kernel_arch_func.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ + +#ifndef _ASMLANGUAGE +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static ALWAYS_INLINE void arch_kernel_init(void) +{ + /* check if: further device initialization functions must be called here */ +} + +static inline bool arch_is_in_isr(void) +{ + return arch_curr_cpu()->nested != 0U; +} + +extern void z_rx_arch_switch(void *switch_to, void **switched_from); + +static inline void arch_switch(void *switch_to, void **switched_from) +{ + z_rx_arch_switch(switch_to, switched_from); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/rx/include/offsets_short_arch.h b/arch/rx/include/offsets_short_arch.h new file mode 100644 index 000000000000..796d4512b26d --- /dev/null +++ b/arch/rx/include/offsets_short_arch.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ + +#include + +/* kernel */ +#define KERNEL_OFFSET(field) _kernel_offset_to_##field + +#define _kernel_offset_to_flags (___kernel_t_arch_OFFSET + ___kernel_arch_t_flags_OFFSET) + +/* end - kernel */ + +/* threads */ +#define THREAD_OFFSET(field) _thread_offset_to_##field + +#define _thread_offset_to_sp (___thread_t_callee_saved_OFFSET + ___callee_saved_t_topOfStack_OFFSET) + +#define _thread_offset_to_retval (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) + +#define _thread_offset_to_coopCoprocReg \ + (___thread_t_arch_OFFSET + ___thread_arch_t_coopCoprocReg_OFFSET) + +#define _thread_offset_to_preempCoprocReg \ + (___thread_t_arch_OFFSET + ___thread_arch_t_preempCoprocReg_OFFSET) + +#define _thread_offset_to_cpStack \ + (_thread_offset_to_preempCoprocReg + __tPreempCoprocReg_cpStack_OFFSET) + +#define _thread_offset_to_cpEnable (_thread_offset_to_cpStack + XT_CPENABLE) + +/* end - threads */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c947c0afc1b8..a9a883a3104f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -83,6 +83,7 @@ config X86_64 select X86_MMX select X86_SSE select X86_SSE2 + select ARCH_HAS_DIRECTED_IPIS if !X2APIC menu "x86 Features" diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt index e8055c6fae27..c34c6909b017 100644 --- a/arch/x86/core/CMakeLists.txt +++ b/arch/x86/core/CMakeLists.txt @@ -21,10 +21,14 @@ zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c) zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c) +zephyr_library_sources_ifdef(CONFIG_DYNAMIC_BOOTARGS bootargs.c) + zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) +zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) + if(CONFIG_X86_64) include(intel64.cmake) else() diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index 7b5359a7ecd6..e1f5869c7722 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -35,7 +35,6 @@ config ARCH_HAS_STACKWALK select DEBUG_INFO select THREAD_STACK_INFO depends on !OMIT_FRAME_POINTER - depends on NO_OPTIMIZATIONS help Internal config to indicate that the arch_stack_walk() API is implemented and it can be enabled. diff --git a/arch/x86/core/bootargs.c b/arch/x86/core/bootargs.c new file mode 100644 index 000000000000..5ae4c2b0f950 --- /dev/null +++ b/arch/x86/core/bootargs.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if defined(CONFIG_MULTIBOOT_INFO) + +__pinned_noinit char multiboot_cmdline[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; + +const char *get_bootargs(void) +{ + return multiboot_cmdline; +} + +#elif defined(CONFIG_X86_EFI) + +__pinned_noinit char efi_bootargs[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; + +const char *get_bootargs(void) +{ + return efi_bootargs; +} + +#endif diff --git a/arch/x86/core/efi.c b/arch/x86/core/efi.c index 64faeb9efa53..e5470e6d8a36 100644 --- a/arch/x86/core/efi.c +++ b/arch/x86/core/efi.c @@ -18,10 +18,6 @@ static uint64_t __aligned(64) efi_stack[1024]; struct efi_boot_arg *efi; -#ifdef CONFIG_DYNAMIC_BOOTARGS -__pinned_noinit char efi_bootargs[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; -#endif - void *efi_get_acpi_rsdp(void) { if (efi == NULL) { @@ -173,10 +169,3 @@ int arch_printk_char_out(int c) return efi_console_putchar(c); } #endif - -#ifdef CONFIG_DYNAMIC_BOOTARGS -const char *get_bootargs(void) -{ - return efi_bootargs; -} -#endif /* CONFIG_DYNAMIC_BOOTARGS */ diff --git a/arch/x86/core/elf.c b/arch/x86/core/elf.c new file mode 100644 index 000000000000..a1660387d0ec --- /dev/null +++ b/arch/x86/core/elf.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); + +#ifdef CONFIG_64BIT +#define R_X86_64_64 1 +#define R_X86_64_PC32 2 +#define R_X86_64_PLT32 4 +#define R_X86_64_32 10 +#define R_X86_64_32S 11 + +/** + * @brief Architecture specific function for relocating shared elf + * + * Elf files contain a series of relocations described in multiple sections. + * These relocation instructions are architecture specific and each architecture + * supporting modules must implement this. + * + * The relocation codes are well documented: + * + * https://refspecs.linuxfoundation.org/elf/x86_64-abi-0.95.pdf (intel64) + */ +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) +{ + int ret = 0; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } + + sym_base_addr += rel->r_addend; + + int reloc_type = ELF32_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_X86_64_PC32: + case R_X86_64_PLT32: + *(uint32_t *)loc = sym_base_addr - loc; + break; + case R_X86_64_64: + case R_X86_64_32: + case R_X86_64_32S: + *(uint32_t *)loc = sym_base_addr; + break; + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; + break; + } + + return ret; +} +#else +#define R_386_32 1 +#define R_286_PC32 2 + +/** + * @brief Architecture specific function for relocating shared elf + * + * Elf files contain a series of relocations described in multiple sections. + * These relocation instructions are architecture specific and each architecture + * supporting modules must implement this. + * + * The relocation codes are well documented: + * + * https://docs.oracle.com/cd/E19683-01/817-3677/chapter6-26/index.html (ia32) + */ +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) +{ + int ret = 0; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + /* x86 uses elf_rel_t records with no addends */ + uintptr_t addend = *(uintptr_t *)loc; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } + + sym_base_addr += addend; + + int reloc_type = ELF32_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_386_32: + *(uint32_t *)loc = sym_base_addr; + break; + case R_286_PC32: + *(uint32_t *)loc = sym_base_addr - loc; + break; + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; + break; + } + + return ret; +} +#endif diff --git a/arch/x86/core/ia32/float.c b/arch/x86/core/ia32/float.c index c89bf7accd5a..9b6f4daa18e0 100644 --- a/arch/x86/core/ia32/float.c +++ b/arch/x86/core/ia32/float.c @@ -194,7 +194,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options) * must be preserved). */ - fp_owner = _kernel.current_fp; + fp_owner = _kernel.cpus[0].arch.fpu_owner; if (fp_owner != NULL) { if ((fp_owner->arch.flags & X86_THREAD_FLAG_ALL) != 0) { FpCtxSave(fp_owner); @@ -215,7 +215,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options) * (The FP context is "live" in hardware, not saved in TCS.) */ - _kernel.current_fp = thread; + _kernel.cpus[0].arch.fpu_owner = thread; } else { /* * When enabling FP support for someone else, assign ownership @@ -230,7 +230,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options) * to its original state. */ - _kernel.current_fp = thread; + _kernel.cpus[0].arch.fpu_owner = thread; z_FpAccessDisable(); } else { /* @@ -280,10 +280,10 @@ int z_float_disable(struct k_thread *thread) if (thread == _current) { z_FpAccessDisable(); - _kernel.current_fp = (struct k_thread *)0; + _kernel.cpus[0].arch.fpu_owner = (struct k_thread *)0; } else { - if (_kernel.current_fp == thread) { - _kernel.current_fp = (struct k_thread *)0; + if (_kernel.cpus[0].arch.fpu_owner == thread) { + _kernel.cpus[0].arch.fpu_owner = (struct k_thread *)0; } } diff --git a/arch/x86/core/ia32/swap.S b/arch/x86/core/ia32/swap.S index af104fdff478..6103e4bbe538 100644 --- a/arch/x86/core/ia32/swap.S +++ b/arch/x86/core/ia32/swap.S @@ -50,7 +50,7 @@ * Floating point registers are handled using a lazy save/restore mechanism * since it's expected relatively few threads will be created with the * K_FP_REGS or K_SSE_REGS option bits. The kernel data structure maintains a - * 'current_fp' field to keep track of the thread that "owns" the floating + * 'fpu_owner' field to keep track of the thread that "owns" the floating * point registers. Floating point registers consist of ST0->ST7 (x87 FPU and * MMX registers) and XMM0 -> XMM7. * @@ -176,7 +176,7 @@ SECTION_FUNC(PINNED_TEXT, arch_swap) * If so, there there is no need to restore the floating point context. */ - movl _kernel_offset_to_current_fp(%edi), %ebx + movl _kernel_offset_to_fpu_owner(%edi), %ebx cmpl %ebx, %eax je restoreContext_NoFloatSwap @@ -265,7 +265,7 @@ restoreContext_NoFloatRestore: /* record that the incoming thread "owns" the floating point registers */ - movl %eax, _kernel_offset_to_current_fp(%edi) + movl %eax, _kernel_offset_to_fpu_owner(%edi) /* diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 8d68afa2a191..31dbf060d6c9 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -97,7 +97,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, */ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot) { -#if defined(CONFIG_ACPI) +#if defined(CONFIG_ACPI) && !defined(CONFIG_ACRN_COMMON) __ASSERT(z_x86_cpuid_get_current_physical_apic_id() == x86_cpu_loapics[cpuboot->cpu_id], "APIC ID miss match!"); #endif diff --git a/arch/x86/core/intel64/smp.c b/arch/x86/core/intel64/smp.c index 1e0aeb3e443a..d6c18cec9e66 100644 --- a/arch/x86/core/intel64/smp.c +++ b/arch/x86/core/intel64/smp.c @@ -8,6 +8,7 @@ #include #include #include +#include #define NR_IRQ_VECTORS (IV_NR_VECTORS - IV_IRQS) /* # vectors free for IRQs */ @@ -38,3 +39,16 @@ void arch_sched_broadcast_ipi(void) { z_loapic_ipi(0, LOAPIC_ICR_IPI_OTHERS, CONFIG_SCHED_IPI_VECTOR); } + +void arch_sched_directed_ipi(uint32_t cpu_bitmap) +{ + unsigned int num_cpus = arch_num_cpus(); + + for (unsigned int i = 0; i < num_cpus; i++) { + if ((cpu_bitmap & BIT(i)) == 0) { + continue; + } + + z_loapic_ipi(i, LOAPIC_ICR_IPI_SPECIFIC, CONFIG_SCHED_IPI_VECTOR); + } +} diff --git a/arch/x86/core/multiboot.c b/arch/x86/core/multiboot.c index b6112b75f82e..06d03c7b8071 100644 --- a/arch/x86/core/multiboot.c +++ b/arch/x86/core/multiboot.c @@ -11,15 +11,6 @@ struct multiboot_info multiboot_info; -#ifdef CONFIG_DYNAMIC_BOOTARGS -__pinned_noinit char multiboot_cmdline[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; - -const char *get_bootargs(void) -{ - return multiboot_cmdline; -} -#endif /* CONFIG_DYNAMIC_BOOTARGS */ - /* * called very early in the boot process to fetch data out of the multiboot * info struct. we need to grab the relevant data before any dynamic memory diff --git a/arch/x86/core/offsets/ia32_offsets.c b/arch/x86/core/offsets/ia32_offsets.c index 2dfbb5c38ef2..dcbf3d7d6806 100644 --- a/arch/x86/core/offsets/ia32_offsets.c +++ b/arch/x86/core/offsets/ia32_offsets.c @@ -33,6 +33,12 @@ GEN_OFFSET_SYM(_thread_arch_t, excNestCount); #endif +#if defined(CONFIG_FPU_SHARING) +GEN_OFFSET_SYM(_kernel_t, cpus); +GEN_OFFSET_SYM(_cpu_t, arch); +GEN_OFFSET_SYM(_cpu_arch_t, fpu_owner); +#endif + #ifdef CONFIG_USERSPACE GEN_OFFSET_SYM(_thread_arch_t, psp); #ifndef CONFIG_X86_COMMON_PAGE_TABLE diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index 96c76f6af26b..2b371d8bfb13 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -61,7 +61,7 @@ FUNC_NORETURN void z_prep_c(void *arg) #ifdef CONFIG_X86_VERY_EARLY_CONSOLE z_x86_early_serial_init(); -#if defined(CONFIG_BOARD_QEMU_X86) || defined(CONFIG_BOARD_QEMU_X86_64) +#if defined(CONFIG_QEMU_TARGET) /* * Under QEMU and SeaBIOS, everything gets to be printed * immediately after "Booting from ROM.." as there is no newline. diff --git a/arch/x86/include/ia32/offsets_short_arch.h b/arch/x86/include/ia32/offsets_short_arch.h index cb5cdb218f0a..b818cf60b550 100644 --- a/arch/x86/include/ia32/offsets_short_arch.h +++ b/arch/x86/include/ia32/offsets_short_arch.h @@ -14,6 +14,9 @@ #define _kernel_offset_to_isf \ (___kernel_t_arch_OFFSET + ___kernel_arch_t_isf_OFFSET) +#define _kernel_offset_to_fpu_owner \ + (___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_fpu_owner_OFFSET) + /* end - kernel */ /* threads */ diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index b69d8bcf02b2..143607a22950 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -169,7 +169,6 @@ config XTENSA_MMU bool "Xtensa MMU Support" select MMU select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE - select XTENSA_SMALL_VECTOR_TABLE_ENTRY select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE select CURRENT_THREAD_USE_NO_TLS if USERSPACE help @@ -223,16 +222,17 @@ config XTENSA_MMU_DOUBLE_MAP This option specifies that the memory is mapped in two distinct region, cached and uncached. - config XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP - bool - help - This invalidates all TLBs referred by the incoming thread's - memory domain when swapping page tables. - config PRIVILEGED_STACK_SIZE # Must be multiple of CONFIG_MMU_PAGE_SIZE default 4096 +config XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + bool "Flush all auto-refill data TLBs when swapping page tables" + depends on USERSPACE + help + This flushes (invalidates) all auto-refill data TLBs when page + tables are swapped. + endif # XTENSA_MMU endif # CPU_HAS_MMU diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index 7d7e260ca0b0..e3d6025a91f2 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -39,6 +39,17 @@ if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc") zephyr_library_sources(xcc_stubs.c) endif() +# ...where to find core-isa.h for custom compilation commands below. +if(CONFIG_SOC_FAMILY_ESPRESSIF_ESP32) + set(XTENSA_CONFIG_HAL_INCLUDE_DIR + -I${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/components/xtensa/${CONFIG_SOC}/include + ) +else() + set(XTENSA_CONFIG_HAL_INCLUDE_DIR + -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ) +endif() + add_subdirectory(startup) # This produces a preprocessed and regenerated (in the sense of gcc @@ -54,7 +65,7 @@ set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c) file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG} - -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ${XTENSA_CONFIG_HAL_INCLUDE_DIR} -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) @@ -73,13 +84,19 @@ else() set(MAY_NEED_SYSCALL_SCRATCH_REG false) endif() +if(CONFIG_KERNEL_COHERENCE AND NOT CONFIG_SCHED_CPU_MASK_PIN_ONLY) + set(NEED_FLUSH_SCRATCH_REG true) +else() + set(NEED_FLUSH_SCRATCH_REG false) +endif() + # Generates a list of device-specific scratch register choices set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h) add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM} COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py $<$:--mmu> $<$:--syscall-scratch> - $<$:--coherence> + $<$:--flush-reg> ${CORE_ISA_DM} ${ZSR_H}) add_custom_target(zsr_h DEPENDS ${ZSR_H}) add_dependencies(zephyr_interface zsr_h) @@ -92,7 +109,7 @@ set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers) add_custom_command( OUTPUT ${HANDLERS}_tmp.c COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__ - -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ${XTENSA_CONFIG_HAL_INCLUDE_DIR} -o ${HANDLERS}_tmp.c - < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl) diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index 17337f4a7bc6..d16f51e61a23 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -34,21 +34,27 @@ LOG_MODULE_DECLARE(llext, CONFIG_LLEXT_LOG_LEVEL); static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, uintptr_t addr, - uint8_t *loc, int type, uint32_t stb) + uint8_t *loc, int type, uint32_t stb, + const struct llext_load_param *ldr_parm) { elf_word *got_entry = (elf_word *)loc; switch (type) { case R_XTENSA_RELATIVE: - ; + if (ldr_parm->pre_located) { + /* Relative relocations are already correct in the pre-located case */ + break; + } + /* Relocate a local symbol: Xtensa specific. Seems to only be used with PIC */ unsigned int sh_ndx; for (sh_ndx = 0; sh_ndx < ext->sect_cnt; sh_ndx++) { if (ext->sect_hdrs[sh_ndx].sh_addr <= *got_entry && *got_entry < - ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) + ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) { break; + } } if (sh_ndx == ext->sect_cnt) { @@ -146,7 +152,8 @@ void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const sh_addr = ldr->sects[LLEXT_MEM_TEXT].sh_addr; } - xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info)); + xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info), + ldr_parm); } /** @@ -163,5 +170,5 @@ void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const } xtensa_elf_relocate(ldr, ext, rel, (uintptr_t)link_addr, rel_addr, type, - ELF_ST_BIND(sym->st_info)); + ELF_ST_BIND(sym->st_info), NULL); } diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c index 0ebc9cc68ccd..91a1d58f8014 100644 --- a/arch/xtensa/core/gdbstub.c +++ b/arch/xtensa/core/gdbstub.c @@ -427,14 +427,14 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - uint32_t *bsa = *(int **)stack; + uint32_t *bsa = *(const int **)stack; - if ((int *)bsa - stack > 4) { - num_laddr_regs = 8; - } else if ((int *)bsa - stack > 8) { - num_laddr_regs = 12; - } else if ((int *)bsa - stack > 12) { + if (bsa - (const uint32_t *)stack > 12) { num_laddr_regs = 16; + } else if (bsa - (const uint32_t *)stack > 8) { + num_laddr_regs = 12; + } else if (bsa - (const uint32_t *)stack > 4) { + num_laddr_regs = 8; } else { num_laddr_regs = 4; } @@ -445,8 +445,7 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) if (reg->regno == SOC_GDB_REGNO_A1) { /* A1 is calculated */ - reg->val = POINTER_TO_UINT( - ((char *)bsa) + BASE_SAVE_AREA_SIZE); + reg->val = POINTER_TO_UINT(((char *)bsa) + sizeof(_xtensa_irq_bsa_t)); reg->seqno = ctx->seqno; } else { reg->val = bsa[reg->stack_offset / 4]; @@ -518,14 +517,14 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - _xtensa_irq_bsa_t *bsa = (void *)*(int **)stack; + _xtensa_irq_bsa_t *bsa = (void *)*(const int **)stack; - if ((int *)bsa - stack > 4) { - num_laddr_regs = 8; - } else if ((int *)bsa - stack > 8) { - num_laddr_regs = 12; - } else if ((int *)bsa - stack > 12) { + if ((uint32_t *)bsa - (const uint32_t *)stack > 12) { num_laddr_regs = 16; + } else if ((uint32_t *)bsa - (const uint32_t *)stack > 8) { + num_laddr_regs = 12; + } else if ((uint32_t *)bsa - (const uint32_t *)stack > 4) { + num_laddr_regs = 8; } else { num_laddr_regs = 4; } @@ -547,7 +546,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) /* Shouldn't be changing stack pointer */ continue; } else { - bsa[reg->stack_offset / 4] = reg->val; + ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; } } @@ -559,7 +558,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) continue; } else if (reg->stack_offset != 0) { /* For those registers stashed in stack */ - bsa[reg->stack_offset / 4] = reg->val; + ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; } else if (gdb_xtensa_is_special_reg(reg)) { /* * Currently not writing back any special diff --git a/arch/xtensa/core/gen_zsr.py b/arch/xtensa/core/gen_zsr.py index 6d9a228303f3..8cb8a713019e 100755 --- a/arch/xtensa/core/gen_zsr.py +++ b/arch/xtensa/core/gen_zsr.py @@ -14,8 +14,8 @@ def parse_args(): parser = argparse.ArgumentParser(allow_abbrev=False) - parser.add_argument("--coherence", action="store_true", - help="Enable scratch registers for CONFIG_KERNEL_COHERENCE") + parser.add_argument("--flush-reg", action="store_true", + help="Enable scratch register ZSR_FLUSH for cache flushing") parser.add_argument("--mmu", action="store_true", help="Enable scratch registers for MMU usage") parser.add_argument("--syscall-scratch", action="store_true", @@ -32,7 +32,7 @@ def parse_args(): NEEDED = ["A0SAVE", "CPU"] if args.mmu: NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"] -if args.coherence: +if args.flush_reg: NEEDED += ["FLUSH"] coreisa = args.coreisa diff --git a/arch/xtensa/core/mmu.c b/arch/xtensa/core/mmu.c index c1073ac0247a..dd20136427a0 100644 --- a/arch/xtensa/core/mmu.c +++ b/arch/xtensa/core/mmu.c @@ -16,37 +16,33 @@ BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && #define ASID_INVALID 0 -struct tlb_regs { - uint32_t rasid; - uint32_t ptevaddr; - uint32_t ptepin_as; - uint32_t ptepin_at; - uint32_t vecpin_as; - uint32_t vecpin_at; -}; - -static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs *regs) +extern uint32_t *xtensa_kernel_ptables; + +void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain) { uint32_t vecbase = XTENSA_RSR("VECBASE"); + uint32_t *l1_page = domain->ptables; + uint32_t user_asid = domain->asid; __ASSERT_NO_MSG((((uint32_t)l1_page) & 0xfff) == 0); __ASSERT_NO_MSG((user_asid == 0) || ((user_asid > 2) && (user_asid < XTENSA_MMU_SHARED_ASID))); /* We don't use ring 1, ring 0 ASID must be 1 */ - regs->rasid = (XTENSA_MMU_SHARED_ASID << 24) | - (user_asid << 16) | 0x000201; + domain->reg_asid = (XTENSA_MMU_SHARED_ASID << 24) | + (user_asid << 16) | 0x000201; /* Derive PTEVADDR from ASID so each domain gets its own PTE area */ - regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000; + domain->reg_ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000; /* The ptables code doesn't add the mapping for the l1 page itself */ - l1_page[XTENSA_MMU_L1_POS(regs->ptevaddr)] = + l1_page[XTENSA_MMU_L1_POS(domain->reg_ptevaddr)] = (uint32_t)l1_page | XTENSA_MMU_PAGE_TABLE_ATTR; - regs->ptepin_at = (uint32_t)l1_page; - regs->ptepin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, regs->ptevaddr) - | XTENSA_MMU_PTE_WAY; + domain->reg_ptepin_at = (uint32_t)l1_page; + domain->reg_ptepin_as = XTENSA_MMU_PTE_ENTRY_VADDR(domain->reg_ptevaddr, + domain->reg_ptevaddr) + | XTENSA_MMU_PTE_WAY; /* Pin mapping for refilling the vector address into the ITLB * (for handling TLB miss exceptions). Note: this is NOT an @@ -58,9 +54,10 @@ static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs */ uint32_t vb_pte = l1_page[XTENSA_MMU_L1_POS(vecbase)]; - regs->vecpin_at = vb_pte; - regs->vecpin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, vecbase) - | XTENSA_MMU_VECBASE_WAY; + domain->reg_vecpin_at = vb_pte; + domain->reg_vecpin_as = XTENSA_MMU_PTE_ENTRY_VADDR(domain->reg_ptevaddr, + vecbase) + | XTENSA_MMU_VECBASE_WAY; } /* Switch to a new page table. There are four items we have to set in @@ -78,18 +75,8 @@ static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs * couldn't think of a way to do the alignment statically that also * interoperated well with inline assembly). */ -void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page) +void xtensa_mmu_set_paging(struct arch_mem_domain *domain) { - /* Optimization note: the registers computed here are pure - * functions of the two arguments. With a minor API tweak, - * they could be cached in e.g. a thread struct instead of - * being recomputed. This is called on context switch paths - * and is performance-sensitive. - */ - struct tlb_regs regs; - - compute_regs(user_asid, l1_page, ®s); - __asm__ volatile("j 1f\n" ".align 16\n" /* enough for 5 insns */ "1:\n" @@ -98,12 +85,12 @@ void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page) "wdtlb %2, %3\n" "wdtlb %4, %5\n" "isync" - :: "r"(regs.ptevaddr), "r"(regs.rasid), - "r"(regs.ptepin_at), "r"(regs.ptepin_as), - "r"(regs.vecpin_at), "r"(regs.vecpin_as)); + :: "r"(domain->reg_ptevaddr), "r"(domain->reg_asid), + "r"(domain->reg_ptepin_at), "r"(domain->reg_ptepin_as), + "r"(domain->reg_vecpin_at), "r"(domain->reg_vecpin_as)); } -/* This is effectively the same algorithm from xtensa_set_paging(), +/* This is effectively the same algorithm from xtensa_mmu_set_paging(), * but it also disables the hardware-initialized 512M TLB entries in * way 6 (because the hardware disallows duplicate TLB mappings). For * instruction fetches this produces a critical ordering constraint: @@ -121,12 +108,19 @@ void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page) * asm for correctness. The other 13 entries get invalidated in a C * loop at the end. */ -void xtensa_init_paging(uint32_t *l1_page) +void xtensa_mmu_init_paging(void) { extern char z_xt_init_pc; /* defined in asm below */ - struct tlb_regs regs; unsigned int initial_rasid; + /* When this is called in xtensa_mmu_init(), the default memory + * domain struct has not been initialized, and memory domains + * are not ready to be used. So we need a local copy of + * struct arch_mem_domain to store the register values to be + * programmed into hardware. + */ + struct arch_mem_domain domain; + /* The initial rasid after hardware initialization is 0x04030201. * 1 is hardwired to ring 0, other slots must be different * from each other and must not be 0. @@ -146,10 +140,12 @@ void xtensa_init_paging(uint32_t *l1_page) sys_cache_data_flush_and_invd_all(); #endif - compute_regs(ASID_INVALID, l1_page, ®s); + domain.asid = ASID_INVALID; + domain.ptables = xtensa_kernel_ptables; + xtensa_mmu_compute_domain_regs(&domain); - uint32_t idtlb_pte = (regs.ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY; - uint32_t idtlb_stk = (((uint32_t)®s) & ~0xfff) | XCHAL_SPANNING_WAY; + uint32_t idtlb_pte = (domain.reg_ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY; + uint32_t idtlb_stk = (((uint32_t)&domain) & ~0xfff) | XCHAL_SPANNING_WAY; uint32_t iitlb_pc = (((uint32_t)&z_xt_init_pc) & ~0xfff) | XCHAL_SPANNING_WAY; /* Note: the jump is mostly pedantry, as it's almost @@ -171,9 +167,9 @@ void xtensa_init_paging(uint32_t *l1_page) "isync\n" "iitlb %8\n" /* invalidate pc */ "isync\n" /* <--- traps a ITLB miss */ - :: "r"(regs.ptevaddr), "r"(initial_rasid), - "r"(regs.ptepin_at), "r"(regs.ptepin_as), - "r"(regs.vecpin_at), "r"(regs.vecpin_as), + :: "r"(domain.reg_ptevaddr), "r"(initial_rasid), + "r"(domain.reg_ptepin_at), "r"(domain.reg_ptepin_as), + "r"(domain.reg_vecpin_at), "r"(domain.reg_vecpin_as), "r"(idtlb_pte), "r"(idtlb_stk), "r"(iitlb_pc)); /* Invalidate the remaining (unused by this function) diff --git a/arch/xtensa/core/offsets/offsets.c b/arch/xtensa/core/offsets/offsets.c index 69df38275bf6..f0b75c999cc6 100644 --- a/arch/xtensa/core/offsets/offsets.c +++ b/arch/xtensa/core/offsets/offsets.c @@ -67,8 +67,22 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi); #ifdef CONFIG_USERSPACE GEN_OFFSET_SYM(_thread_arch_t, psp); +GEN_OFFSET_SYM(_thread_arch_t, return_ps); +GEN_OFFSET_SYM(_thread_t, switch_handle); #ifdef CONFIG_XTENSA_MMU GEN_OFFSET_SYM(_thread_arch_t, ptables); + +GEN_OFFSET_SYM(_thread_t, mem_domain_info); +GEN_OFFSET_SYM(_mem_domain_info_t, mem_domain); +GEN_OFFSET_SYM(k_mem_domain_t, arch); + +GEN_OFFSET_SYM(arch_mem_domain_t, reg_asid); +GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptevaddr); +GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptepin_as); +GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptepin_at); +GEN_OFFSET_SYM(arch_mem_domain_t, reg_vecpin_as); +GEN_OFFSET_SYM(arch_mem_domain_t, reg_vecpin_at); + #endif #ifdef CONFIG_XTENSA_MPU GEN_OFFSET_SYM(_thread_arch_t, mpu_map); diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c index 6dbab69f50f5..771ad7e42307 100644 --- a/arch/xtensa/core/prep_c.c +++ b/arch/xtensa/core/prep_c.c @@ -44,10 +44,12 @@ void z_prep_c(void) */ sys_cache_data_flush_and_invd_all(); +#if !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) /* Our cache top stash location might have junk in it from a * pre-boot environment. Must be zero or valid! */ XTENSA_WSR(ZSR_FLUSH_STR, 0); +#endif #endif cpu0->nested = 0; diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index c02ecc64b0db..b66a9bc30f1f 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -157,17 +157,6 @@ static const struct xtensa_mmu_range mmu_zephyr_ranges[] = { }, }; -static inline uint32_t *thread_page_tables_get(const struct k_thread *thread) -{ -#ifdef CONFIG_USERSPACE - if ((thread->base.user_options & K_USER) != 0U) { - return thread->arch.ptables; - } -#endif - - return xtensa_kernel_ptables; -} - /** * @brief Check if the page table entry is illegal. * @@ -250,18 +239,25 @@ static void map_memory_range(const uint32_t start, const uint32_t end, static void map_memory(const uint32_t start, const uint32_t end, const uint32_t attrs) { - map_memory_range(start, end, attrs); - #ifdef CONFIG_XTENSA_MMU_DOUBLE_MAP + uint32_t uc_attrs = attrs & ~XTENSA_MMU_PTE_ATTR_CACHED_MASK; + uint32_t c_attrs = attrs | XTENSA_MMU_CACHED_WB; + if (sys_cache_is_ptr_uncached((void *)start)) { + map_memory_range(start, end, uc_attrs); + map_memory_range(POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)start)), - POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)end)), - attrs | XTENSA_MMU_CACHED_WB); + POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)end)), c_attrs); } else if (sys_cache_is_ptr_cached((void *)start)) { + map_memory_range(start, end, c_attrs); + map_memory_range(POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)start)), - POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)end)), attrs); - } + POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)end)), uc_attrs); + } else #endif + { + map_memory_range(start, end, attrs); + } } static void xtensa_init_page_tables(void) @@ -313,7 +309,7 @@ void xtensa_mmu_init(void) { xtensa_init_page_tables(); - xtensa_init_paging(xtensa_kernel_ptables); + xtensa_mmu_init_paging(); /* * This is used to determine whether we are faulting inside double @@ -328,7 +324,7 @@ void xtensa_mmu_init(void) void xtensa_mmu_reinit(void) { /* First initialize the hardware */ - xtensa_init_paging(xtensa_kernel_ptables); + xtensa_mmu_init_paging(); #ifdef CONFIG_USERSPACE struct k_thread *thread = _current_cpu->current; @@ -337,7 +333,7 @@ void xtensa_mmu_reinit(void) /* Set the page table for current context */ - xtensa_set_paging(domain->asid, domain->ptables); + xtensa_mmu_set_paging(domain); #endif /* CONFIG_USERSPACE */ arch_xtensa_mmu_post_init(_current_cpu->id == 0); @@ -706,7 +702,7 @@ void xtensa_mmu_tlb_shootdown(void) */ struct arch_mem_domain *domain = &(thread->mem_domain_info.mem_domain->arch); - xtensa_set_paging(domain->asid, (uint32_t *)thread_ptables); + xtensa_mmu_set_paging(domain); } } @@ -725,6 +721,15 @@ void xtensa_mmu_tlb_shootdown(void) #ifdef CONFIG_USERSPACE +static inline uint32_t *thread_page_tables_get(const struct k_thread *thread) +{ + if ((thread->base.user_options & K_USER) != 0U) { + return thread->arch.ptables; + } + + return xtensa_kernel_ptables; +} + static inline uint32_t *alloc_l1_table(void) { uint16_t idx; @@ -833,6 +838,7 @@ int arch_mem_domain_init(struct k_mem_domain *domain) sys_slist_append(&xtensa_domain_list, &domain->arch.node); end: + xtensa_mmu_compute_domain_regs(&domain->arch); ret = 0; err: @@ -995,7 +1001,9 @@ int arch_mem_domain_thread_add(struct k_thread *thread) * the current thread running. */ if (thread == _current_cpu->current) { - xtensa_set_paging(domain->arch.asid, thread->arch.ptables); + struct arch_mem_domain *arch_domain = &(domain->arch); + + xtensa_mmu_set_paging(arch_domain); } #if CONFIG_MP_MAX_NUM_CPUS > 1 @@ -1114,26 +1122,20 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return mem_buffer_validate(addr, size, write, XTENSA_MMU_USER_RING); } +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP +/* This is only used when swapping page tables and auto-refill DTLBs + * needing to be invalidated. Otherwise, SWAP_PAGE_TABLE assembly + * is used to avoid a function call. + */ void xtensa_swap_update_page_tables(struct k_thread *incoming) { - uint32_t *ptables = incoming->arch.ptables; struct arch_mem_domain *domain = &(incoming->mem_domain_info.mem_domain->arch); - xtensa_set_paging(domain->asid, ptables); - -#ifdef CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP - struct k_mem_domain *mem_domain = incoming->mem_domain_info.mem_domain; - - for (int idx = 0; idx < mem_domain->num_partitions; idx++) { - struct k_mem_partition *part = &mem_domain->partitions[idx]; - uintptr_t end = part->start + part->size; + xtensa_mmu_set_paging(domain); - for (uintptr_t addr = part->start; addr < end; addr += CONFIG_MMU_PAGE_SIZE) { - xtensa_dtlb_vaddr_invalidate((void *)addr); - } - } -#endif + xtensa_dtlb_autorefill_invalidate(); } +#endif #endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c index f9673e67814c..9e14a560e7e1 100644 --- a/arch/xtensa/core/syscall_helper.c +++ b/arch/xtensa/core/syscall_helper.c @@ -25,7 +25,7 @@ uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2, register uintptr_t a8 __asm__("%a8") = arg5; register uintptr_t a9 __asm__("%a9") = arg6; - __asm__ volatile("syscall\n\t" + __asm__ volatile(XTENSA_SYSCALL_ASM : "=r" (a2) : "r" (a2), "r" (a6), "r" (a3), "r" (a4), "r" (a5), "r" (a8), "r" (a9) @@ -45,7 +45,7 @@ uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2, register uintptr_t a5 __asm__("%a5") = arg4; register uintptr_t a8 __asm__("%a8") = arg5; - __asm__ volatile("syscall\n\t" + __asm__ volatile(XTENSA_SYSCALL_ASM : "=r" (a2) : "r" (a2), "r" (a6), "r" (a3), "r" (a4), "r" (a5), "r" (a8) @@ -64,7 +64,7 @@ uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, register uintptr_t a4 __asm__("%a4") = arg3; register uintptr_t a5 __asm__("%a5") = arg4; - __asm__ volatile("syscall\n\t" + __asm__ volatile(XTENSA_SYSCALL_ASM : "=r" (a2) : "r" (a2), "r" (a6), "r" (a3), "r" (a4), "r" (a5) @@ -73,61 +73,6 @@ uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, return a2; } -uintptr_t xtensa_syscall_helper_args_3(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t call_id) -{ - register uintptr_t a2 __asm__("%a2") = call_id; - register uintptr_t a6 __asm__("%a6") = arg1; - register uintptr_t a3 __asm__("%a3") = arg2; - register uintptr_t a4 __asm__("%a4") = arg3; - - __asm__ volatile("syscall\n\t" - : "=r" (a2) - : "r" (a2), "r" (a6), "r" (a3), "r" (a4) - : "memory"); - - return a2; -} - -uintptr_t xtensa_syscall_helper_args_2(uintptr_t arg1, uintptr_t arg2, - uintptr_t call_id) -{ - register uintptr_t a2 __asm__("%a2") = call_id; - register uintptr_t a6 __asm__("%a6") = arg1; - register uintptr_t a3 __asm__("%a3") = arg2; - - __asm__ volatile("syscall\n\t" - : "=r" (a2) - : "r" (a2), "r" (a6), "r" (a3) - : "memory"); - - return a2; -} - -uintptr_t xtensa_syscall_helper_args_1(uintptr_t arg1, uintptr_t call_id) -{ - register uintptr_t a2 __asm__("%a2") = call_id; - register uintptr_t a6 __asm__("%a6") = arg1; - - __asm__ volatile("syscall\n\t" - : "=r" (a2) - : "r" (a2), "r" (a6) - : "memory"); - - return a2; -} - -uintptr_t xtensa_syscall_helper_args_0(uintptr_t call_id) -{ - register uintptr_t a2 __asm__("%a2") = call_id; - - __asm__ volatile("syscall\n\t" - : "=r" (a2) - : "r" (a2) - : "memory"); - - return a2; -} #endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ #if XCHAL_HAVE_THREADPTR == 0 diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c index f9b8179173d4..2bf1a7e11d37 100644 --- a/arch/xtensa/core/thread.c +++ b/arch/xtensa/core/thread.c @@ -42,11 +42,7 @@ static void *init_stack(struct k_thread *thread, int *stack_top, void *ret; _xtensa_irq_stack_frame_a11_t *frame; #ifdef CONFIG_USERSPACE - struct xtensa_thread_stack_header *header = - (struct xtensa_thread_stack_header *)thread->stack_obj; - - thread->arch.psp = header->privilege_stack + - sizeof(header->privilege_stack); + thread->arch.psp = NULL; #endif /* Not-a-cpu ID Ensures that the first time this is run, the @@ -70,26 +66,19 @@ static void *init_stack(struct k_thread *thread, int *stack_top, (void)memset(frame, 0, bsasz); - frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1); #ifdef CONFIG_USERSPACE - if ((thread->base.user_options & K_USER) == K_USER) { -#ifdef CONFIG_INIT_STACKS - /* setup_thread_stack() does not initialize the architecture specific - * privileged stack. So we need to do it manually here as this function - * is called by arch_new_thread() via z_setup_new_thread() after - * setup_thread_stack() but before thread starts running. - * - * Note that only user threads have privileged stacks and kernel - * only threads do not. - */ - (void)memset(&header->privilege_stack[0], 0xaa, sizeof(header->privilege_stack)); -#endif + /* _restore_context uses this instead of frame->bsa.ps to + * restore PS value. + */ + thread->arch.return_ps = PS_WOE | PS_UM | PS_CALLINC(1); + if ((thread->base.user_options & K_USER) == K_USER) { frame->bsa.pc = (uintptr_t)arch_user_mode_enter; } else { frame->bsa.pc = (uintptr_t)z_thread_entry; } #else + frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1); frame->bsa.pc = (uintptr_t)z_thread_entry; #endif @@ -159,6 +148,30 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, struct k_thread *current = _current; size_t stack_end; + struct xtensa_thread_stack_header *header = + (struct xtensa_thread_stack_header *)current->stack_obj; + + current->arch.psp = header->privilege_stack + + sizeof(header->privilege_stack); + +#ifdef CONFIG_INIT_STACKS + /* setup_thread_stack() does not initialize the architecture specific + * privileged stack. So we need to do it manually here as this function + * is called by arch_new_thread() via z_setup_new_thread() after + * setup_thread_stack() but before thread starts running. + * + * Note that only user threads have privileged stacks and kernel + * only threads do not. + */ + (void)memset(&header->privilege_stack[0], 0xaa, sizeof(header->privilege_stack)); + +#endif + +#ifdef CONFIG_KERNEL_COHERENCE + sys_cache_data_flush_and_invd_range(&header->privilege_stack[0], + sizeof(header->privilege_stack)); +#endif + /* Transition will reset stack pointer to initial, discarding * any old context since this is a one-way operation */ diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index 3db5d8cea8d6..56d53d59b0b5 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -53,6 +53,12 @@ _is_user_context_return: _not_checking_user_context: rsr a2, ZSR_SYSCALL_SCRATCH #endif + + /* Need to disable any interrupts while we are saving + * register content to avoid any interferences. + */ + rsil a0, 0xf + rsr a0, ZSR_CPU l32i a0, a0, ___cpu_t_current_OFFSET l32i a0, a0, _thread_offset_to_psp @@ -65,21 +71,27 @@ _not_checking_user_context: rsr a2, ZSR_A0SAVE s32i a2, a0, ___xtensa_irq_bsa_t_a0_OFFSET rsr.ps a2 - movi a3, ~PS_OWB_MASK + movi a3, ~PS_OWB_MASK & ~PS_EXCM_MASK and a2, a2, a3 s32i a2, a0, ___xtensa_irq_bsa_t_ps_OFFSET - rsr.epc1 a2 - s32i a2, a0, ___xtensa_irq_bsa_t_pc_OFFSET -#if XCHAL_HAVE_NMI - movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NMILEVEL) -#elif XCHAL_HAVE_INTERRUPTS - movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NUM_INTLEVELS) -#else -#error Xtensa core with no interrupt support is used -#endif + /* Manipulate PC where we will return to after syscall. + * This is needed as syscall will stash the PC where + * the syscall instruction locates, instead of + * the instruction after it. We need to increment it to + * execute the next instruction when we return. + * The instruction size is 3 bytes, so lets just add it. + */ + rsr.epc1 a3 + addi a3, a3, 3 + s32i a3, a0, ___xtensa_irq_bsa_t_pc_OFFSET + + /* Need to setup PS so we can spill all registers. + * EXCM and RING bits need to be cleared as CPU + * needs to run in kernel and non-exception modes + * for window rotation to work. + */ rsr.ps a3 - or a3, a3, a2 movi a2, ~(PS_EXCM | PS_RING_MASK) and a3, a3, a2 wsr.ps a3 @@ -95,34 +107,7 @@ _not_checking_user_context: mov a1, a0 - l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET -#if XCHAL_HAVE_LOOPS - /* If the syscall instruction was the last instruction in the body of - * a zero-overhead loop, and the loop will execute again, decrement - * the loop count and resume execution at the head of the loop. - */ - rsr.lend a2 - addi a3, a3, 3 - bne a2, a3, end_loop - rsr.lcount a2 - beqz a2, end_loop - addi a2, a2, -1 - wsr.lcount a2 - rsr.lbeg a3 -end_loop: -#else - /* EPC1 (and now a3) contains the address that invoked syscall. - * We need to increment it to execute the next instruction when - * we return. The instruction size is 3 bytes, so lets just add it. - */ - addi a3, a3, 3 -#endif - s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET - ODD_REG_SAVE - -#if defined(CONFIG_XTENSA_HIFI_SHARING) - call0 _xtensa_hifi_save -#endif + ODD_REG_SAVE a0, a1 call0 xtensa_save_high_regs @@ -134,8 +119,7 @@ end_loop: _id_ok: /* Find the function handler for the given syscall id. */ movi a3, _k_syscall_table - slli a2, a2, 2 - add a2, a2, a3 + addx4 a2, a2, a3 l32i a2, a2, 0 #if XCHAL_HAVE_THREADPTR @@ -173,12 +157,14 @@ _id_ok: /* Stack frame pointer is the 7th argument to z_mrsh_*() * as ssf, and must be put on stack to be consumed. + * + * Subtract 16 bytes as stack needs to be 16-byte aligned. */ mov a3, a1 - addi a1, a1, -4 + addi a1, a1, -16 s32i a3, a1, 0 - l32i a3, a1, 4 + l32i a3, a1, 16 l32i a7, a3, ___xtensa_irq_bsa_t_a3_OFFSET @@ -195,7 +181,7 @@ _id_ok: * actual the stack frame. So restoration of registers * can be done properly when finishing syscalls. */ - addi a1, a1, 4 + addi a1, a1, 16 /* copy return value. Lets put it in the top of stack * because registers will be clobbered in @@ -204,25 +190,13 @@ _id_ok: l32i a3, a1, 0 s32i a6, a3, ___xtensa_irq_bsa_t_a2_OFFSET - j _syscall_returned - _syscall_returned: + /* Disable interrupts as we are restoring context. */ + rsil a0, 0xf + call0 xtensa_restore_high_regs - l32i a3, a1, ___xtensa_irq_bsa_t_sar_OFFSET - wsr a3, SAR -#if XCHAL_HAVE_LOOPS - l32i a3, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET - wsr a3, LBEG - l32i a3, a1, ___xtensa_irq_bsa_t_lend_OFFSET - wsr a3, LEND - l32i a3, a1, ___xtensa_irq_bsa_t_lcount_OFFSET - wsr a3, LCOUNT -#endif -#if XCHAL_HAVE_S32C1I - l32i a3, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET - wsr a3, SCOMPARE1 -#endif + ODD_REG_RESTORE a3, a1 #if XCHAL_HAVE_THREADPTR #ifdef CONFIG_THREAD_LOCAL_STORAGE @@ -231,18 +205,14 @@ _syscall_returned: add a0, a3, a0 movi a3, 1 s32i a3, a0, 0 -#else - rsr a3, ZSR_CPU - l32i a3, a3, ___cpu_t_current_OFFSET - wur.THREADPTR a3 #endif #endif /* XCHAL_HAVE_THREADPTR */ l32i a3, a1, ___xtensa_irq_bsa_t_ps_OFFSET - wsr.ps a3 + wsr.ZSR_EPS a3 l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET - wsr.epc1 a3 + wsr.ZSR_EPC a3 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET l32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET @@ -251,7 +221,7 @@ _syscall_returned: l32i a1, a1, ___xtensa_irq_bsa_t_scratch_OFFSET rsync - rfe + rfi ZSR_RFI_LEVEL _bad_syscall: movi a2, K_SYSCALL_BAD @@ -300,7 +270,11 @@ xtensa_userspace_enter: l32i a6, a1, 24 #ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP call4 xtensa_swap_update_page_tables +#else + SWAP_PAGE_TABLE a6, a3, a7 +#endif #endif #ifdef CONFIG_XTENSA_MPU call4 xtensa_mpu_map_write @@ -331,8 +305,11 @@ xtensa_userspace_enter: /* Go back to user stack */ l32i a1, a1, 4 + /* Disabling interrupts as we need to use ZSR_EPC and ZSR_EPS */ + rsil a0, 0xf + movi a0, z_thread_entry - wsr.epc2 a0 + wsr.ZSR_EPC a0 /* Configuring PS register. * We have to set callinc as well, since the called @@ -346,9 +323,9 @@ xtensa_userspace_enter: movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(1) #endif - wsr a0, EPS2 + wsr.ZSR_EPS a0 /* Wipe out a0 (thre is no return from this function */ movi a0, 0 - rfi 2 + rfi ZSR_RFI_LEVEL diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index 11b18013033c..c488aeee1ce0 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -153,9 +153,34 @@ _restore_context: l32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET wsr a0, ZSR_EPC + +#ifdef CONFIG_USERSPACE + /* When restoring context via xtensa_switch and + * returning from non-nested interrupts, we use + * the stashed PS value in the thread struct + * instead of the one in the thread stack. + * Both scenarios will have nested value of 0. + */ + rsr.ZSR_CPU a2 + l32i a0, a2, ___cpu_t_nested_OFFSET + bnez a0, _restore_ps_from_stack + + l32i a0, a2, ___cpu_t_current_OFFSET + l32i a0, a0, _thread_offset_to_return_ps + wsr a0, ZSR_EPS + + j _restore_ps_after + +_restore_ps_from_stack: +#endif + l32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET wsr a0, ZSR_EPS +#ifdef CONFIG_USERSPACE +_restore_ps_after: +#endif + #if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) FPU_REG_RESTORE #endif @@ -165,25 +190,8 @@ _restore_context: call0 _xtensa_hifi_load #endif - l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET - wsr a0, SAR -#if XCHAL_HAVE_LOOPS - l32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET - wsr a0, LBEG - l32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET - wsr a0, LEND - l32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET - wsr a0, LCOUNT -#endif -#if XCHAL_HAVE_S32C1I - l32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET - wsr a0, SCOMPARE1 -#endif -#if XCHAL_HAVE_THREADPTR && \ - (defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE)) - l32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET - wur a0, THREADPTR -#endif + ODD_REG_RESTORE a0, a1 + rsync l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET @@ -232,7 +240,35 @@ xtensa_arch_kernel_oops_epc: .global xtensa_switch .align 4 xtensa_switch: +#ifdef CONFIG_USERSPACE + entry a1, 32 + + s32i a4, a1, 0 + s32i a5, a1, 4 + s32i a6, a1, 8 + s32i a7, a1, 12 + + rsr a6, ZSR_CPU + l32i a6, a6, ___cpu_t_current_OFFSET +#ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + call4 xtensa_swap_update_page_tables +#else + SWAP_PAGE_TABLE a6, a4, a7 +#endif +#endif +#ifdef CONFIG_XTENSA_MPU + call4 xtensa_mpu_map_write +#endif + + l32i a7, a1, 12 + l32i a6, a1, 8 + l32i a5, a1, 4 + l32i a4, a1, 0 +#else entry a1, 16 +#endif + SPILL_ALL_WINDOWS addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF @@ -245,11 +281,27 @@ xtensa_switch: s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET - ODD_REG_SAVE + ODD_REG_SAVE a0, a1 + +#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) + FPU_REG_SAVE +#endif /* Stash our PS register contents and a "restore" PC. */ rsr a0, PS s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET + +#ifdef CONFIG_USERSPACE + /* Backtrack to the head of thread struct and + * then store the PS value to be restored in + * the architecture specific section. + * This will be used to restore PS instead of + * the one stashed inside stack. + */ + addi a3, a3, -___thread_t_switch_handle_OFFSET + s32i a0, a3, _thread_offset_to_return_ps +#endif + movi a0, _switch_restore_pc s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET @@ -260,10 +312,11 @@ xtensa_switch: /* Now the high registers */ call0 xtensa_save_high_regs -#ifdef CONFIG_KERNEL_COHERENCE +#if defined(CONFIG_KERNEL_COHERENCE) && !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) /* Flush the stack. The top of stack was stored for us by * arch_cohere_stacks(). It can be NULL for a dummy thread. */ + rsync rsr a0, ZSR_FLUSH beqz a0, noflush mov a3, a1 @@ -282,21 +335,6 @@ noflush: l32i a3, a2, ___xtensa_irq_bsa_t_a3_OFFSET s32i a1, a3, 0 -#ifdef CONFIG_USERSPACE - /* Switch page tables */ - rsr a6, ZSR_CPU - l32i a6, a6, ___cpu_t_current_OFFSET -#ifdef CONFIG_XTENSA_MMU - call4 xtensa_swap_update_page_tables -#endif -#ifdef CONFIG_XTENSA_MPU - call4 xtensa_mpu_map_write -#endif - - l32i a2, a3, 0 - l32i a2, a2, 0 -#endif - /* Switch stack pointer and restore. The jump to * _restore_context does not return as such, but we arrange * for the restored "next" address to be immediately after for diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 5e735dedffff..8e0641f9d4be 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -39,23 +39,119 @@ static ALWAYS_INLINE void arch_switch(void *switch_to, void **switched_from) } #ifdef CONFIG_KERNEL_COHERENCE +/** + * @brief Invalidate cache between two stack addresses. + * + * This invalidates the cache lines between two stack addresses, + * beginning with the cache line including the start address, up to + * but not including the cache line containing the end address. + * Not invalidating the last cache line is due to the usage in + * arch_cohere_stacks() where it invalidates the unused portion of + * stack. If the stack pointer happens to be in the middle of + * a cache line, the cache line containing the stack pointer + * address will be flushed, and then immediately invalidated. + * If we are swapping back into the same thread (e.g. after + * handling interrupt), that cache line, being invalidated, needs + * to be retrieved from main memory. This creates unnecessary + * data move between main memory and cache. + * + * @param s_addr Starting address of memory region to have cache invalidated. + * @param e_addr Ending address of memory region to have cache invalidated. + */ +static ALWAYS_INLINE void xtensa_cohere_stacks_cache_invd(size_t s_addr, size_t e_addr) +{ + const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE); + const size_t last = ROUND_DOWN(e_addr, XCHAL_DCACHE_LINESIZE); + size_t line; + + for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) { + __asm__ volatile("dhi %0, 0" :: "r"(line)); + } +} + +/** + * @brief Flush cache between two stack addresses. + * + * This flushes the cache lines between two stack addresses, + * beginning with the cache line including the start address, + * and ending with the cache line including the end address. + * Note that, contrary to xtensa_cohere_stacks_cache_invd(), + * the last cache line will be flushed instead of being + * ignored. + * + * @param s_addr Starting address of memory region to have cache invalidated. + * @param e_addr Ending address of memory region to have cache invalidated. + */ +static ALWAYS_INLINE void xtensa_cohere_stacks_cache_flush(size_t s_addr, size_t e_addr) +{ + const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE); + const size_t last = ROUND_UP(e_addr, XCHAL_DCACHE_LINESIZE); + size_t line; + + for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) { + __asm__ volatile("dhwb %0, 0" :: "r"(line)); + } +} + +/** + * @brief Flush and invalidate cache between two stack addresses. + * + * This flushes the cache lines between two stack addresses, + * beginning with the cache line including the start address, + * and ending with the cache line including the end address. + * Note that, contrary to xtensa_cohere_stacks_cache_invd(), + * the last cache line will be flushed and invalidated instead + * of being ignored. + * + * @param s_addr Starting address of memory region to have cache manipulated. + * @param e_addr Ending address of memory region to have cache manipulated. + */ +static ALWAYS_INLINE void xtensa_cohere_stacks_cache_flush_invd(size_t s_addr, size_t e_addr) +{ + const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE); + const size_t last = ROUND_UP(e_addr, XCHAL_DCACHE_LINESIZE); + size_t line; + + for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) { + __asm__ volatile("dhwbi %0, 0" :: "r"(line)); + } +} + static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, void *old_switch_handle, struct k_thread *new_thread) { +#ifdef CONFIG_SCHED_CPU_MASK_PIN_ONLY + ARG_UNUSED(old_thread); + ARG_UNUSED(old_switch_handle); + ARG_UNUSED(new_thread); + + /* This kconfig option ensures that a living thread will never + * be executed in a different CPU so we can safely return without + * invalidate and/or flush threads cache. + */ + return; +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ + +#if !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) int32_t curr_cpu = _current_cpu->id; size_t ostack = old_thread->stack_info.start; - size_t osz = old_thread->stack_info.size; + size_t oend = ostack + old_thread->stack_info.size; size_t osp = (size_t) old_switch_handle; size_t nstack = new_thread->stack_info.start; - size_t nsz = new_thread->stack_info.size; + size_t nend = nstack + new_thread->stack_info.size; size_t nsp = (size_t) new_thread->switch_handle; - int zero = 0; + uint32_t flush_end = 0; + +#ifdef CONFIG_USERSPACE + /* End of old_thread privileged stack. */ + void *o_psp_end = old_thread->arch.psp; +#endif - __asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(zero)); + __asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(flush_end)); if (old_switch_handle != NULL) { int32_t a0save; @@ -66,14 +162,6 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, : "=r"(a0save)); } - /* The following option ensures that a living thread will never - * be executed in a different CPU so we can safely return without - * invalidate and/or flush threads cache. - */ - if (IS_ENABLED(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) { - return; - } - /* The "live" area (the region between the switch handle, * which is the stack pointer, and the top of the stack * memory) of the inbound stack needs to be invalidated if we @@ -88,7 +176,7 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, * automatically overwritten as needed. */ if (curr_cpu != new_thread->arch.last_cpu) { - sys_cache_data_invd_range((void *)nsp, (nstack + nsz) - nsp); + xtensa_cohere_stacks_cache_invd(nsp, nend); } old_thread->arch.last_cpu = curr_cpu; @@ -116,8 +204,13 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, * to the stack top stashed in a special register. */ if (old_switch_handle != NULL) { - sys_cache_data_flush_range((void *)osp, (ostack + osz) - osp); - sys_cache_data_invd_range((void *)ostack, osp - ostack); +#ifdef CONFIG_USERSPACE + if (o_psp_end == NULL) +#endif + { + xtensa_cohere_stacks_cache_flush(osp, oend); + xtensa_cohere_stacks_cache_invd(ostack, osp); + } } else { /* When in a switch, our current stack is the outbound * stack. Flush the single line containing the stack @@ -128,13 +221,58 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, */ __asm__ volatile("mov %0, a1" : "=r"(osp)); osp -= 16; - sys_cache_data_flush_range((void *)osp, 1); - sys_cache_data_invd_range((void *)ostack, osp - ostack); + xtensa_cohere_stacks_cache_flush(osp, osp + 16); - uint32_t end = ostack + osz; +#ifdef CONFIG_USERSPACE + if (o_psp_end == NULL) +#endif + { + xtensa_cohere_stacks_cache_invd(ostack, osp); - __asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(end)); + flush_end = oend; + } } + +#ifdef CONFIG_USERSPACE + /* User threads need a bit more processing due to having + * privileged stack for handling syscalls. The privileged + * stack always immediately precedes the thread stack. + * + * Note that, with userspace enabled, we need to swap + * page table during context switch via function calls. + * This means that the stack is being actively used + * unlike the non-userspace case mentioned above. + * Therefore we need to set ZSR_FLUSH_STR to make sure + * we flush the cached data in the stack. + */ + if (o_psp_end != NULL) { + /* Start of old_thread privileged stack. + * + * struct xtensa_thread_stack_header wholly contains + * a array for the privileged stack, so we can use + * its size to calculate where the start is. + */ + size_t o_psp_start = (size_t)o_psp_end - sizeof(struct xtensa_thread_stack_header); + + if ((osp >= ostack) && (osp < oend)) { + /* osp in user stack. */ + xtensa_cohere_stacks_cache_invd(o_psp_start, osp); + + flush_end = oend; + } else if ((osp >= o_psp_start) && (osp < ostack)) { + /* osp in privileged stack. */ + xtensa_cohere_stacks_cache_flush(ostack, oend); + xtensa_cohere_stacks_cache_invd(o_psp_start, osp); + + flush_end = (size_t)old_thread->arch.psp; + } + } +#endif /* CONFIG_USERSPACE */ + + flush_end = ROUND_DOWN(flush_end, XCHAL_DCACHE_LINESIZE); + __asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(flush_end)); + +#endif /* !CONFIG_SCHED_CPU_MASK_PIN_ONLY */ } #endif diff --git a/arch/xtensa/include/offsets_short_arch.h b/arch/xtensa/include/offsets_short_arch.h index f19750dc0ac8..80ece2b1dee3 100644 --- a/arch/xtensa/include/offsets_short_arch.h +++ b/arch/xtensa/include/offsets_short_arch.h @@ -12,8 +12,33 @@ #define _thread_offset_to_psp \ (___thread_t_arch_OFFSET + ___thread_arch_t_psp_OFFSET) +#define _thread_offset_to_return_ps \ + (___thread_t_arch_OFFSET + ___thread_arch_t_return_ps_OFFSET) + #define _thread_offset_to_ptables \ (___thread_t_arch_OFFSET + ___thread_arch_t_ptables_OFFSET) + +#define _thread_offset_to_mem_domain \ + (___thread_t_mem_domain_info_OFFSET + ___mem_domain_info_t_mem_domain_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_asid \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_asid_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_ptevaddr \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptevaddr_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_ptepin_as \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_as_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_ptepin_at \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_at_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_vecpin_as \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_as_OFFSET) + +#define _k_mem_domain_offset_to_arch_reg_vecpin_at \ + (__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_at_OFFSET) + #endif /* CONFIG_USERSPACE */ #endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h index d5593d7adbc8..ac13a611c67f 100644 --- a/arch/xtensa/include/xtensa_asm2_context.h +++ b/arch/xtensa/include/xtensa_asm2_context.h @@ -80,6 +80,68 @@ #include #include +/* Stack needs to aligned on 16-bytes as mentioned on Xtensa ISA. + * So we pad _xtensa_irq_bsa_t to achieve that. The followings + * are see how much space is taken depending on features enabled. + */ + +#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) +# define _BSA_PADDING_FPU (sizeof(uintptr_t) * 18U) +#else +# define _BSA_PADDING_FPU (0) +#endif + +#if defined(CONFIG_XTENSA_HIFI_SHARING) +# define _BSA_PADDING_HIFI (XCHAL_CP1_SA_SIZE + XCHAL_CP1_SA_ALIGN) +#else +# define _BSA_PADDING_HIFI (0) +#endif + +#if XCHAL_HAVE_THREADPTR +# define _BSA_PADDING_THREADPTR (sizeof(uintptr_t)) +#else +# define _BSA_PADDING_THREADPTR (0) +#endif + +#if XCHAL_HAVE_S32C1I +# define _BSA_PADDING_S32C1I (sizeof(uintptr_t)) +#else +# define _BSA_PADDING_S32C1I (0) +#endif + +#if XCHAL_HAVE_LOOPS +# define _BSA_PADDING_LOOPS (sizeof(uintptr_t) * 3U) +#else +# define _BSA_PADDING_LOOPS (0) +#endif + +/* Must have fields regardless of features. */ +#define _BSA_PADDING_COMMON (sizeof(uintptr_t) * 12U) + +/* Raw size by adding up all the above. */ +#define _BSA_PADDING_BASE_SIZE \ + (_BSA_PADDING_FPU + \ + _BSA_PADDING_HIFI + \ + _BSA_PADDING_THREADPTR + \ + _BSA_PADDING_S32C1I + \ + _BSA_PADDING_LOOPS + \ + _BSA_PADDING_COMMON) + +/* Each stack frame always has a pointer to BSA so we add + * that (+4) to the BSA size before padding the BSA to have + * size aligned on 16 bytes. Each group of high registers to + * be saved (totally 3 groups) consists of 4 registers which + * are 16 bytes already. So each type of stack frame + * (A[3, 7, 11, 15]) do not need any further padding as long + * as the BSA struct is of correct size. + */ +#define _BSA_PADDING_PADDED_SIZE \ + ((((_BSA_PADDING_BASE_SIZE + 4) + 15) / 16 * 16) - 4) + +/* How many extra bytes needed. */ +#define _BSA_PADDING_NEEDED \ + (_BSA_PADDING_PADDED_SIZE - _BSA_PADDING_BASE_SIZE) + /** * Base Save Area (BSA) during interrupt. * @@ -147,6 +209,8 @@ struct xtensa_irq_base_save_area { uintptr_t a2; uintptr_t a3; + uintptr_t padding[_BSA_PADDING_NEEDED / sizeof(uintptr_t)]; + uintptr_t caller_a0; uintptr_t caller_a1; uintptr_t caller_a2; @@ -155,6 +219,16 @@ struct xtensa_irq_base_save_area { typedef struct xtensa_irq_base_save_area _xtensa_irq_bsa_t; +#undef _BSA_PADDING_NEEDED +#undef _BSA_PADDING_PADDED_SIZE +#undef _BSA_PADDING_BASE_SIZE +#undef _BSA_PADDING_COMMON +#undef _BSA_PADDING_LOOPS +#undef _BSA_PADDING_S32C1I +#undef _BSA_PADDING_THREADPTR +#undef _BSA_PADDING_HIFI +#undef _BSA_PADDING_FPU + /** * Raw interrupt stack frame. * diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index 150df82c35cb..d7799ac1125f 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -11,6 +11,7 @@ #include "xtensa_asm2_context.h" #include +#include /* Assembler header! This file contains macros designed to be included * only by the assembler. @@ -156,134 +157,111 @@ * ODD_REG_SAVE * * Stashes the oddball shift/loop context registers in the base save - * area pointed to by the current stack pointer. On exit, A0 will - * have been modified but A2/A3 have not, and the shift/loop - * instructions can be used freely (though note loops don't work in - * exceptions for other reasons!). + * area pointed to by the register specified by parameter BSA_PTR. + * On exit, the scratch register specified by parameter SCRATCH_REG + * will have been modified, and the shift/loop instructions can be + * used freely (though note loops don't work in exceptions for other + * reasons!). * * Does not populate or modify the PS/PC save locations. */ -.macro ODD_REG_SAVE - rsr.sar a0 - s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET +.macro ODD_REG_SAVE SCRATCH_REG, BSA_PTR + rsr.sar \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET #if XCHAL_HAVE_LOOPS - rsr.lbeg a0 - s32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET - rsr.lend a0 - s32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET - rsr.lcount a0 - s32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET + rsr.lbeg \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET + rsr.lend \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lend_OFFSET + rsr.lcount \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lcount_OFFSET #endif - rsr.exccause a0 - s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET + rsr.exccause \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_exccause_OFFSET #if XCHAL_HAVE_S32C1I - rsr.scompare1 a0 - s32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET + rsr.scompare1 \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_scompare1_OFFSET #endif #if XCHAL_HAVE_THREADPTR && \ (defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE)) - rur.THREADPTR a0 - s32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET -#endif -#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) - FPU_REG_SAVE + rur.THREADPTR \SCRATCH_REG + s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_threadptr_OFFSET #endif .endm -#ifdef CONFIG_XTENSA_MMU /* - * CALC_PTEVADDR_BASE + * ODD_REG_RESTORE * - * This calculates the virtual address of the first PTE page - * (PTEVADDR base, the one mapping 0x00000000) so that we can - * use this to obtain the virtual address of the PTE page we are - * interested in. This can be obtained via - * (1 << CONFIG_XTENSA_MMU_PTEVADDR_SHIFT). + * Restores the oddball shift/loop context registers in the base save + * area pointed to by the register specified by parameter BSA_PTR. + * On exit, the scratch register specified by parameter SCRATCH_REG + * will have been modified. * - * Note that this is done this way is to avoid any TLB - * miss if we are to use l32r to load the PTEVADDR base. - * If the page containing the PTEVADDR base address is - * not in TLB, we will need to handle the TLB miss which - * we are trying to avoid here. - * - * @param ADDR_REG Register to store the calculated - * PTEVADDR base address. - * - * @note The content of ADDR_REG will be modified. - * Save and restore it around this macro usage. + * Does not restore the PS/PC save locations. */ -.macro CALC_PTEVADDR_BASE ADDR_REG - movi \ADDR_REG, 1 - slli \ADDR_REG, \ADDR_REG, CONFIG_XTENSA_MMU_PTEVADDR_SHIFT +.macro ODD_REG_RESTORE SCRATCH_REG, BSA_PTR + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET + wsr.sar \SCRATCH_REG +#if XCHAL_HAVE_LOOPS + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET + wsr.lbeg \SCRATCH_REG + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lend_OFFSET + wsr.lend \SCRATCH_REG + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lcount_OFFSET + wsr.lcount \SCRATCH_REG +#endif + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_exccause_OFFSET + wsr.exccause \SCRATCH_REG +#if XCHAL_HAVE_S32C1I + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_scompare1_OFFSET + wsr.scompare1 \SCRATCH_REG +#endif +#if XCHAL_HAVE_THREADPTR && \ + (defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE)) + l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_threadptr_OFFSET + wur.THREADPTR \SCRATCH_REG +#endif + .endm +#if defined(CONFIG_XTENSA_MMU) && defined(CONFIG_USERSPACE) /* - * PRELOAD_PTEVADDR + * SWAP_PAGE_TABLE * - * This preloads the page table entries for a 4MB region to avoid TLB - * misses. This 4MB region is mapped via a page (4KB) of page table - * entries (PTE). Each entry is 4 bytes mapping a 4KB region. Each page, - * then, has 1024 entries mapping a 4MB region. Filling TLB entries is - * automatically done via hardware, as long as the PTE page associated - * with a particular address is also in TLB. If the PTE page is not in - * TLB, an exception will be raised that must be handled. This TLB miss - * is problematic when we are in the middle of dealing with another - * exception or handling an interrupt. So we need to put the PTE page - * into TLB by simply do a load operation. + * This swaps the page tables by using the pre-computed register values + * inside the architecture-specific memory domain struct. * - * @param ADDR_REG Register containing the target address - * @param PTEVADDR_BASE_REG Register containing the PTEVADDR base + * THREAD_PTR_REG is input containing pointer to the incoming thread struct. + * SC1_REG and SC2_REG are scratch registers. * - * @note Both the content of ADDR_REG will be modified. - * Save and restore it around this macro usage. + * Note that all THREAD_PTR_REG, SC1_REG and SC2_REG are all clobbered. + * Restore the thread pointer after this if necessary. */ -.macro PRELOAD_PTEVADDR ADDR_REG, PTEVADDR_BASE_REG - /* - * Calculate the offset to first PTE page of all memory. - * - * Every page (4KB) of page table entries contains - * 1024 entires (as each entry is 4 bytes). Each entry - * maps one 4KB page. So one page of entries maps 4MB of - * memory. - * - * 1. We need to find the virtual address of the PTE page - * having the page table entry mapping the address in - * register ADDR_REG. To do this, we first need to find - * the offset of this PTE page from the first PTE page - * (the one mapping memory 0x00000000): - * a. Find the beginning address of the 4KB page - * containing address in ADDR_REG. This can simply - * be done by discarding 11 bits (or shifting right - * and then left 12 bits). - * b. Since each PTE page contains 1024 entries, - * we divide the address obtained in step (a) by - * further dividing it by 1024 (shifting right and - * then left 10 bits) to obtain the offset of - * the PTE page. - * - * Step (a) and (b) can be obtained together so that - * we can shift right 22 bits, and then shift left - * 12 bits. - * - * 2. Once we have combine the results from step (1) and - * PTEVADDR_BASE_REG to get the virtual address of - * the PTE page. - * - * 3. Do a l32i to force the PTE page to be in TLB. - */ +.macro SWAP_PAGE_TABLE THREAD_PTR_REG, SC1_REG, SC2_REG + l32i \THREAD_PTR_REG, \THREAD_PTR_REG, _thread_offset_to_mem_domain + + j _swap_page_table_\@ + +.align 16 +_swap_page_table_\@: + l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptevaddr + l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_asid + wsr \SC1_REG, PTEVADDR + wsr \SC2_REG, RASID - /* Step 1 */ - srli \ADDR_REG, \ADDR_REG, 22 - slli \ADDR_REG, \ADDR_REG, 12 + l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptepin_as + l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptepin_at + wdtlb \SC2_REG, \SC1_REG - /* Step 2 */ - add \ADDR_REG, \ADDR_REG, \PTEVADDR_BASE_REG + l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_vecpin_as + l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_vecpin_at + wdtlb \SC2_REG, \SC1_REG - /* Step 3 */ - l32i \ADDR_REG, \ADDR_REG, 0 + isync .endm -#endif /* CONFIG_XTENSA_MMU */ + +#endif /* CONFIG_XTENSA_MMU && CONFIG_USERSPACE */ /* * CROSS_STACK_CALL @@ -353,16 +331,26 @@ * the context save handle in A1 as it's first argument. */ .macro CROSS_STACK_CALL - mov a6, a3 /* place "new sp" in the next frame's A2 */ - mov a10, a1 /* pass "context handle" in 2nd frame's A2 */ - mov a3, a1 /* stash it locally in A3 too */ - mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */ + /* Since accessing A4-A11 may trigger window overflows so + * we need to setup A0 and A1 correctly before putting + * the function arguments for the next two callx4 into + * A6, A10 and A11. So stach the "context handle" into + * ZSR_EPC, which is usable for now similar to ZSR_EPS. + */ + wsr.ZSR_EPC a1 + rsync /* Recover the interrupted SP from the BSA */ l32i a1, a1, 0 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF + mov a6, a3 /* place "new sp" in the next frame's A2 */ + + rsr.ZSR_EPC a3 /* restore saved "context handle" in A3 */ + mov a10, a3 /* pass "context handle" in 2nd frame's A2 */ + mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */ + call4 _xstack_call0_\@ mov a1, a3 /* restore original SP */ mov a2, a6 /* copy return value */ @@ -377,16 +365,50 @@ _xstack_call0_\@: mov a1, a2 rsr.ZSR_EPS a2 wsr.ps a2 - call4 _xstack_call1_\@ + +#ifdef CONFIG_USERSPACE + /* Save "context handle" in A3 as we need it to determine + * if we need to swap page table later. + */ + mov a3, a6 +#endif + + callx4 a7 /* call handler */ mov a2, a6 /* copy return value */ - retw -.align 4 -_xstack_call1_\@: - /* Remember the handler is going to do our ENTRY, so the - * handler pointer is still in A6 (not A2) even though this is - * after the second CALL4. + +#ifdef CONFIG_USERSPACE + rsil a6, XCHAL_NUM_INTLEVELS + + /* If "next" handle to be restored is the same as + * the current handle, there is no need to swap page + * tables or MPU entries since we will return to + * the same thread that was interrupted. + */ + beq a2, a3, _xstack_skip_table_swap_\@ + + /* Need to switch page tables because the "next" handle + * returned above is not the same handle as we started + * with. This means we are being restored to another + * thread. */ - jx a7 + rsr a6, ZSR_CPU + l32i a6, a6, ___cpu_t_current_OFFSET + +#ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + call4 xtensa_swap_update_page_tables +#else + SWAP_PAGE_TABLE a6, a3, a7 +#endif +#endif +#ifdef CONFIG_XTENSA_MPU + call4 xtensa_mpu_map_write +#endif + +_xstack_skip_table_swap_\@: +#endif /* CONFIG_USERSPACE */ + + retw _xstack_returned_\@: .endm @@ -409,7 +431,11 @@ _xstack_returned_\@: */ s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET - ODD_REG_SAVE + ODD_REG_SAVE a0, a1 + +#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) + FPU_REG_SAVE +#endif #if defined(CONFIG_XTENSA_HIFI_SHARING) call0 _xtensa_hifi_save /* Save HiFi registers */ @@ -430,6 +456,23 @@ _xstack_returned_\@: wur.THREADPTR a0 #endif /* XCHAL_HAVE_THREADPTR && CONFIG_USERSPACE */ + /* Setting up the cross stack call below has states where the + * resulting frames are invalid/non-reentrant, so we can't + * allow nested interrupts. But we do need EXCM unmasked, as + * we use CALL/ENTRY instructions in the process and need to + * handle exceptions to spill caller/interruptee frames. Use + * PS.INTLEVEL at maximum to mask all interrupts and stash the + * current value in our designated EPS register (which is + * guaranteed unused across the call) + */ + rsil a0, 0xf + + /* Since we are unmasking EXCM, we need to set RING bits to kernel + * mode, otherwise we won't be able to run the exception handler in C. + */ + movi a3, ~(PS_EXCM_MASK) & ~(PS_RING_MASK) + and a0, a0, a3 + #ifdef CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE /* Setting the interrupt mask to the max non-debug level @@ -437,12 +480,11 @@ _xstack_returned_\@: * high level interrupts until processing of that lower level * interrupt has completed. */ - rsr.ps a0 movi a3, ~(PS_INTLEVEL_MASK) and a0, a0, a3 movi a3, PS_INTLEVEL(ZSR_RFI_LEVEL) or a0, a0, a3 - wsr.ps a0 + wsr.ZSR_EPS a0 #else @@ -458,35 +500,20 @@ _xstack_returned_\@: * argument and expand two versions of this handler. An * optimization FIXME, I guess. */ - rsr.ps a0 movi a3, PS_INTLEVEL_MASK - and a0, a0, a3 - bnez a0, _not_l1 - rsr.ps a0 + and a3, a0, a3 + bnez a3, _not_l1 + + /* interrupt masking is zero, so no need to zero it before OR-ing. */ movi a3, PS_INTLEVEL(1) or a0, a0, a3 - wsr.ps a0 _not_l1: + wsr.ZSR_EPS a0 #endif /* CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE */ - /* Setting up the cross stack call below has states where the - * resulting frames are invalid/non-reentrant, so we can't - * allow nested interrupts. But we do need EXCM unmasked, as - * we use CALL/ENTRY instructions in the process and need to - * handle exceptions to spill caller/interruptee frames. Use - * PS.INTLEVEL at maximum to mask all interrupts and stash the - * current value in our designated EPS register (which is - * guaranteed unused across the call) - */ - rsil a0, 0xf - - /* Since we are unmasking EXCM, we need to set RING bits to kernel - * mode, otherwise we won't be able to run the exception handler in C. - */ - movi a3, ~(PS_EXCM_MASK) & ~(PS_RING_MASK) - and a0, a0, a3 - wsr.ZSR_EPS a0 + movi a3, PS_INTLEVEL(0xf) + or a0, a0, a3 wsr.ps a0 rsync @@ -536,52 +563,48 @@ _do_call_\@: */ beq a6, a1, _restore_\@ -#ifndef CONFIG_USERSPACE +#if !defined(CONFIG_KERNEL_COHERENCE) || \ + (defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) l32i a1, a1, 0 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF -#ifndef CONFIG_KERNEL_COHERENCE + /* When using coherence, the registers of the interrupted * context got spilled upstream in arch_cohere_stacks() */ SPILL_ALL_WINDOWS #endif - /* Restore A1 stack pointer from "next" handle. */ - mov a1, a6 -#else - /* With userspace, we cannot simply restore A1 stack pointer - * at this pointer because we need to swap page tables to - * the incoming thread, and we do not want to call that - * function with thread's stack. So we stash the new stack - * pointer into A2 first, then move it to A1 after we have - * swapped the page table. - */ - mov a2, a6 +#if defined(CONFIG_KERNEL_COHERENCE) && \ + defined(CONFIG_USERSPACE) && \ + !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) - /* Need to switch page tables because the "next" handle - * returned above is not the same handle as we started - * with. This means we are being restored to another - * thread. + /* With userspace enabled, we need to swap page table via function calls + * above after returning from syscall handler above in CROSS_STACK_CALL. + * This means that the stack is being actively used, and so we need to + * flush the cached data in stack. */ - rsr a6, ZSR_CPU - l32i a6, a6, ___cpu_t_current_OFFSET -#ifdef CONFIG_XTENSA_MMU - call4 xtensa_swap_update_page_tables -#endif -#ifdef CONFIG_XTENSA_MPU - call4 xtensa_mpu_map_write -#endif - l32i a1, a1, 0 - l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET - addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF + movi a2, 0 + xsr.ZSR_FLUSH a2 + beqz a2, _excint_noflush_\@ - SPILL_ALL_WINDOWS + rsr.ZSR_CPU a3 + l32i a3, a3, \NEST_OFF + bnez a3, _excint_noflush_\@ - /* Moved stashed stack pointer to A1 to restore stack. */ - mov a1, a2 -#endif + mov a3, a1 + +_excint_flushloop_\@: + dhwb a3, 0 + addi a3, a3, XCHAL_DCACHE_LINESIZE + blt a3, a2, _excint_flushloop_\@ + +_excint_noflush_\@: +#endif /* CONFIG_KERNEL_COHERENCE && CONFIG_USERSPACE && !CONFIG_SCHED_CPU_MASK_PIN_ONLY */ + + /* Restore A1 stack pointer from "next" handle. */ + mov a1, a6 _restore_\@: j _restore_context @@ -706,6 +729,25 @@ _Level\LVL\()Vector: s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET .endif +#ifdef CONFIG_USERSPACE + /* When restoring context via xtensa_switch and + * returning from non-nested interrupts, we will be + * using the stashed PS value in the thread struct + * instead of the one in the thread stack. Both of + * these scenarios will have nested value of 0. + * So when nested value is zero, we store the PS + * value into thread struct. + */ + rsr.ZSR_CPU a3 + l32i a2, a3, ___cpu_t_nested_OFFSET + bnez a2, _excint_skip_ps_save_to_thread_\LVL + + l32i a2, a3, ___cpu_t_current_OFFSET + s32i a0, a2, _thread_offset_to_return_ps + +_excint_skip_ps_save_to_thread_\LVL: +#endif + rsr.epc\LVL a0 s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET diff --git a/arch/xtensa/include/xtensa_mmu_priv.h b/arch/xtensa/include/xtensa_mmu_priv.h index 608cbac9c465..7cd51f132936 100644 --- a/arch/xtensa/include/xtensa_mmu_priv.h +++ b/arch/xtensa/include/xtensa_mmu_priv.h @@ -14,6 +14,7 @@ #include #include #include +#include /** * @defgroup xtensa_mmu_internal_apis Xtensa Memory Management Unit (MMU) Internal APIs @@ -363,6 +364,29 @@ static inline void xtensa_tlb_autorefill_invalidate(void) __asm__ volatile("isync"); } +/** + * @brief Invalidate all autorefill DTLB entries. + * + * This should be used carefully since all refill entries in the data + * TLBs are affected. The current stack page will be repopulated by + * this code as it returns. + */ +static inline void xtensa_dtlb_autorefill_invalidate(void) +{ + uint8_t way, i, entries; + + entries = BIT(XCHAL_DTLB_ARF_ENTRIES_LOG2); + + for (way = 0; way < XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS; way++) { + for (i = 0; i < entries; i++) { + uint32_t entry = way + (i << XTENSA_MMU_PTE_PPN_SHIFT); + + xtensa_dtlb_entry_invalidate(entry); + } + } + __asm__ volatile("isync"); +} + /** * @brief Set the page tables. * @@ -509,18 +533,22 @@ static inline void xtensa_dtlb_vaddr_invalidate(void *vaddr) /** * @brief Tell hardware to use a page table very first time after boot. - * - * @param l1_page Pointer to the page table to be used. */ -void xtensa_init_paging(uint32_t *l1_page); +void xtensa_mmu_init_paging(void); /** * @brief Switch to a new page table. * - * @param asid The ASID of the memory domain associated with the incoming page table. - * @param l1_page Page table to be switched to. + * @param domain Architecture-specific memory domain data. + */ +void xtensa_mmu_set_paging(struct arch_mem_domain *domain); + +/** + * @brief Computer the necessary register values when changing page tables. + * + * @param domain Architecture-specific memory domain data. */ -void xtensa_set_paging(uint32_t asid, uint32_t *l1_page); +void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain); /** * @} diff --git a/boards/01space/esp32c3_042_oled/doc/index.rst b/boards/01space/esp32c3_042_oled/doc/index.rst index 29fcfc786150..801e8651cfa6 100644 --- a/boards/01space/esp32c3_042_oled/doc/index.rst +++ b/boards/01space/esp32c3_042_oled/doc/index.rst @@ -34,31 +34,7 @@ It features: Supported Features ================== -The 01space ESP32C3 0.42 OLED board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+------------------+ -| DISPLAY | off-chip | display | -+-----------+------------+------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -91,6 +67,8 @@ retrieve those files. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Standalone application ====================== diff --git a/boards/96boards/stm32_sensor_mez/board.yml b/boards/96boards/stm32_sensor_mez/board.yml index 19d96543563a..4011ccbd2209 100644 --- a/boards/96boards/stm32_sensor_mez/board.yml +++ b/boards/96boards/stm32_sensor_mez/board.yml @@ -1,6 +1,6 @@ board: name: 96b_stm32_sensor_mez full_name: STM32 Sensor Mezzanine - vendor: st + vendor: 96boards socs: - name: stm32f446xx diff --git a/boards/Kconfig b/boards/Kconfig index 40e8e5006e12..71b3b9571ad2 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2,8 +2,7 @@ config BOARD string - # When using hw model v2, then the board is inherited from CMake. - default "$(BOARD)" if "$(HWM_SCHEME)" = "v2" + default "$(BOARD)" help This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). @@ -53,7 +52,7 @@ config NET_DRIVERS When building for a qemu target then NET_DRIVERS will be default enabled to allow for easy use of SLIP or PPP -rsource "Kconfig.$(HWM_SCHEME)" +rsource "Kconfig.v2" # Parse shields references # Don't do it as a menuconfig, as shield selection is a CMake feature. diff --git a/boards/Kconfig.v1 b/boards/Kconfig.v1 deleted file mode 100644 index c98bd27d2db8..000000000000 --- a/boards/Kconfig.v1 +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -# In HWMv1 the KCONFIG_BOARD_DIR points directly to the BOARD_DIR. -# Set the BOARD_DIR variable for backwards compatibility to legacy hardware model. -BOARD_DIR := $(KCONFIG_BOARD_DIR) - -choice - prompt "Board Selection" - -source "$(KCONFIG_BOARD_DIR)/Kconfig.board" - -endchoice diff --git a/boards/aconno/acn52832/board.cmake b/boards/aconno/acn52832/board.cmake index ddd57ab8839a..69caa8667e3a 100644 --- a/boards/aconno/acn52832/board.cmake +++ b/boards/aconno/acn52832/board.cmake @@ -2,5 +2,7 @@ board_runner_args(nrfjprog "--nrf-family=NRF52") board_runner_args(jlink "--device=nrf52" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/acrn/acrn/Kconfig b/boards/acrn/acrn/Kconfig index 7d7b97605a46..857bd3470750 100644 --- a/boards/acrn/acrn/Kconfig +++ b/boards/acrn/acrn/Kconfig @@ -1,17 +1,9 @@ -# Copyright (c) 2019-2024 Intel Corporation +# Copyright (c) 2019-2025 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 -config BOARD_ACRN +config ACRN_COMMON bool + default y if BOARD_ACRN || BOARD_ACRN_EHL_CRB || BOARD_ACRN_ADL_CRB select CPU_HAS_FPU select X86_64 - help - "ACRN User OS" - -config BOARD_ACRN_EHL_CRB - bool - select CPU_HAS_FPU - select X86_64 - help - "ACRN User OS on ElkhartLake CRB" diff --git a/boards/acrn/acrn/Kconfig.acrn_adl_crb b/boards/acrn/acrn/Kconfig.acrn_adl_crb new file mode 100644 index 000000000000..c105411cede5 --- /dev/null +++ b/boards/acrn/acrn/Kconfig.acrn_adl_crb @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN_ADL_CRB + select SOC_ATOM diff --git a/boards/acrn/acrn/Kconfig.defconfig b/boards/acrn/acrn/Kconfig.defconfig index 678c8a5e378f..dbc4a23333cc 100644 --- a/boards/acrn/acrn/Kconfig.defconfig +++ b/boards/acrn/acrn/Kconfig.defconfig @@ -5,6 +5,11 @@ config MP_MAX_NUM_CPUS default 2 -config HEAP_MEM_POOL_ADD_SIZE_ACPI +configdefault HEAP_MEM_POOL_ADD_SIZE_ACPI default 32768 - depends on ACPI + +configdefault MAIN_STACK_SIZE + default 32000 if ACPI + +configdefault SHELL_STACK_SIZE + default 32000 if SHELL && ACPI diff --git a/boards/acrn/acrn/acrn_adl_crb.dts b/boards/acrn/acrn/acrn_adl_crb.dts new file mode 100644 index 000000000000..064b9d46231f --- /dev/null +++ b/boards/acrn/acrn/acrn_adl_crb.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#define DT_DRAM_SIZE DT_SIZE_K(8192) +#define DT_DRAM_BASE 0 + +#include + +/ { + model = "ACRN"; + compatible = "acrn"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + }; + + chosen { + zephyr,sram = &dram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + pcie0: pcie0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pcie-controller"; + acpi-hid = "PNP0A03"; + ranges; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/acrn/acrn/acrn_adl_crb.yaml b/boards/acrn/acrn/acrn_adl_crb.yaml new file mode 100644 index 000000000000..4bb5438c97cd --- /dev/null +++ b/boards/acrn/acrn/acrn_adl_crb.yaml @@ -0,0 +1,11 @@ +identifier: acrn_adl_crb +name: ACRN on ADL configuration +type: mcu +arch: x86 +toolchain: + - zephyr +ram: 8192 +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/acrn/acrn/acrn_adl_crb_defconfig b/boards/acrn/acrn/acrn_adl_crb_defconfig new file mode 100644 index 000000000000..765fc7e30712 --- /dev/null +++ b/boards/acrn/acrn/acrn_adl_crb_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_X2APIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1500000000 +CONFIG_BUILD_OUTPUT_BIN=y +CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +CONFIG_KERNEL_VM_SIZE=0x5000000 +CONFIG_APIC_TSC_DEADLINE_TIMER=y +CONFIG_MP_MAX_NUM_CPUS=1 +CONFIG_ACPI=y +CONFIG_PCIE=y diff --git a/boards/acrn/acrn/board.yml b/boards/acrn/acrn/board.yml index dce367c0f96a..bb41da4f8288 100644 --- a/boards/acrn/acrn/board.yml +++ b/boards/acrn/acrn/board.yml @@ -2,10 +2,18 @@ boards: - name: acrn full_name: ACRN hypervisor + vendor: acrn socs: - name: atom - name: acrn_ehl_crb full_name: ACRN on EHL hypervisor + vendor: acrn socs: - - name: elkhart_lake + - name: atom + + - name: acrn_adl_crb + full_name: ACRN Hypervisor on ADL + vendor: acrn + socs: + - name: atom diff --git a/boards/actinius/icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi index 39616df663fc..b44370babb10 100644 --- a/boards/actinius/icarus/actinius_icarus_common.dtsi +++ b/boards/actinius/icarus/actinius_icarus_common.dtsi @@ -170,4 +170,4 @@ #include "feather_connector.dtsi" /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus/board.cmake b/boards/actinius/icarus/board.cmake index 9c0c33243af6..91aec43ebb51 100644 --- a/boards/actinius/icarus/board.cmake +++ b/boards/actinius/icarus/board.cmake @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi index 4d302d006fb6..bd692cdc9ead 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi @@ -157,4 +157,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_bee/board.cmake b/boards/actinius/icarus_bee/board.cmake index 9c0c33243af6..91aec43ebb51 100644 --- a/boards/actinius/icarus_bee/board.cmake +++ b/boards/actinius/icarus_bee/board.cmake @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi index 605b2bdd3e72..99eaab08dd3a 100644 --- a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi +++ b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi @@ -66,4 +66,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_som/board.cmake b/boards/actinius/icarus_som/board.cmake index 9c0c33243af6..91aec43ebb51 100644 --- a/boards/actinius/icarus_som/board.cmake +++ b/boards/actinius/icarus_som/board.cmake @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi index f084595540f1..c5ff38367b6f 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi @@ -159,4 +159,4 @@ neopixel_spi: &spi1 { #include "arduino_connector.dtsi" /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_som_dk/board.cmake b/boards/actinius/icarus_som_dk/board.cmake index 9c0c33243af6..91aec43ebb51 100644 --- a/boards/actinius/icarus_som_dk/board.cmake +++ b/boards/actinius/icarus_som_dk/board.cmake @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adafruit/feather_esp32s2/CMakeLists.txt b/boards/adafruit/feather_esp32s2/CMakeLists.txt new file mode 100644 index 000000000000..218a0602483a --- /dev/null +++ b/boards/adafruit/feather_esp32s2/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/adafruit/feather_esp32s2/Kconfig b/boards/adafruit/feather_esp32s2/Kconfig new file mode 100644 index 000000000000..272e4c39ee9f --- /dev/null +++ b/boards/adafruit/feather_esp32s2/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 + +config BOARD_NEEDS_LATE_HOOK + bool + default y if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE + select BOARD_LATE_INIT_HOOK diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 new file mode 100644 index 000000000000..5baed3c43d47 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S2 + select SOC_ESP32S2_R2 diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft new file mode 100644 index 000000000000..bdf0d84d47c5 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT + select SOC_ESP32S2_R2 diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse new file mode 100644 index 000000000000..1025c63cf4df --- /dev/null +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE + select SOC_ESP32S2_R2 diff --git a/boards/adafruit/feather_esp32s2/Kconfig.defconfig b/boards/adafruit/feather_esp32s2/Kconfig.defconfig new file mode 100644 index 000000000000..a2559a48619f --- /dev/null +++ b/boards/adafruit/feather_esp32s2/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE + +if DISPLAY + +choice ST7789V_PIXEL_FORMAT + default ST7789V_RGB565 +endchoice + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild b/boards/adafruit/feather_esp32s2/Kconfig.sysbuild similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild rename to boards/adafruit/feather_esp32s2/Kconfig.sysbuild diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi new file mode 100644 index 000000000000..bd19e0ddc449 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025 Philipp Steiner . + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + /* Debug TX (DBG) - This is the hardware UART debug pin */ + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_ws2812_led: spim3_ws2812_led { + group1 { + pinmux = ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts new file mode 100644 index 000000000000..4cf4d79c29a9 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "adafruit_feather_esp32s2_common.dtsi" +#include "feather_connector.dtsi" + +/ { + model = "Adafruit Feather ESP32-S2"; + compatible = "espressif,esp32s2"; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay new file mode 100644 index 000000000000..0fdd649728bd --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* + * On-board transistor powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + label = "I2C Power"; + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + startup-delay-us = <10>; + }; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml new file mode 100644 index 000000000000..7246420988f8 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml @@ -0,0 +1,20 @@ +identifier: adafruit_feather_esp32s2@B +name: Adafruit Feather ESP32-S2 Rev B +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma +vendor: adafruit +testing: + ignore_tags: + - bluetooth diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay new file mode 100644 index 000000000000..c8f08e5b3445 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* + * On-board regulator powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + label = "I2C Power"; + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10>; + }; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml new file mode 100644 index 000000000000..86ca59f5965d --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml @@ -0,0 +1,20 @@ +identifier: adafruit_feather_esp32s2@C +name: Adafruit Feather ESP32-S2 Rev C +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma +vendor: adafruit +testing: + ignore_tags: + - bluetooth diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi new file mode 100644 index 000000000000..ae0eaf92ade6 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "adafruit_feather_esp32s2-pinctrl.dtsi" +#include +#include +#include +#include +#include + +/ { + compatible = "espressif,esp32s2"; + + chosen { + zephyr,sram = &sram1; + /* + * uart1 is used as the default uart for zephyr,console and zephyr,shell, + * because USB-OTG is until now not supported and USB-CDC is not available + * for ESP32-S2. + * See issue #29394 - ESP32 development overview + * To use uart1 a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins. + * See feather_connector.dtsi + */ + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + led0 = &led0; + i2c-0 = &i2c0; + sw0 = &user_button; + led-strip = &led_strip; + watchdog0 = &wdt0; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0: led_0 { + label = "Red-LED"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + user_button: user_button { + label = "BOOT Button"; + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + neopixel_power_enable { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + line-idle-low; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + + /* WS2812 */ + reg = <0>; + spi-max-frequency = <6400000>; + chain-length = <1>; + spi-cpha; + spi-one-frame = ; /* 11110000: 625ns high and 625ns low */ + spi-zero-frame = ; /* 11000000: 312.5ns high and 937.5ns low */ + color-mapping = , + , + ; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig new file mode 100644 index 000000000000..d8fbaa879257 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts new file mode 100644 index 000000000000..114a2d9cb91d --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "adafruit_feather_esp32s2_common.dtsi" +#include "feather_connector_tft.dtsi" + +/ { + model = "Adafruit Feather ESP32-S2 TFT"; + compatible = "espressif,esp32s2"; + + chosen { + zephyr,display = &st7789v_tft; + }; + + aliases { + backlight = &led1; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led1: led_1 { + label = "TFT Backlight"; + gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * On-board regulator powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + label = "I2C Power"; + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10>; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_tft: st7789v_tft@0 { + compatible = "sitronix,st7789v"; + status = "disabled"; + + /* Also powered by i2c_reg */ + power-domains = <&i2c_reg>; + + mipi-max-frequency = ; + reg = <0>; + width = <135>; + height = <240>; + x-offset = <52>; + y-offset = <40>; + vcom = <0x20>; + gctrl = <0x35>; + vrhs = <0x0b>; + vdvs = <0x20>; + mdac = <0x08>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +&gpio0 { + status = "okay"; + + neopixel_power_enable { + gpio-hog; + gpios = <34 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml new file mode 100644 index 000000000000..99ca5778e7a0 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml @@ -0,0 +1,21 @@ +identifier: adafruit_feather_esp32s2_tft +name: Adafruit ESP32-S2 TFT Feather +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma + - display +vendor: adafruit +testing: + ignore_tags: + - bluetooth diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig new file mode 100644 index 000000000000..d8fbaa879257 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts new file mode 100644 index 000000000000..be28841df3a4 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "adafruit_feather_esp32s2_common.dtsi" +#include "feather_connector.dtsi" + +/ { + model = "Adafruit Feather ESP32-S2 TFT Reverse"; + compatible = "espressif,esp32s2"; + + chosen { + zephyr,display = &st7789v_tft; + }; + + aliases { + backlight = &led1; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led1: led_1 { + label = "TFT Backlight"; + gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + d1_button: d1_button { + label = "D1 Button"; + gpios = <&gpio0 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + d2_button: d2_button { + label = "D3 Button"; + gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + i2c_reg: i2c_reg { + label = "TFT I2C Power"; + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10>; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio1 40 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_tft: st7789v_tft@0 { + compatible = "sitronix,st7789v"; + status = "disabled"; + + /* Also powered by i2c_reg */ + power-domains = <&i2c_reg>; + + mipi-max-frequency = ; + reg = <0>; + width = <135>; + height = <240>; + x-offset = <52>; + y-offset = <40>; + vcom = <0x20>; + gctrl = <0x35>; + vrhs = <0x0b>; + vdvs = <0x20>; + mdac = <0x08>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +&pinctrl { + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; +}; + +&i2c0 { + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "disabled"; + reg = <0x36 >; + power-domains = <&i2c_reg>; + }; +}; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml new file mode 100644 index 000000000000..f5c673e211be --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml @@ -0,0 +1,22 @@ +identifier: adafruit_feather_esp32s2_tft_reverse/esp32s2 +name: Adafruit ESP32-S2 TFT Feather Reverse +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma + - display + - fuel_gauge +vendor: adafruit +testing: + ignore_tags: + - bluetooth diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig new file mode 100644 index 000000000000..d8fbaa879257 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s2/board.c b/boards/adafruit/feather_esp32s2/board.c new file mode 100644 index 000000000000..aa4053f60fa1 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/board.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + * + * Automatically turns on backlight if display is configured, i.e. display DT + * node has status okay. + */ + +#include +#include +#include + +#define DISPLAY_NODE DT_CHOSEN(zephyr_display) + +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) +static const struct gpio_dt_spec backlight = GPIO_DT_SPEC_GET(DT_ALIAS(backlight), gpios); +#endif + +void board_late_init_hook(void) +{ +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) + if (gpio_is_ready_dt(&backlight)) { + gpio_pin_configure_dt(&backlight, GPIO_OUTPUT_ACTIVE); + } +#endif +} diff --git a/boards/adafruit/feather_esp32s2/board.cmake b/boards/adafruit/feather_esp32s2/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/feather_esp32s2/board.yml b/boards/adafruit/feather_esp32s2/board.yml new file mode 100644 index 000000000000..fda3bf5e8556 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/board.yml @@ -0,0 +1,22 @@ +boards: +- name: adafruit_feather_esp32s2 + full_name: Adafruit Feather ESP32S2 + vendor: adafruit + socs: + - name: esp32s2 + revision: + format: "letter" + default: "C" + revisions: + - name: "B" + - name: "C" +- name: adafruit_feather_esp32s2_tft + full_name: Adafruit Feather ESP32S2 TFT + vendor: adafruit + socs: + - name: esp32s2 +- name: adafruit_feather_esp32s2_tft_reverse + full_name: Adafruit Feather ESP32S2 TFT Reverse + vendor: adafruit + socs: + - name: esp32s2 diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst new file mode 100644 index 000000000000..a5fb76324d98 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst @@ -0,0 +1,358 @@ +.. zephyr:board:: adafruit_feather_esp32s2 + +Overview +******** + +The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the +Feather standard layout, sharing peripheral placement with other devices labeled +as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module, +a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible +`STEMMA QT`_ connector for the I2C bus. + +Hardware +******** + +- ESP32-S2 mini module, featuring the 240MHz Tensilica processor +- 320KB SRAM, 4MB flash + 2MB PSRAM +- USB-C directly connected to the ESP32-S2 for USB +- LiPo connector and built-in battery charging when powered via USB-C +- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Built-in NeoPixel indicator RGB LED +- STEMMA QT connector for I2C devices, with switchable power for low-power mode + +.. note:: + + - The `Adafruit ESP32-S2 Feather with BME280 Sensor`_ is the same board as the + `Adafruit ESP32-S2 Feather`_ but with an already equipped BME280 Sensor, but is not + stated as a separate board, instead the BME280 needs to be added via a devicetree + overlay. All boards, except the `Adafruit ESP32-S2 Feather with BME280 Sensor`_ have a + space for it, but will not be shipped with. + - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the + now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + see which chip you have. + - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via + a devicetree overlay. + - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC + is not available. + - For the `Adafruit ESP32-S2 Feather`_ there are two different Revisions ``rev B`` and + ``rev C``. The ``rev C`` board has revised the power circuitry for the NeoPixel and I2C + QT port. Instead of a transistor the ``rev C`` has a LDO regulator. To enable the + NeoPixel and I2C QT port on ``rev B`` boards ``GPIO7`` (``i2c_reg``) needs to be set to + LOW and on ``rev C`` boards it needs to be set HIGH. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output + a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector. + +Connections and IOs +=================== + +The `Adafruit ESP32-S2 Feather`_ User Guide has detailed information about the board including +pinouts and the schematic. + +- `Adafruit ESP32-S2 Feather Pinouts`_ +- `Adafruit ESP32-S2 Feather Schematic`_ + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi binary blobs in order work. Run the command below +to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_espressif + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +**Rev B** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@B + :goals: build + :west-args: --sysbuild + :compact: + +**Rev C** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@C + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual: + +**Rev B** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@B + :goals: build + +**Rev C** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@C + :goals: build + +The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button. +When in the ROM bootloader, you can upload code and query the chip using ``west flash``. + + +**Rev B** + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@B + :goals: flash + +**Rev C** + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@C + :goals: flash + +After the flashing you will receive most likely this Error: + +.. code-block:: console + + WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0. + esptool.py can not exit the download mode over USB. To run the app, reset the chip manually. + To suppress this note, set --after option to 'no_reset'. + FATAL ERROR: command exited with status 1: ... + +As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message +can be ignored and the board needs to be reseted via the Reset-Button manually. + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has been manually reseted and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s2 + +Debugging +********* + +ESP32-S2 support on OpenOCD is available at `OpenOCD`_. + +ESP32-S2 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor +in `JTAG debugging for ESP32-S2`_. + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + +**Rev B** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@B + :goals: debug + +**Rev C** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2@C + :goals: debug + +Testing the On-Board-LED +************************ + +There is a sample available to verify that the LEDs on the board are +functioning correctly with Zephyr: + +**Rev B** + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_esp32s2@B + :goals: build flash + +**Rev C** + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_esp32s2@C + :goals: build flash + +Testing the NeoPixel +******************** + +There is a sample available to verify that the NeoPixel on the board are +functioning correctly with Zephyr: + +**Rev B** + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: adafruit_feather_esp32s2@B + :goals: build flash + +**Rev C** + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: adafruit_feather_esp32s2@C + :goals: build flash + +Testing the Fuel Gauge (MAX17048) +********************************* + +There is a sample available to verify that the MAX17048 fuel gauge on the board are +functioning correctly with Zephyr: + +.. note:: + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + to the MAX17048. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge/max17048/ + :board: adafruit_feather_esp32s2@C + :goals: build flash + +Testing Wi-Fi +************* + +There is a sample available to verify that the Wi-Fi on the board are +functioning correctly with Zephyr: + +.. note:: + The Prerequisites must be met before testing Wi-Fi. + +**Rev B** + + .. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: adafruit_feather_esp32s2@B + :goals: build flash + +**Rev C** + + .. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: adafruit_feather_esp32s2@C + :goals: build flash + +References +********** + +.. target-notes:: + +.. _`Adafruit ESP32-S2 Feather`: https://www.adafruit.com/product/5000 +.. _`Adafruit ESP32-S2 Feather with BME280 Sensor`: https://www.adafruit.com/product/5303 +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831 +.. _`Adafruit ESP32-S2 Feather Pinouts`: https://learn.adafruit.com/adafruit-esp32-s2-feather/pinouts +.. _`Adafruit ESP32-S2 Feather Schematic`: https://learn.adafruit.com/adafruit-esp32-s2-feather/downloads +.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic +.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst new file mode 100644 index 000000000000..6f44363ca4b5 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst @@ -0,0 +1,296 @@ +.. zephyr:board:: adafruit_feather_esp32s2_tft + +Overview +******** + +The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the +Feather standard layout, sharing peripheral placement with other devices labeled +as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module, +a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible +`STEMMA QT`_ connector for the I2C bus. + +Hardware +******** + +- ESP32-S2 mini module, featuring the 240MHz Tensilica processor +- 320KB SRAM, 4MB flash + 2MB PSRAM +- USB-C directly connected to the ESP32-S2 for USB +- LiPo connector and built-in battery charging when powered via USB-C +- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Charging indicator LED, user LED, reset and boot buttons. +- Built-in NeoPixel indicator RGB LED +- STEMMA QT connector for I2C devices, with switchable power for low-power mode +- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset + +.. note:: + + - The board has a space for a BME280, but will not be shipped with. + - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the + now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + see which chip you have. + - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via + a devicetree overlay. + - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC + is not available. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output + a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector. + +Connections and IOs +=================== + +The `Adafruit ESP32-S2 TFT Feather`_ User Guide has detailed information about the board including +pinouts and the schematic. + +- `Adafruit ESP32-S2 TFT Feather Pinouts`_ +- `Adafruit ESP32-S2 TFT Feather Schematic`_ + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi binary blobs in order work. Run the command below +to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_espressif + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft + :goals: build + +The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button. +When in the ROM bootloader, you can upload code and query the chip using ``west flash``. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft + :goals: flash + +After the flashing you will receive most likely this Error: + +.. code-block:: console + + WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0. + esptool.py can not exit the download mode over USB. To run the app, reset the chip manually. + To suppress this note, set --after option to 'no_reset'. + FATAL ERROR: command exited with status 1: ... + +As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message +can be ignored and the board needs to be reseted via the Reset-Button manually. + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has been manually reseted and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s2_tft + +Debugging +********* + +ESP32-S2 support on OpenOCD is available at `OpenOCD`_. + +ESP32-S2 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor +in `JTAG debugging for ESP32-S2`_. + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft + :goals: debug + +Testing the On-Board-LED +************************ + +There is a sample available to verify that the LEDs on the board are +functioning correctly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +Testing the NeoPixel +******************** + +There is a sample available to verify that the NeoPixel on the board are +functioning correctly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +Testing the TFT +*************** + +.. note:: + To activate the backlight of the display ``GPIO45`` (``backlight``) needs to be set to HIGH. + This will be done automatically via ``board_late_init_hook()``. + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +Testing the Fuel Gauge (MAX17048) +********************************* + +There is a sample available to verify that the MAX17048 fuel gauge on the board are +functioning correctly with Zephyr: + +.. note:: + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + to the MAX17048. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge/max17048/ + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +Testing Wi-Fi +************* + +There is a sample available to verify that the Wi-Fi on the board are +functioning correctly with Zephyr: + +.. note:: + The Prerequisites must be met before testing Wi-Fi. + +.. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +References +********** + +.. target-notes:: + +.. _`Adafruit ESP32-S2 TFT Feather`: https://www.adafruit.com/product/5300 +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831 +.. _`Adafruit ESP32-S2 TFT Feather Pinouts`: https://learn.adafruit.com/adafruit-esp32-s2-tft-feather/pinouts +.. _`Adafruit ESP32-S2 TFT Feather Schematic`: https://learn.adafruit.com/adafruit-esp32-s2-tft-feather/downloads +.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic +.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst new file mode 100644 index 000000000000..fcbb63522059 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst @@ -0,0 +1,293 @@ +.. zephyr:board:: adafruit_feather_esp32s2_tft_reverse + +Overview +******** + +The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the +Feather standard layout, sharing peripheral placement with other devices labeled +as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module, +a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible +`STEMMA QT`_ connector for the I2C bus. + +Hardware +******** + +- ESP32-S2 mini module, featuring the 240MHz Tensilica processor +- 320KB SRAM, 4MB flash + 2MB PSRAM +- USB-C directly connected to the ESP32-S2 for USB +- LiPo connector and built-in battery charging when powered via USB-C +- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Charging indicator LED, user LED, reset and boot buttons and has 2 additional buttons. +- Built-in NeoPixel indicator RGB LED +- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset. + +.. note:: + + - The board has a space for a BME280, but will not be shipped with. + - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via + a devicetree overlay. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output + a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector. + +Connections and IOs +=================== + +The `Adafruit ESP32-S2 Reverse TFT Feather`_ User Guide has detailed information about the board +including pinouts and the schematic. + +- `Adafruit ESP32-S2 Reverse TFT Feather Pinouts`_ +- `Adafruit ESP32-S2 Reverse TFT Feather Schematic`_ + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi binary blobs in order work. Run the command below +to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_espressif + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build + +The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button. +When in the ROM bootloader, you can upload code and query the chip using ``west flash``. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft_reverse + :goals: flash + +After the flashing you will receive most likely this Error: + +.. code-block:: console + + WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0. + esptool.py can not exit the download mode over USB. To run the app, reset the chip manually. + To suppress this note, set --after option to 'no_reset'. + FATAL ERROR: command exited with status 1: ... + +As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message +can be ignored and the board needs to be reseted via the Reset-Button manually. + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has been manually reseted and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s2_tft_reverse + +Debugging +********* + +ESP32-S2 support on OpenOCD is available at `OpenOCD`_. + +ESP32-S2 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor +in `JTAG debugging for ESP32-S2`_. + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s2_tft_reverse + :goals: debug + +Testing the On-Board-LED +************************ + +There is a sample available to verify that the LEDs on the board are +functioning correctly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build flash + +Testing the NeoPixel +******************** + +There is a sample available to verify that the NeoPixel on the board are +functioning correctly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build flash + +Testing the TFT +*************** + +There is a sample available to verify that the TFT on the board are +functioning correctly with Zephyr: + +.. note:: + To activated the backlight of the display ``GPIO45`` (``backlight``) needs to be set to HIGH. + This will be done automatically via ``board_late_init_hook()``. + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build flash + +Testing the Fuel Gauge (MAX17048) +********************************* + +There is a sample available to verify that the MAX17048 fuel gauge on the board are +functioning correctly with Zephyr: + +.. note:: + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + to the MAX17048. + +.. zephyr-app-commands:: + :zephyr-app: samples/fuel_gauge/max17048/ + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build flash + +Testing Wi-Fi +************* + +There is a sample available to verify that the Wi-Fi on the board are +functioning correctly with Zephyr: + +.. note:: + The Prerequisites must be met before testing Wi-Fi. + +.. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: adafruit_feather_esp32s2_tft_reverse + :goals: build flash + +References +********** + +.. target-notes:: + +.. _`Adafruit ESP32-S2 Reverse TFT Feather`: https://www.adafruit.com/product/5345 +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831 +.. _`Adafruit ESP32-S2 Reverse TFT Feather Pinouts`: https://learn.adafruit.com/esp32-s2-reverse-tft-feather/pinouts +.. _`Adafruit ESP32-S2 Reverse TFT Feather Schematic`: https://learn.adafruit.com/esp32-s2-reverse-tft-feather/downloads +.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic +.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2.webp new file mode 100644 index 000000000000..b63d6c73977c Binary files /dev/null and b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2.webp differ diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft.webp new file mode 100644 index 000000000000..a1b9d091218e Binary files /dev/null and b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft.webp differ diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp new file mode 100644 index 000000000000..8b607c89f858 Binary files /dev/null and b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp differ diff --git a/boards/adafruit/feather_esp32s2/feather_connector.dtsi b/boards/adafruit/feather_esp32s2/feather_connector.dtsi new file mode 100644 index 000000000000..f4bfbc1c3b57 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/feather_connector.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Richard Osterloh + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = + <0 0 &gpio0 18 0>, /* A0 */ + <1 0 &gpio0 17 0>, /* A1 */ + <2 0 &gpio0 16 0>, /* A2 */ + <3 0 &gpio0 15 0>, /* A3 */ + <4 0 &gpio0 14 0>, /* A4 */ + <5 0 &gpio0 8 0>, /* A5 */ + <6 0 &gpio1 36 0>, /* SCK */ + <7 0 &gpio1 35 0>, /* MOSI */ + <8 0 &gpio1 37 0>, /* MISO */ + <9 0 &gpio1 38 0>, /* RX */ + <10 0 &gpio1 39 0>, /* TX */ + <11 0 &gpio1 43 0>, /* DB */ + <12 0 &gpio1 3 0>, /* SDA */ + <13 0 &gpio1 4 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart1 {}; +feather_i2c: &i2c0 {}; +feather_spi: &spi2 {}; diff --git a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi new file mode 100644 index 000000000000..a593471c7879 --- /dev/null +++ b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Richard Osterloh + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = + <0 0 &gpio0 18 0>, /* A0 */ + <1 0 &gpio0 17 0>, /* A1 */ + <2 0 &gpio0 16 0>, /* A2 */ + <3 0 &gpio0 15 0>, /* A3 */ + <4 0 &gpio0 14 0>, /* A4 */ + <5 0 &gpio0 8 0>, /* A5 */ + <6 0 &gpio1 36 0>, /* SCK */ + <7 0 &gpio1 35 0>, /* MOSI */ + <8 0 &gpio1 37 0>, /* MISO */ + <9 0 &gpio0 2 0>, /* RX */ + <10 0 &gpio0 1 0>, /* TX */ + <11 0 &gpio1 43 0>, /* DB */ + <12 0 &gpio1 42 0>, /* SDA */ + <13 0 &gpio1 41 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart1 {}; +feather_i2c: &i2c0 {}; +feather_spi: &spi2 {}; diff --git a/boards/adafruit/feather_esp32s2/support/openocd.cfg b/boards/adafruit/feather_esp32s2/support/openocd.cfg new file mode 100644 index 000000000000..2f740b4a36ab --- /dev/null +++ b/boards/adafruit/feather_esp32s2/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/adafruit/feather_esp32s3/Kconfig b/boards/adafruit/feather_esp32s3/Kconfig new file mode 100644 index 000000000000..e56e7f846c47 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/Kconfig @@ -0,0 +1,10 @@ +# Adafruit Feather ESP32-S3 board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_PROCPU + default 256 if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3 b/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3 new file mode 100644 index 000000000000..a96fe9293082 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3 @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S3 + select SOC_ESP32S3_WROOM_N8 + select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3/Kconfig.sysbuild b/boards/adafruit/feather_esp32s3/Kconfig.sysbuild new file mode 100644 index 000000000000..8d3acb9e11d7 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi new file mode 100644 index 000000000000..dc41eaae5412 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = ; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts new file mode 100644 index 000000000000..8b9f9953792e --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "adafruit_feather_esp32s3-pinctrl.dtsi" + +/ { + model = "Adafruit Feather ESP32S3 APPCPU"; + compatible = "adafruit,feather_esp32s3", "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml new file mode 100644 index 000000000000..329bcd7fa92c --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_feather_esp32s3/esp32s3/appcpu +name: Adafruit Feather ESP32-S3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig new file mode 100644 index 000000000000..9abf2ff0430a --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts new file mode 100644 index 000000000000..b745820ddaa0 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "feather_connector.dtsi" +#include "adafruit_feather_esp32s3-pinctrl.dtsi" + +/ { + model = "Adafruit Feather ESP32S3 PROCPU"; + compatible = "adafruit,feather_esp32s3", "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + uart-0 = &uart0; + sw0 = &button0; + led0 = &led0; + led-strip = &led_strip; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * The neopixel on this board has its positive side hooked up to a GPIO + * pin rather than a positive voltage rail to save on power. + */ + neopixel_pwr: neopixel_pwr { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + /* + * On-board regulator powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&usb_serial { + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "okay"; + reg = <0x36>; + + /* + * The MAX17048 itself is directly powered by the battery, not + * through the on-board regulator. However using this device + * requires I2C pull-ups powered by the regulator. + */ + power-domains = <&i2c_reg>; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + /* Workaround to support WS2812 driver */ + line-idle-low; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + power-domains = <&neopixel_pwr>; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* WS2812 */ + chain-length = <1>; + spi-cpha; + spi-one-frame = <0xf0>; /* 625 ns high and 625 ns low */ + spi-zero-frame = <0xc0>; /* 312.5 ns high and 937.5 ns low */ + color-mapping = ; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml new file mode 100644 index 000000000000..6ca1ba6ae3c1 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: adafruit_feather_esp32s3/esp32s3/procpu +name: Adafruit Feather ESP32-S3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input + - feather_serial + - feather_i2c + - feather_spi +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig new file mode 100644 index 000000000000..d789bab1824a --- /dev/null +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3/board.cmake b/boards/adafruit/feather_esp32s3/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/adafruit/feather_esp32s3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/feather_esp32s3/board.yml b/boards/adafruit/feather_esp32s3/board.yml new file mode 100644 index 000000000000..89db0bb116cc --- /dev/null +++ b/boards/adafruit/feather_esp32s3/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_esp32s3 + full_name: Adafruit Feather ESP32S3 + vendor: adafruit + socs: + - name: esp32s3 diff --git a/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp b/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp new file mode 100644 index 000000000000..5d6575dca117 Binary files /dev/null and b/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp differ diff --git a/boards/adafruit/feather_esp32s3/doc/index.rst b/boards/adafruit/feather_esp32s3/doc/index.rst new file mode 100644 index 000000000000..17332ba68fab --- /dev/null +++ b/boards/adafruit/feather_esp32s3/doc/index.rst @@ -0,0 +1,281 @@ +.. zephyr:board:: adafruit_feather_esp32s3 + +Overview +******** + +The Adafruit Feather ESP32-S3 is an ESP32-S3 development board in the Feather +standard layout, sharing peripheral placement with other devices labeled as +Feathers or FeatherWings. The board is equipped with an ESP32-S3 mini module, a +LiPo battery charger, a fuel gauge, a USB-C and Qwiic/STEMMA-QT connector. For +more information, check `Adafruit Feather ESP32-S3`_. + +Hardware +******** + +- ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor + (Tensilica LX7), running at up to 240MHz +- 512KB SRAM and either 8MB flash or 4MB flash + 2MB PSRAM, depending on the + module variant +- USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging +- LiPo connector and built-in battery charging when powered via USB-C +- MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Charging indicator LED, user LED, reset and boot buttons +- Built-in NeoPixel indicator RGB LED +- STEMMA QT connector for I2C devices, with switchable power for low-power mode + +Asymmetric Multiprocessing (AMP) +================================ + +The ESP32-S3 SoC allows 2 different applications to be executed in asymmetric +multiprocessing. Due to its dual-core architecture, each core can be enabled to +execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP +framework. See :zephyr:code-sample-category:`ipc` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +The current ``adafruit_feather_esp32s3`` board supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +The `Adafruit Feather ESP32-S3 User Guide`_ has detailed information about the +board including `pinouts`_ and the `schematic`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the +command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +=================== + +Simple boot +----------- + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +------------------ + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` +documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly +possible. For that reason, images can be build one at a time using traditional +build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``adafruit_feather_esp32s3`` board +. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s3 + +Debugging +========= + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. Download +and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Adafruit Feather ESP32-S3`: + https://www.adafruit.com/product/5323 + +.. _`OpenOCD`: + https://github.com/openocd-org/openocd + +.. _`JTAG debugging for ESP32-S3`: + https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ + +.. _Adafruit Feather ESP32-S3 User Guide: + https://learn.adafruit.com/adafruit-esp32-s3-feather + +.. _pinouts: + https://learn.adafruit.com/adafruit-esp32-s3-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-esp32-s3-feather/downloads + +.. _ESP32-S3 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf + +.. _ESP32 Technical Reference Manual: + https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/adafruit/feather_esp32s3/feather_connector.dtsi b/boards/adafruit/feather_esp32s3/feather_connector.dtsi new file mode 100644 index 000000000000..49671be660cd --- /dev/null +++ b/boards/adafruit/feather_esp32s3/feather_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 Richard Osterloh + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 18 0>, /* A0 */ + <1 0 &gpio0 17 0>, /* A1 */ + <2 0 &gpio0 16 0>, /* A2 */ + <3 0 &gpio0 15 0>, /* A3 */ + <4 0 &gpio0 14 0>, /* A4 */ + <5 0 &gpio0 8 0>, /* A5 */ + <6 0 &gpio1 36 0>, /* SCK */ + <7 0 &gpio1 35 0>, /* MOSI */ + <8 0 &gpio1 37 0>, /* MISO */ + <9 0 &gpio1 38 0>, /* RX */ + <10 0 &gpio1 39 0>, /* TX */ + <11 0 &gpio1 44 0>, /* DB */ + <12 0 &gpio0 3 0>, /* SDA */ + <13 0 &gpio0 4 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart1 {}; +feather_i2c: &i2c0 {}; +feather_spi: &spi2 {}; diff --git a/boards/adafruit/feather_esp32s3/support/openocd.cfg b/boards/adafruit/feather_esp32s3/support/openocd.cfg new file mode 100644 index 000000000000..2f740b4a36ab --- /dev/null +++ b/boards/adafruit/feather_esp32s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt b/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt new file mode 100644 index 000000000000..218a0602483a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig b/boards/adafruit/feather_esp32s3_tft/Kconfig new file mode 100644 index 000000000000..86f1012ae0d9 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/Kconfig @@ -0,0 +1,10 @@ +# Adafruit Feather ESP32S3 board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU + default 256 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft new file mode 100644 index 000000000000..cd78387ff887 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT + select SOC_ESP32S3_WROOM_N8 + select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig b/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig new file mode 100644 index 000000000000..2c3e9c9cfa76 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Leon Rinkel +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU + +if DISPLAY + +config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT + select BOARD_LATE_INIT_HOOK + +choice ST7789V_PIXEL_FORMAT + default ST7789V_RGB565 +endchoice + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_PROCPU diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild b/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild new file mode 100644 index 000000000000..8d3acb9e11d7 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi new file mode 100644 index 000000000000..0cf040eeb87d --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = ; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts new file mode 100644 index 000000000000..f4662f4b0a3e --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "adafruit_feather_esp32s3_tft-pinctrl.dtsi" + +/ { + model = "Adafruit Feather ESP32S3 TFT APPCPU"; + compatible = "adafruit,feather_esp32s3_tft", "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml new file mode 100644 index 000000000000..baed9f8ff70d --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_feather_esp32s3_tft/esp32s3/appcpu +name: Adafruit Feather ESP32-S3 TFT APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig new file mode 100644 index 000000000000..9abf2ff0430a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts new file mode 100644 index 000000000000..b09b6262aa1e --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "feather_connector.dtsi" +#include "adafruit_feather_esp32s3_tft-pinctrl.dtsi" + +/ { + model = "Adafruit Feather ESP32S3 TFT PROCPU"; + compatible = "adafruit,feather_esp32s3_tft", "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v_tft; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + uart-0 = &uart0; + sw0 = &button0; + led0 = &led0; + led-strip = &led_strip; + backlight = &led1; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + led1: led_1 { + gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * The neopixel on this board has its positive side hooked up to a GPIO + * pin rather than a positive voltage rail to save on power. + */ + neopixel_pwr: neopixel_pwr { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio1 34 GPIO_ACTIVE_HIGH>; + }; + + /* + * On-board regulator powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_tft: st7789v_tft@0 { + compatible = "sitronix,st7789v"; + status = "disabled"; + + /* Also powered by i2c_reg */ + power-domains = <&i2c_reg>; + + mipi-max-frequency = ; + reg = <0>; + width = <135>; + height = <240>; + x-offset = <52>; + y-offset = <40>; + vcom = <0x20>; + gctrl = <0x35>; + vrhs = <0x0b>; + vdvs = <0x20>; + mdac = <0x08>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +&usb_serial { + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "okay"; + reg = <0x36>; + + /* + * The MAX17048 itself is directly powered by the battery, not + * through the on-board regulator. However using this device + * requires I2C pull-ups powered by the regulator. + */ + power-domains = <&i2c_reg>; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + /* Workaround to support WS2812 driver */ + line-idle-low; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + power-domains = <&neopixel_pwr>; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* WS2812 */ + chain-length = <1>; + spi-cpha; + spi-one-frame = <0xf0>; /* 625 ns high and 625 ns low */ + spi-zero-frame = <0xc0>; /* 312.5 ns high and 937.5 ns low */ + color-mapping = ; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml new file mode 100644 index 000000000000..bed1ac8ba70f --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml @@ -0,0 +1,23 @@ +identifier: adafruit_feather_esp32s3_tft/esp32s3/procpu +name: Adafruit Feather ESP32-S3 TFT PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input + - feather_serial + - feather_i2c + - feather_spi + - display +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig new file mode 100644 index 000000000000..d789bab1824a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3_tft/board.c b/boards/adafruit/feather_esp32s3_tft/board.c new file mode 100644 index 000000000000..88aa3b0b3544 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/board.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Automatically turns on backlight if display is configured, i.e. display DT + * node has status okay. + */ + +#include +#include +#include + +#define DISPLAY_NODE DT_CHOSEN(zephyr_display) + +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) +static const struct gpio_dt_spec backlight = GPIO_DT_SPEC_GET(DT_ALIAS(backlight), gpios); +#endif + +void board_late_init_hook(void) +{ +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) + if (gpio_is_ready_dt(&backlight)) { + gpio_pin_configure_dt(&backlight, GPIO_OUTPUT_ACTIVE); + } +#endif +} diff --git a/boards/adafruit/feather_esp32s3_tft/board.cmake b/boards/adafruit/feather_esp32s3_tft/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/feather_esp32s3_tft/board.yml b/boards/adafruit/feather_esp32s3_tft/board.yml new file mode 100644 index 000000000000..86f7b9293c89 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_esp32s3_tft + full_name: Adafruit Feather ESP32S3 TFT + vendor: adafruit + socs: + - name: esp32s3 diff --git a/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp b/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp new file mode 100644 index 000000000000..796170908e7e Binary files /dev/null and b/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp differ diff --git a/boards/adafruit/feather_esp32s3_tft/doc/index.rst b/boards/adafruit/feather_esp32s3_tft/doc/index.rst new file mode 100644 index 000000000000..f46daa99688a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/doc/index.rst @@ -0,0 +1,284 @@ +.. zephyr:board:: adafruit_feather_esp32s3_tft + +Overview +******** + +The Adafruit Feather ESP32-S3 TFT is an ESP32-S3 development board in the +Feather standard layout, sharing peripheral placement with other devices labeled +as Feathers or FeatherWings. The board is equipped with an ESP32-S3 mini module, +a LiPo battery charger, a fuel gauge, a USB-C and Qwiic/STEMMA-QT connector. +Compared to the base model, this TFT variant additionally comes with a 240x135 +pixel IPS TFT color display. For more information, check +`Adafruit Feather ESP32-S3 TFT`_. + +Hardware +******** + +- ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor + (Tensilica LX7), running at up to 240MHz +- 512KB SRAM and either 8MB flash or 4MB flash + 2MB PSRAM, depending on the + module variant +- USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging +- LiPo connector and built-in battery charging when powered via USB-C +- MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Charging indicator LED, user LED, reset and boot buttons +- Built-in NeoPixel indicator RGB LED +- STEMMA QT connector for I2C devices, with switchable power for low-power mode +- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset + +Asymmetric Multiprocessing (AMP) +================================ + +The ESP32-S3 SoC allows 2 different applications to be executed in asymmetric +multiprocessing. Due to its dual-core architecture, each core can be enabled to +execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP +framework. See :zephyr:code-sample-category:`ipc` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +The current ``adafruit_feather_esp32s3_tft`` board supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +The `Adafruit Feather ESP32-S3 TFT User Guide`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the +command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +=================== + +Simple boot +----------- + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +------------------ + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` +documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly +possible. For that reason, images can be build one at a time using traditional +build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``adafruit_feather_esp32s3_tft`` +board. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s3_tft + +Debugging +========= + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. Download +and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Adafruit Feather ESP32-S3 TFT`: + https://www.adafruit.com/product/5483 + +.. _`OpenOCD`: + https://github.com/openocd-org/openocd + +.. _`JTAG debugging for ESP32-S3`: + https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ + +.. _Adafruit Feather ESP32-S3 TFT User Guide: + https://learn.adafruit.com/adafruit-esp32-s3-tft-feather + +.. _pinouts: + https://learn.adafruit.com/adafruit-esp32-s3-tft-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-esp32-s3-tft-feather/downloads + +.. _ESP32-S3 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf + +.. _ESP32 Technical Reference Manual: + https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi new file mode 100644 index 000000000000..9a4dd731e8ca --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 Richard Osterloh + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 18 0>, /* A0 */ + <1 0 &gpio0 17 0>, /* A1 */ + <2 0 &gpio0 16 0>, /* A2 */ + <3 0 &gpio0 15 0>, /* A3 */ + <4 0 &gpio0 14 0>, /* A4 */ + <5 0 &gpio0 8 0>, /* A5 */ + <6 0 &gpio1 36 0>, /* SCK */ + <7 0 &gpio1 35 0>, /* MOSI */ + <8 0 &gpio1 37 0>, /* MISO */ + <9 0 &gpio0 2 0>, /* RX */ + <10 0 &gpio0 1 0>, /* TX */ + <11 0 &gpio1 44 0>, /* DB */ + <12 0 &gpio1 42 0>, /* SDA */ + <13 0 &gpio1 41 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart1 {}; +feather_i2c: &i2c0 {}; +feather_spi: &spi2 {}; diff --git a/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg new file mode 100644 index 000000000000..2f740b4a36ab --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst index 20d1cd4750ab..69abd4bb9acc 100644 --- a/boards/adafruit/feather_m0_basic_proto/doc/index.rst +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -23,35 +23,7 @@ Hardware Supported Features ================== -The adafruit_feather_m0_basic_proto board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -96,6 +68,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible SAM-BA bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst index 7a3e9fc78bf5..1e85f48b1f54 100644 --- a/boards/adafruit/feather_m0_lora/doc/index.rst +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -24,37 +24,7 @@ Hardware Supported Features ================== -The adafruit_feather_m0_lora board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| RADIO | SPI | LoRa radio | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -105,6 +75,8 @@ version, 433MHz or 900MHz is supported. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Adafruit Feather M0 with LoRa ships with a BOSSA compatible SAM-BA bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/feather_m4_express/doc/index.rst b/boards/adafruit/feather_m4_express/doc/index.rst index a4178626eeec..a44c75808aa6 100644 --- a/boards/adafruit/feather_m4_express/doc/index.rst +++ b/boards/adafruit/feather_m4_express/doc/index.rst @@ -23,39 +23,7 @@ Hardware Supported Features ================== -The ``adafruit_feather_m4_express`` board target supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Unique 128 bit serial number | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig`. +.. zephyr:board-supported-hw:: Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set @@ -105,6 +73,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Feather ships with a the BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/feather_nrf52840/doc/index.rst b/boards/adafruit/feather_nrf52840/doc/index.rst index 6f2477e673ff..b136a30ba49f 100644 --- a/boards/adafruit/feather_nrf52840/doc/index.rst +++ b/boards/adafruit/feather_nrf52840/doc/index.rst @@ -58,43 +58,7 @@ Hardware Supported Features ================== -The Adafruit Feather nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -129,6 +93,8 @@ Push buttons Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adafruit/feather_stm32f405/doc/index.rst b/boards/adafruit/feather_stm32f405/doc/index.rst index 0cc6c327760f..656f96f8a8f9 100644 --- a/boards/adafruit/feather_stm32f405/doc/index.rst +++ b/boards/adafruit/feather_stm32f405/doc/index.rst @@ -26,29 +26,7 @@ Hardware Supported Features ================== -The Adafruit Feather STM32F405 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| USB | on-chip | USB device | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -86,6 +64,8 @@ dedicated to the 2 MB SPI Flash chip. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + DFU-Util programming is supported through Zephyr by default. Set up of the built in DFU-Util bootloader is possible by following the `instructions on the Learn website`_. diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst index 4bab88899672..d85b2e922e02 100644 --- a/boards/adafruit/grand_central_m4_express/doc/index.rst +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -21,37 +21,7 @@ Hardware Supported Features ================== -The adafruit_grand_central_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | SysTick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports, User LED | -+-----------+------------+------------------------------------------+ -| UART | on-chip | Serial ports, Console | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | SPI ports, microSDHC slot | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -95,6 +65,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Grand Central ships with a BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/itsybitsy/board.cmake b/boards/adafruit/itsybitsy/board.cmake index 6366e4775ecc..54b79bdf74b4 100644 --- a/boards/adafruit/itsybitsy/board.cmake +++ b/boards/adafruit/itsybitsy/board.cmake @@ -3,6 +3,7 @@ include(${ZEPHYR_BASE}/boards/common/bossac.board.cmake) board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst index 3fbcb918adb4..3dac6fea3b86 100644 --- a/boards/adafruit/itsybitsy/doc/index.rst +++ b/boards/adafruit/itsybitsy/doc/index.rst @@ -40,45 +40,7 @@ Hardware Supported Features ================== -The Adafruit ItsyBitsy nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -124,6 +86,9 @@ your board. The button and LED definitions can be found in Programming and Debugging ************************* + +.. zephyr:board-supported-runners:: + The ItsyBitsy ships with the BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst index 31e19cb8a992..19b5cdf29066 100644 --- a/boards/adafruit/itsybitsy_m4_express/doc/index.rst +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -22,41 +22,7 @@ Hardware Supported Features ================== -The adafruit_itsybitsy_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Unique 128 bit serial number | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`. +.. zephyr:board-supported-hw:: Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set @@ -106,6 +72,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adafruit/kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst index f1b5d998dc83..0db8c71653e1 100644 --- a/boards/adafruit/kb2040/doc/index.rst +++ b/boards/adafruit/kb2040/doc/index.rst @@ -27,54 +27,7 @@ Hardware Supported Features ================== -The adafruit_kb2040 board configuration supports the following -hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - NVIC - - N/A - - :dtcompatible:`arm,v6m-nvic` - * - UART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`raspberrypi,pico-gpio` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`raspberrypi,pico-adc` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`snps,designware-i2c` - * - SPI - - :kconfig:option:`CONFIG_SPI` - - :dtcompatible:`raspberrypi,pico-spi` - * - USB Device - - :kconfig:option:`CONFIG_USB_DEVICE_STACK` - - :dtcompatible:`raspberrypi,pico-usbd` - * - HWINFO - - :kconfig:option:`CONFIG_HWINFO` - - N/A - * - Watchdog Timer (WDT) - - :kconfig:option:`CONFIG_WATCHDOG` - - :dtcompatible:`raspberrypi,pico-watchdog` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`raspberrypi,pico-pwm` - * - Flash - - :kconfig:option:`CONFIG_FLASH` - - :dtcompatible:`raspberrypi,pico-flash` - * - Clock controller - - :kconfig:option:`CONFIG_CLOCK_CONTROL` - - :dtcompatible:`raspberrypi,pico-clock-controller` - * - UART (PIO) - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart-pio` +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -99,6 +52,8 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adafruit/macropad_rp2040/doc/index.rst b/boards/adafruit/macropad_rp2040/doc/index.rst index 7f2e78418cd8..74f9e14fa1d5 100644 --- a/boards/adafruit/macropad_rp2040/doc/index.rst +++ b/boards/adafruit/macropad_rp2040/doc/index.rst @@ -30,63 +30,13 @@ Hardware Supported Features ****************** -The ``adafruit_macropad_rp2040`` board target supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - NVIC - - N/A - - :dtcompatible:`arm,v6m-nvic` - * - UART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`raspberrypi,pico-gpio` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`raspberrypi,pico-adc` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`snps,designware-i2c` - * - SPI - - :kconfig:option:`CONFIG_SPI` - - :dtcompatible:`raspberrypi,pico-spi` - * - USB Device - - :kconfig:option:`CONFIG_USB_DEVICE_STACK` - - :dtcompatible:`raspberrypi,pico-usbd` - * - HWINFO - - :kconfig:option:`CONFIG_HWINFO` - - N/A - * - Watchdog Timer (WDT) - - :kconfig:option:`CONFIG_WATCHDOG` - - :dtcompatible:`raspberrypi,pico-watchdog` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`raspberrypi,pico-pwm` - * - Flash - - :kconfig:option:`CONFIG_FLASH` - - :dtcompatible:`raspberrypi,pico-flash-controller` - * - UART (PIO) - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart-pio` - * - Display - - :kconfig:option:`CONFIG_DISPLAY` - - :dtcompatible:`sinowealth,sh1106` - * - LED Strip (12 pixels) - - :kconfig:option:`CONFIG_LED_STRIP` - - :dtcompatible:`worldsemi,ws2812-rpi_pico-pio` - * - Rotary Encoder - - :kconfig:option:`CONFIG_INPUT` - - :dtcompatible:`gpio-qdec` +.. zephyr:board-supported-hw:: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``adafruit_macropad_rp2040`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/adafruit/nrf52_adafruit_feather/board.cmake b/boards/adafruit/nrf52_adafruit_feather/board.cmake index 4ddbcf66fbee..ca3935224642 100644 --- a/boards/adafruit/nrf52_adafruit_feather/board.cmake +++ b/boards/adafruit/nrf52_adafruit_feather/board.cmake @@ -2,6 +2,7 @@ board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52832" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst index c84bc73f62bd..4e318acd7935 100644 --- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -35,29 +35,7 @@ Hardware Supported Features ================== -The nRF52 Adafruit Feather board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTT | on-chip | console | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -80,6 +58,8 @@ Push buttons Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The ``nrf52_adafruit_feather`` board is available in two different versions: - `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay index ac1ec4af1b19..58eaee33a2b5 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay @@ -27,8 +27,7 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; #include diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts index ac757645e5b5..5d8b14a96a61 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts @@ -42,6 +42,15 @@ zephyr,code = ; }; }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 7 0>, + <1 0 &gpio1 8 0>; + }; }; &usb_serial { diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay index 5ab0be63c3ff..cd9ca5f1dcf0 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay @@ -27,8 +27,7 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; #include diff --git a/boards/adafruit/qt_py_esp32s3/doc/index.rst b/boards/adafruit/qt_py_esp32s3/doc/index.rst index 1c1f6e04eeec..8ad715a673c0 100644 --- a/boards/adafruit/qt_py_esp32s3/doc/index.rst +++ b/boards/adafruit/qt_py_esp32s3/doc/index.rst @@ -32,47 +32,7 @@ numerous peripherals. Supported Features ================== -Current Zephyr's Adafruit QT Py ESP32-S3 board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Prerequisites ------------- @@ -91,6 +51,8 @@ command below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index 3f87e4188b22..a6eaf30bbe6c 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -27,6 +27,15 @@ watchdog0 = &wdt0; led-strip = &ws2812; }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 23 0>, + <1 0 &gpio0 22 0>; + }; }; &flash0 { diff --git a/boards/adafruit/qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst index 0db8b4e40348..253ab615ac29 100644 --- a/boards/adafruit/qt_py_rp2040/doc/index.rst +++ b/boards/adafruit/qt_py_rp2040/doc/index.rst @@ -27,51 +27,7 @@ Hardware Supported Features ================== -The adafruit_qt_py_rp2040 board configuration supports the following -hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - NVIC - - N/A - - :dtcompatible:`arm,v6m-nvic` - * - UART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`raspberrypi,pico-gpio` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`raspberrypi,pico-adc` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`snps,designware-i2c` - * - SPI - - :kconfig:option:`CONFIG_SPI` - - :dtcompatible:`raspberrypi,pico-spi` - * - USB Device - - :kconfig:option:`CONFIG_USB_DEVICE_STACK` - - :dtcompatible:`raspberrypi,pico-usbd` - * - HWINFO - - :kconfig:option:`CONFIG_HWINFO` - - N/A - * - Watchdog Timer (WDT) - - :kconfig:option:`CONFIG_WATCHDOG` - - :dtcompatible:`raspberrypi,pico-watchdog` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`raspberrypi,pico-pwm` - * - Flash - - :kconfig:option:`CONFIG_FLASH` - - :dtcompatible:`raspberrypi,pico-flash` - * - UART (PIO) - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`raspberrypi,pico-uart-pio` +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -98,6 +54,8 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst index 224f9aa4c6de..ceaa0fd0ca2b 100644 --- a/boards/adafruit/trinket_m0/doc/index.rst +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -21,35 +21,7 @@ Hardware Supported Features ================== -The adafruit_trinket_m0 board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -98,6 +70,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Trinket M0 ships the BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl b/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl new file mode 100644 index 000000000000..b8b2e0fed816 --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl @@ -0,0 +1,7 @@ +# AD-SWIOT1L-SL board configuration + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_AD_SWIOT1L_SL + select SOC_MAX32650 diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts new file mode 100644 index 000000000000..d46ad87c1cf9 --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices AD-SWIOT1L-SL"; + compatible = "adi,ad_swiot1l_sl"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + + led2: led_2 { + gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml new file mode 100644 index 000000000000..495481a989db --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml @@ -0,0 +1,13 @@ +identifier: ad_swiot1l_sl +name: ad_swiot1l_sl +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial +ram: 1024 +flash: 3072 diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig new file mode 100644 index 000000000000..9428e5334a08 --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/ad_swiot1l_sl/board.cmake b/boards/adi/ad_swiot1l_sl/board.cmake new file mode 100644 index 000000000000..716d81214611 --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MAX32650" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/ad_swiot1l_sl/board.yml b/boards/adi/ad_swiot1l_sl/board.yml new file mode 100644 index 000000000000..f458ef3b9e89 --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: ad_swiot1l_sl + full_name: AD-SWIOT1L-SL + vendor: adi + socs: + - name: max32650 diff --git a/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp b/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp new file mode 100644 index 000000000000..6b734dc80b45 Binary files /dev/null and b/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp differ diff --git a/boards/adi/ad_swiot1l_sl/doc/index.rst b/boards/adi/ad_swiot1l_sl/doc/index.rst new file mode 100644 index 000000000000..42ef89a467ff --- /dev/null +++ b/boards/adi/ad_swiot1l_sl/doc/index.rst @@ -0,0 +1,107 @@ +.. zephyr:board:: ad_swiot1l_sl + +Overview +******** +The AD-SWIOT1L-SL is a complete hardware and software platform for prototyping intelligent, +secure, network-capable field devices, with applications in factory automation, process +control, and intelligent buildings. + +The Zephyr port is running on the MAX32650 MCU. + +Hardware +******** + +- MAX32650 MCU: + + - Ultra-Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 Processor with FPU + - SmartDMA Provides Background Memory Transfers with Programmable Data Processing + - 120MHz High-Speed and 50MHz Low-Power Oscillators + - 7.3728MHz Low-Power Oscillators + - 32.768kHz and RTC Clock (Requires External Crystal) + - 8kHz, Always-On, Ultra-Low-Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM + - 104μW/MHz Executing from Cache at 1.1V + - Five Low-Power Modes: Active, Sleep, Background, Deep Sleep, and Backup + - 1.8V and 3.3V I/O with No Level Translators + + - Scalable Cached External Memory Interfaces: + + - 120MB/s HyperBus/Xccela DDR Interface + - SPIXF/SPIXR for External Flash/RAM Expansion + - 240Mbps SDHC/eMMC/SDIO/microSD Interface + + - Optimal Peripheral Mix Provides Platform Scalability + + - 16-Channel DMA + - Three SPI Master (60MHz)/Slave (48MHz) + - One QuadSPI Master (60MHz)/Slave (48MHz) + - Up to Three 4Mbaud UARTs with Flow Control + - Two 1MHz I2C Master/Slave + - I2S Slave + - Four-Channel, 7.8ksps, 10-Bit Delta-Sigma ADC + - USB 2.0 Hi-Speed Device Interface with PHY + - 16 Pulse Train Generators + - Six 32-Bit Timers with 8mA High Drive + - 1-Wire® Master + + - Trust Protection Unit (TPU) for IP/Data Security + + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Memory Decryption Integrity Unit, Secure Boot ROM + +- External devices connected to the AD-SWIOT1L-SL: + + - On-Board HyperRAM + - On-Board QSPI Flash + - MAXQ1065 Ultralow Power Cryptographic Controller with ChipDNA + - ADIN1110 Robust, Industrial, Low Power 10BASE-T1L Ethernet MAC-PHY + - 2-Pin external power supply terminal block (24V DC) + - ADP1032 high performance, isolated micropower management unit (PMU) + - SWD 10-Pin Header + - On-Board 3.3V, 1.8V, and 1.1V voltage regulators + - AD74413R Quad-channel, Software Configurable I/O + - MAX14906 Quad-channel, Industrial Digital I/O + - Two general-purpose LEDs + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== +The MAX32650 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable + +Debugging +========= +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `AD-SWIOT1L-SL web page`_ + +.. _AD-SWIOT1L-SL web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-SWIOT1L-SL.html diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index 4de11b92848b..f291e50a8068 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -82,6 +83,37 @@ <20 0 &gpio2 17 0>, /* D14 */ <21 0 &gpio2 18 0>; /* D15 */ }; + + pmod_header: pmod-header { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 0 0>, /* IO1/CS */ + <1 0 &gpio1 1 0>, /* IO2/MOSI */ + <2 0 &gpio1 2 0>, /* IO3/MISO */ + <3 0 &gpio1 3 0>, /* IO4/SCK */ + <4 0 &gpio2 21 0>, /* IO5/INT */ + <5 0 &gpio1 6 0>, /* IO6/RESET */ + <6 0 &gpio1 4 0>, /* IO7/CS2 */ + <7 0 &gpio1 5 0>; /* IO8/CS3 */ + }; + + sdram1: sdram1@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_M(64)>; + zephyr,memory-region = "SDRAM1"; + }; + + sdram2: sdram2@70000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x70000000 DT_SIZE_M(64)>; + zephyr,memory-region = "SDRAM2"; + }; }; &clk_ipo { @@ -227,3 +259,52 @@ pmod_spi: &spi4 { pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>; pinctrl-names = "default"; }; + +&hpb { + pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_cs1n_p1_17 &hyp_rwds_p1_14 + &hyp_d0_p1_12 &hyp_d1_p1_15 + &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 + &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; + pinctrl-names = "default"; + enable-emcc; + + mem@0 { + reg = <0>; + base-address = <0x60000000>; + device-type = ; + + latency-cycles = ; + read-cs-high = ; + write-cs-high = ; + read-cs-setup = ; + write-cs-setup = ; + read-cs-hold = ; + write-cs-hold = ; + + /* CR0 settings. Key setting is enabling 6-clock latency, since + * HPB doesn't support 7-clock latency which is default + */ + config-regs = <0x1000>; + config-reg-vals = <0x801F>; + }; + + mem@1 { + reg = <1>; + base-address = <0x70000000>; + device-type = ; + + latency-cycles = ; + read-cs-high = ; + write-cs-high = ; + read-cs-setup = ; + write-cs-setup = ; + read-cs-hold = ; + write-cs-hold = ; + + /* CR0 settings. Key setting is enabling 6-clock latency, since + * HPB doesn't support 7-clock latency which is default + */ + config-regs = <0x1000>; + config-reg-vals = <0x801F>; + }; +}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml index bf6486d175b3..ba9f690d0549 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.yaml +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -11,11 +11,13 @@ supported: - arduino_serial - arduino_spi - pmod_spi + - pmod_gpio - gpio - serial - spi - trng - counter - w1 + - memc ram: 1024 flash: 3072 diff --git a/boards/adi/apard32690/doc/index.rst b/boards/adi/apard32690/doc/index.rst index edd879bd3ddc..318d34b361e9 100644 --- a/boards/adi/apard32690/doc/index.rst +++ b/boards/adi/apard32690/doc/index.rst @@ -87,32 +87,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on APARD32690. - -+-----------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+------------------------------------+ -| ADIN1110 | spi | ADIN1110 10BASE-T1L mac/phy | -+-----------+------------+------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+------------------------------------+ - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -182,6 +157,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst index 4f38e78faf0f..ed1db60a4ee0 100644 --- a/boards/adi/eval_adin1110ebz/doc/index.rst +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -38,43 +38,7 @@ https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide Supported Features ================== -The ADI adi_eval_adin1110ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN1110 | spi | adin1110 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ -| ADT7422 | i2c | temperature sensor | -+--------------+------------+-------------------------------------+ -| ISS66WVE4M16 | fmc | 8MB PSRAM | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - :zephyr_file:`boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -119,6 +83,8 @@ to a FT232, so available through Micro USB connector. Default settings are 11520 Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst index 7579c85b0cd2..9c65a86ce369 100644 --- a/boards/adi/eval_adin2111ebz/doc/index.rst +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -46,39 +46,7 @@ https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide Supported Features ================== -The ADI adi_eval_adin2111ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN2111 | spi | adin2111 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - :zephyr_file:`boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -120,6 +88,8 @@ Same UART1 TX and RX cmos signals are available before the FT232, at P9 connecto Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32650evkit/Kconfig.max32650evkit b/boards/adi/max32650evkit/Kconfig.max32650evkit new file mode 100644 index 000000000000..accb9f0e0f31 --- /dev/null +++ b/boards/adi/max32650evkit/Kconfig.max32650evkit @@ -0,0 +1,7 @@ +# MAX32650EVKIT boards configuration + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32650EVKIT + select SOC_MAX32650 diff --git a/boards/adi/max32650evkit/board.cmake b/boards/adi/max32650evkit/board.cmake new file mode 100644 index 000000000000..716d81214611 --- /dev/null +++ b/boards/adi/max32650evkit/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MAX32650" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32650evkit/board.yml b/boards/adi/max32650evkit/board.yml new file mode 100644 index 000000000000..24e70315fb5e --- /dev/null +++ b/boards/adi/max32650evkit/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32650evkit + full_name: MAX32650EVKIT + vendor: adi + socs: + - name: max32650 diff --git a/boards/adi/max32650evkit/doc/img/max32650evkit.webp b/boards/adi/max32650evkit/doc/img/max32650evkit.webp new file mode 100644 index 000000000000..1300e5e44b91 Binary files /dev/null and b/boards/adi/max32650evkit/doc/img/max32650evkit.webp differ diff --git a/boards/adi/max32650evkit/doc/index.rst b/boards/adi/max32650evkit/doc/index.rst new file mode 100644 index 000000000000..d66d875a782c --- /dev/null +++ b/boards/adi/max32650evkit/doc/index.rst @@ -0,0 +1,103 @@ +.. zephyr:board:: max32650evkit + +Overview +******** +The MAX32650 evaluation kit (EV kit) provides a platform for evaluating the +capabilities of the MAX32650 ultra-low power memory-scalable microcontroller +designed specifically for high performance battery powered applications. + +The Zephyr port is running on the MAX32650 MCU. + +Hardware +******** + +- MAX32650 MCU: + + - Ultra Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 with FPU + - SmartDMA Provides Background Memory Transfers with Programmable Data Processing + - 120MHz High-Speed and 50MHz Low-Power Oscillators + - 7.3728MHz Low Power Oscillators + - 32.768kHz and RTC Clock (Requires External Crystal) + - 8kHz, Always-on, Ultra-Low-Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM + - 104µW/MHz Executing from Cache at 1.1V + - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup + - 1.8V and 3.3V I/O with No Level Translators + - Programming and Debugging + + - Scalable Cached External Memory Interfaces + + - 120MB/s HyperBus/Xccela DDR Interface + - SPIXF/SPIXR for External Flash/RAM Expansion + - 240Mbps SDHC/eMMC/SDIO/microSD Interface + + - Optimal Peripheral Mix Provides Platform Scalability + + - 16-Channel DMA + - Three SPI Master (60MHz)/Slave (48MHz) + - One QuadSPI Master (60MHz)/Slave (48MHz) + - Up to Three 4Mbaud UARTs with Flow Control + - Two 1MHz I2C Master/Slave + - I2S Slave + - Four-Channel, 7.8ksps, 10-bit Delta-Sigma ADC + - USB 2.0 Hi-Speed Device Interface with PHY + - 16 Pulse Train Generators + - Six 32-bit Timers with 8mA Hi-Drive + - 1-Wire® Master + + - Trust Protection Unit (TPU) for IP/Data and Security + + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Memory Decryption Integrity Unit, Secure Boot ROM + +- External devices connected to the MAX32650EVKIT: + + - 3.5in 320 x 240 Color TFT Display + - 64MB HyperRAM + - 64MB XIP Flash + - 1MB XIP RAM + - USB 2.0 Micro B + - Two General-Purpose LEDs and Two GeneralPurpose Pushbutton Switches + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== +The MAX32650 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable + +Debugging +========= +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32650EVKIT web page`_ + +.. _MAX32650EVKIT web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html diff --git a/boards/adi/max32650evkit/max32650evkit.dts b/boards/adi/max32650evkit/max32650evkit.dts new file mode 100644 index 000000000000..48d8e177a890 --- /dev/null +++ b/boards/adi/max32650evkit/max32650evkit.dts @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32650EVKIT"; + compatible = "adi,max32650evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + + led2: led_2 { + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio2 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + + pb2: pb2 { + gpios = <&gpio2 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_scl_p2_8 &i2c0_sda_p2_7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi2_mosi_p2_4 &spi2_miso_p2_3 &spi2_sck_p2_2 &spi2_ss0_p2_5>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32650evkit/max32650evkit.yaml b/boards/adi/max32650evkit/max32650evkit.yaml new file mode 100644 index 000000000000..21b8ce3bfa00 --- /dev/null +++ b/boards/adi/max32650evkit/max32650evkit.yaml @@ -0,0 +1,19 @@ +identifier: max32650evkit +name: max32650evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial + - spi + - i2c + - dma + - watchdog + - counter + - rtc_counter +ram: 1024 +flash: 3072 diff --git a/boards/adi/max32650evkit/max32650evkit_defconfig b/boards/adi/max32650evkit/max32650evkit_defconfig new file mode 100644 index 000000000000..9428e5334a08 --- /dev/null +++ b/boards/adi/max32650evkit/max32650evkit_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32650fthr/Kconfig.max32650fthr b/boards/adi/max32650fthr/Kconfig.max32650fthr new file mode 100644 index 000000000000..cf8acafe85d8 --- /dev/null +++ b/boards/adi/max32650fthr/Kconfig.max32650fthr @@ -0,0 +1,7 @@ +# MAX32650FTHR board configuration + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32650FTHR + select SOC_MAX32650 diff --git a/boards/adi/max32650fthr/board.cmake b/boards/adi/max32650fthr/board.cmake new file mode 100644 index 000000000000..716d81214611 --- /dev/null +++ b/boards/adi/max32650fthr/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MAX32650" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32650fthr/board.yml b/boards/adi/max32650fthr/board.yml new file mode 100644 index 000000000000..46dee2be2339 --- /dev/null +++ b/boards/adi/max32650fthr/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32650fthr + full_name: MAX32650FTHR + vendor: adi + socs: + - name: max32650 diff --git a/boards/adi/max32650fthr/doc/img/max32650fthr.webp b/boards/adi/max32650fthr/doc/img/max32650fthr.webp new file mode 100644 index 000000000000..065de009e8cf Binary files /dev/null and b/boards/adi/max32650fthr/doc/img/max32650fthr.webp differ diff --git a/boards/adi/max32650fthr/doc/index.rst b/boards/adi/max32650fthr/doc/index.rst new file mode 100644 index 000000000000..de4a139081d9 --- /dev/null +++ b/boards/adi/max32650fthr/doc/index.rst @@ -0,0 +1,102 @@ +.. zephyr:board:: max32650fthr + +Overview +******** +The MAX32650FTHR evaluation kit provides a platform for evaluating the capabilities +of the MAX32650 ultra-low-power memory-scalable microcontroller designed specifically +for high-performance, battery-powered applications. + +The Zephyr port is running on the MAX32650 MCU. + +Hardware +******** + +- MAX32650 MCU: + + - Ultra Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 with FPU + - SmartDMA Provides Background Memory Transfers with Programmable Data Processing + - 120MHz High-Speed and 50MHz Low-Power Oscillators + - 7.3728MHz Low Power Oscillators + - 32.768kHz and RTC Clock (Requires External Crystal) + - 8kHz, Always-on, Ultra-Low-Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM + - 104µW/MHz Executing from Cache at 1.1V + - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup + - 1.8V and 3.3V I/O with No Level Translators + - Programming and Debugging + + - Scalable Cached External Memory Interfaces + + - 120MB/s HyperBus/Xccela DDR Interface + - SPIXF/SPIXR for External Flash/RAM Expansion + - 240Mbps SDHC/eMMC/SDIO/microSD Interface + + - Optimal Peripheral Mix Provides Platform Scalability + + - 16-Channel DMA + - Three SPI Master (60MHz)/Slave (48MHz) + - One QuadSPI Master (60MHz)/Slave (48MHz) + - Up to Three 4Mbaud UARTs with Flow Control + - Two 1MHz I2C Master/Slave + - I2S Slave + - Four-Channel, 7.8ksps, 10-bit Delta-Sigma ADC + - USB 2.0 Hi-Speed Device Interface with PHY + - 16 Pulse Train Generators + - Six 32-bit Timers with 8mA Hi-Drive + - 1-Wire® Master + + - Trust Protection Unit (TPU) for IP/Data and Security + + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Memory Decryption Integrity Unit, Secure Boot ROM + +- External devices connected to the MAX32650FTHR: + + - Battery Connector and Charging Circuit + - Micro-SD Card Interface + - USB 2.0 Full-Speed Device Interface + - MAX11261 6-Channel, 24-Bit, 16ksps, ADC + - Adafruit® Feather Board Compatible + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== +The MAX32650 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J5. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J5) using an + appropriate adapter board and cable + +Debugging +========= +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32650FTHR web page`_ + +.. _MAX32650FTHR web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html diff --git a/boards/adi/max32650fthr/max32650fthr.dts b/boards/adi/max32650fthr/max32650fthr.dts new file mode 100644 index 000000000000..aa6fcf4e4417 --- /dev/null +++ b/boards/adi/max32650fthr/max32650fthr.dts @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32650FTHR"; + compatible = "adi,max32650fthr"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + + led2: led_2 { + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio1 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + + pb2: pb2 { + gpios = <&gpio1 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_mosi_p1_29 &spi1_miso_p1_28 &spi1_sck_p1_26 &spi1_ss0_p1_23>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32650fthr/max32650fthr.yaml b/boards/adi/max32650fthr/max32650fthr.yaml new file mode 100644 index 000000000000..880af88f9c4f --- /dev/null +++ b/boards/adi/max32650fthr/max32650fthr.yaml @@ -0,0 +1,19 @@ +identifier: max32650fthr +name: max32650fthr +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial + - spi + - i2c + - dma + - watchdog + - counter + - rtc_counter +ram: 1024 +flash: 3072 diff --git a/boards/adi/max32650fthr/max32650fthr_defconfig b/boards/adi/max32650fthr/max32650fthr_defconfig new file mode 100644 index 000000000000..9428e5334a08 --- /dev/null +++ b/boards/adi/max32650fthr/max32650fthr_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32655evkit/doc/index.rst b/boards/adi/max32655evkit/doc/index.rst index 1dce1fbad6ec..9c72155a4d90 100644 --- a/boards/adi/max32655evkit/doc/index.rst +++ b/boards/adi/max32655evkit/doc/index.rst @@ -69,41 +69,7 @@ Hardware Supported Features ================== -Below are the interfaces supported by Zephyr on MAX32655EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -161,6 +127,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32655fthr/doc/index.rst b/boards/adi/max32655fthr/doc/index.rst index bc3f191c19b1..648133f2142f 100644 --- a/boards/adi/max32655fthr/doc/index.rst +++ b/boards/adi/max32655fthr/doc/index.rst @@ -82,39 +82,7 @@ Hardware Supported Features ================== -Below are the interfaces supported by Zephyr on MAX32655FTHR. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Push Buttons ************ @@ -184,6 +152,8 @@ used as a user LED. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32657evkit/Kconfig.defconfig b/boards/adi/max32657evkit/Kconfig.defconfig new file mode 100644 index 000000000000..dc6e2838d637 --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32657EVKIT + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +if BOARD_MAX32657EVKIT_MAX32657_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# MAX32657 has one UART interface, +# It can be used either on TFM or Zephyr +# Enabling debug (TFM_SPM_LOG_LEVEL || TFM_PARTITION_LOG_LEVEL) will transfer it to the TFM side +# Disabling TFM debug will transfer it to the Zephyr side. + +choice TFM_SPM_LOG_LEVEL + default TFM_SPM_LOG_LEVEL_SILENCE +endchoice + +choice TFM_PARTITION_LOG_LEVEL + default TFM_PARTITION_LOG_LEVEL_SILENCE +endchoice + +endif # BOARD_MAX32657EVKIT_MAX32657_NS + +endif # BOARD_MAX32657EVKIT diff --git a/boards/adi/max32657evkit/Kconfig.max32657evkit b/boards/adi/max32657evkit/Kconfig.max32657evkit new file mode 100644 index 000000000000..c43a70cd6f71 --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.max32657evkit @@ -0,0 +1,6 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32657EVKIT + select SOC_MAX32657 if BOARD_MAX32657EVKIT_MAX32657 || \ + BOARD_MAX32657EVKIT_MAX32657_NS diff --git a/boards/adi/max32657evkit/board.cmake b/boards/adi/max32657evkit/board.cmake new file mode 100644 index 000000000000..ecf66679a233 --- /dev/null +++ b/boards/adi/max32657evkit/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_MAX32657EVKIT_MAX32657_NS) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +board_runner_args(jlink "--device=MAX32657" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32657evkit/board.yml b/boards/adi/max32657evkit/board.yml new file mode 100644 index 000000000000..6fa072a593ce --- /dev/null +++ b/boards/adi/max32657evkit/board.yml @@ -0,0 +1,10 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32657evkit + vendor: adi + socs: + - name: max32657 + variants: + - name: "ns" diff --git a/boards/adi/max32657evkit/doc/img/max32657evkit.webp b/boards/adi/max32657evkit/doc/img/max32657evkit.webp new file mode 100644 index 000000000000..dfdd54a34da2 Binary files /dev/null and b/boards/adi/max32657evkit/doc/img/max32657evkit.webp differ diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst new file mode 100644 index 000000000000..e96410f6a1e1 --- /dev/null +++ b/boards/adi/max32657evkit/doc/index.rst @@ -0,0 +1,575 @@ +.. zephyr:board:: max32657evkit + +Overview +******** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +The nano-power modes increase battery life substantially. + +The MAX32657 is qualified to operate at a temperature range of -20°C to +85°C. +Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. +A cryptographic toolbox (CTB) provides advanced root of trust security features, +including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. +TrustZone is also included in the M33 Core. +Many high-speed interfaces are supported on the device, including multiple SPI, UART, +and I3C/I2C serial interfaces. +All interfaces support efficient DMA-driven transfers between peripheral and memory. + +The Zephyr port is running on the MAX32657 MCU. + +Hardware +******** + +- MAX32657 MCU: + + - Arm Cortex-M33 CPU with TrustZone® and FPU + - 1.2V to 1.6V Input Range for Integrated Boost DC-DC Converter + - 50MHz Low Power Oscillator + - External Crystal Support + + - 32MHz required for BLE + + - 1MB Internal Flash with ECC + - 256kB Internal SRAM + - 8kB Cache + - 32.768kHz RTC external crystal + + - Typical Electrical Characteristics + + - ACTIVE: 50μA/MHz Arm Cortex-M33 Running Coremark (50MHz) + + - Bluetooth 5.4 LE Radio + + - Rx Sensitivity: -96dBm; Tx Power: +4.5dBm + - 15mW Tx Power at 0dBm at 1.5Vin + - 14mW Rx Power at 1.5Vin + - Single-Ended Antenna Connection (50Ω) + - Supports 802.15.4, and LE Audio + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + + - Optimal Peripheral Mix Provides Platform Scalability + + - 2 DMA Controllers (Secure and non-Secure) + - One SPI Controller/Peripheral + - One I2C/I3C + - 1 Low-Power UART (LPUART) + - Six 32-Bit Low Power Timers with PWM + - 14 Configurable GPIO with Internal Pullup/Pulldown Resistors + + - Cryptographic Tool Box (CTB) for IP/Data Security + + - True Random Number Generator (TRNG) + - AES-128/192/256 + - Unique ID + + - Secure Boot ROM + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VLDO SEL | | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Sets the LDO output used for system power according to the value of resistor R4. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Sets the LDO output used for system power to 1.2V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Sets the LDO output used for system power to 1.5V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Sets the LDO output used for system power to 1.6V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | VIN SEL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VIN Powered from LDO. (USB Type-C connector is board's power source) | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | VIN Powered from Battery | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | VIN EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the board's power source to system power by connecting VIN to VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power by disconnecting VIN from VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | VDD12 EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to the MAX32657 by connecting VDD12 to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power from the MAX32657 by disconnecting VDD12 from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VTREF EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects a reference voltage to the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects a reference voltage from the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | OBD VBUS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the OBD by connecting OBD_VBUS to VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the OBD by disconnecting OBD_VBUS from VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| J7 | VSYS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to all peripherals by connecting VSYS to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power to all peripherals by disconnecting VSYS from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | ACC VS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its supply voltage pin VS to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its supply voltage pin VS from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | ACC VDD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its VDDIO pin to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its VDDIO pin from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SDA Pin is connected to MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SDA Pin is disconnected from MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SCL Pin is connected to MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SCL Pin is disconnected from MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | BYP MAG SW | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Bypass Magnetic Switch. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Enables magnetic switch. The output of the switch is controlled by the AFE pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | LOCK RSTN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE Lock Pin is connected to MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | AFE Lock Pin is disconnected from MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | LATCH CTRL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the AFE (LOCK) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the AFE (WAKE) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | AFE EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the AFE (VBAT) by connecting it to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the AFE (VBAT) by disconnecting it from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | AFE SPI EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE CSB is connected to MAX32657 SPI0_CS0. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | AFE SDI is connected to MAX32657 SPI0_MOSI. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | AFE SCLK is connected to MAX32657 SPI0_SCK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | AFE SDO is connected to MAX32657 SPI0_MISO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | AFE INTB is connected to MAX32657 P0.7. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | AFE GPIO2 is connected to MAX32657 P0.8. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disconnect SPI Interface from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | OBD SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD SWDIO is connected to the MAX32657 SWDIO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD SWCLK is connected to the MAX32657 SWCLK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD JTAG TDO Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD JTAG TDI Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | OBD RSTN is connected to the MAX32657 RSTN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 13-14 | | | OBD JTAG TRST Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disable OBD SWD Connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | OBD VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD VCOM TXD is connected VCOM EN RX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD VCOM RXD is connected VCOM EN TX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD VCOM CTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD VCOM RTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable OBD VCOM connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM RXD to the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM RXD from the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM TXD to the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM TXD from the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Data Signals to the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Data Signals from the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Clock Signals to the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Clock Signals from the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Zephyr board options +******************** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an ARM Cortex-M33 architecture that provides Trustzone technology +which allow define secure and non-secure application. +Zephyr provides support for building for both Secure (S) and Non-Secure (NS) firmware. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| max32657evkit/max32657 | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ +| max32657evkit/max32657/ns | Building with TF-M (includes NS+S images) | ++-------------------------------+-------------------------------------------+ + + +BOARD: max32657evkit/max32657 +============================= + +Build the zephyr app for ``max32657evkit/max32657`` board target will generate secure firmware +for zephyr. In this configuration 960KB of flash is used to store the code and 64KB +is used for storage section. In this mode tf-m is off and secure mode flag is on +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_SECURE` to ``y`` and +:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``n``) + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| slot0 | 0x1000000[960k] | Secure zephyr image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +Here are the instructions to build zephyr with a secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32657evkit/max32657 + :goals: build + + +BOARD: max32657evkit/max32657/ns +================================ + +The ``max32657evkit/max32657/ns`` board target is used to build the secure firmware +image using TF-M (:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``y``) and +the non-secure firmware image using Zephyr +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_NONSECURE` to ``y``). + +Here are the instructions to build zephyr with a non-secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32657evkit/max32657/ns + :goals: build + +The above command will: + * Build a bootloader image (MCUboot) + * Build a TF-M (secure) firmware image + * Build Zephyr application as non-secure firmware image + * Merge them as ``tfm_merged.hex`` which contain all images. + + +Note: + +Zephyr build TF-M with :kconfig:option:`CONFIG_TFM_PROFILE_TYPE_NOT_SET` mode +that meet most use case configuration especially for BLE related applications. +if TF-M small profile meet your application requirement you can set TF-M profile as small +:kconfig:option:`CONFIG_TFM_PROFILE_TYPE_SMALL` to ``y`` to decrease TF-M RAM and flash use. + + +Memory mappings +--------------- + +MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, +TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. +Default layout of MAX32657 is listed in below table. + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x1000000[64K] | MCU Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x1060000[576k] | Non-secure image slot0 (Zephyr) | ++----------+------------------+---------------------------------+ +| slot1 | 0x10F0000[0k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | Persistent storage | ++----------+------------------+---------------------------------+ + + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x20000000[64k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20010000[192k] | Non-Secure memory | ++----------------+------------------+-------------------+ + + +Flash memory layout are defines both on zephyr board file and `Trusted Firmware M`_ (TF-M) project +these definition shall be match. Zephyr defines it in +:zephyr_file:`boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi` +file under flash section. TF-M project define them in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/partition/flash_layout.h file.` +If you would like to update flash region for your application you shall update related section in +these files. + +Additionally if firmware update feature requires slot1 and slot1_ns section need to be +defined. On default the section size set as 0 due to firmware update not requires on default. + + +Peripherals and Memory Ownership +-------------------------------- + +The ARM Security Extensions model allows system developers to partition device hardware and +software resources, so that they exist in either the Secure world for the security subsystem, +or the Normal world for everything else. Correct system design can ensure that no Secure world +assets can be accessed from the Normal world. A Secure design places all sensitive resources +in the Secure world, and ideally has robust software running that can protect assets against +a wide range of possible software attacks (`1`_). + +MPC (Memory Protection Controller) and PPC (Peripheral Protection Controller) are allow to +protect memory and peripheral. Incase of need peripheral and flash ownership can be updated in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/s_ns_access.cmake` +file by updating cmake flags to ON/OFF. + +As an example for below configuration TRNG, SRAM_0 and SRAM_1 is not going to be accessible +by non-secure. All others is going to be accessible by NS world. + +.. code-block:: + + set(ADI_NS_PRPH_GCR ON CACHE BOOL "") + set(ADI_NS_PRPH_SIR ON CACHE BOOL "") + set(ADI_NS_PRPH_FCR ON CACHE BOOL "") + set(ADI_NS_PRPH_WDT ON CACHE BOOL "") + set(ADI_NS_PRPH_AES OFF CACHE BOOL "") + set(ADI_NS_PRPH_AESKEY OFF CACHE BOOL "") + set(ADI_NS_PRPH_CRC ON CACHE BOOL "") + set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") + set(ADI_NS_PRPH_I3C ON CACHE BOOL "") + set(ADI_NS_PRPH_UART ON CACHE BOOL "") + set(ADI_NS_PRPH_SPI ON CACHE BOOL "") + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") + set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") + set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") + set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") + set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") + set(ADI_NS_PRPH_RTC ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") + set(ADI_NS_PRPH_PWR ON CACHE BOOL "") + set(ADI_NS_PRPH_MCR ON CACHE BOOL "") + + # SRAMs + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") + + # Ramfuncs section size + set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") + + # Flash: BL2, TFM and Zephyr are contiguous sections. + set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") + set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") + set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") + set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + + # + # Allow user set S-NS resources ownership by overlay file + # + if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") + include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) + endif() + + +As an alternative method (which recommended) user can configurate ownership peripheral by +an cmake overlay file too without touching TF-M source files. For this path +create ``s_ns_access_overlay.cmake`` file under your project root folder and put peripheral/memory +you would like to be accessible by secure world. + +As an example if below configuration files been put in the ``s_ns_access_overlay.cmake`` file +TRNG, SRAM_0 and SRAM_1 will be accessible by secure world only. + +.. code-block:: + + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 + +Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| +---------------------------------------------------------------------- +The TF-M integration samples can be run using the +``max32657evkit/max32657/ns`` board target. To run we need to manually flash +the resulting image (``tfm_merged.hex``) with a J-Link as follows +(reset and erase are for recovering a locked core): + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657/ns + :goals: build + +.. code-block:: console + + west flash --hex-file build/zephyr/tfm_merged.hex + +.. code-block:: console + + [INF] Starting bootloader + [WRN] This device was provisioned with dummy keys. This device is NOT SECURE + [INF] PSA Crypto init done, sig_type: RSA-3072 + [WRN] Cannot upgrade: slots have non-compatible sectors + [WRN] Cannot upgrade: slots have non-compatible sectors + [INF] Bootloader chainload address offset: 0x10000 + [INF] Jumping to the first image slot + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657/ns + + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 + +References +********** + +.. _1: + https://developer.arm.com/documentation/100935/0100/The-TrustZone-hardware-architecture- + +.. _Trusted Firmware M: + https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.dts b/boards/adi/max32657evkit/max32657evkit_max32657.dts new file mode 100644 index 000000000000..7cee4e112771 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32657evkit_max32657_common.dtsi" + +/ { + chosen { + zephyr,sram = &secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + secure_ram: partition@30000000 { + label = "secure-memory"; + reg = <0x30000000 DT_SIZE_K(256)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(960)>; + read-only; + }; + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.yaml b/boards/adi/max32657evkit/max32657evkit_max32657.yaml new file mode 100644 index 000000000000..8290aa1fdd52 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.yaml @@ -0,0 +1,14 @@ +identifier: max32657evkit/max32657 +name: max32657evkit-max32657 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio + - trng +ram: 256 +flash: 960 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi new file mode 100644 index 000000000000..5bc950bc1670 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32657EVKIT"; + compatible = "adi,max32657evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + sw0 = &pb1; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_5>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig new file mode 100644 index 000000000000..25ef03ee5131 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts b/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts new file mode 100644 index 000000000000..a8e9369eeedb --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32657evkit_max32657_common.dtsi" + +/ { + chosen { + zephyr,sram = &non_secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* RAM split used by TFM */ + secure_ram: partition@20000000 { + label = "secure-memory"; + reg = <0x20000000 DT_SIZE_K(64)>; + }; + + non_secure_ram: partition@20010000 { + label = "non-secure-memory"; + reg = <0x20010000 DT_SIZE_K(192)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(320)>; + }; + + slot0_ns_partition: partition@60000 { + label = "image-0-nonsecure"; + reg = <0x60000 DT_SIZE_K(576)>; + }; + + /* + * slot1_partition: partition@f0000 { + * label = "image-1"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + * slot1_ns_partition: partition@f0000 { + * label = "image-1-nonsecure"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + */ + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml new file mode 100644 index 000000000000..82703d9e3544 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml @@ -0,0 +1,13 @@ +identifier: max32657evkit/max32657/ns +name: max32657evkit-max32657-Non-Secure +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio +ram: 192 +flash: 576 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig new file mode 100644 index 000000000000..d808f79c5459 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is non-secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Set TFM and Zephyr sign key +CONFIG_TFM_MCUBOOT_SIGNATURE_TYPE="RSA-3072" diff --git a/boards/adi/max32660evsys/Kconfig.max32660evsys b/boards/adi/max32660evsys/Kconfig.max32660evsys new file mode 100644 index 000000000000..2e9363977615 --- /dev/null +++ b/boards/adi/max32660evsys/Kconfig.max32660evsys @@ -0,0 +1,7 @@ +# MAX32660EVSYS boards configuration + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32660EVSYS + select SOC_MAX32660 diff --git a/boards/adi/max32660evsys/board.cmake b/boards/adi/max32660evsys/board.cmake new file mode 100644 index 000000000000..617eecca8f8e --- /dev/null +++ b/boards/adi/max32660evsys/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32660evsys/board.yml b/boards/adi/max32660evsys/board.yml new file mode 100644 index 000000000000..5e7e264b04c8 --- /dev/null +++ b/boards/adi/max32660evsys/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32660evsys + full_name: MAX32660EVSYS + vendor: adi + socs: + - name: max32660 diff --git a/boards/adi/max32660evsys/doc/img/max32660evsys.webp b/boards/adi/max32660evsys/doc/img/max32660evsys.webp new file mode 100644 index 000000000000..b3043a033a24 Binary files /dev/null and b/boards/adi/max32660evsys/doc/img/max32660evsys.webp differ diff --git a/boards/adi/max32660evsys/doc/index.rst b/boards/adi/max32660evsys/doc/index.rst new file mode 100644 index 000000000000..c556fcbfeb9a --- /dev/null +++ b/boards/adi/max32660evsys/doc/index.rst @@ -0,0 +1,111 @@ +.. zephyr:board:: max32660evsys + +Overview +******** +The MAX32660 evaluation system offers a compact development platform that +provides access to all the features of the MAX32660 in a tiny, easy to +use board. A MAX32625PICO-based debug adapter comes attached to the main +board. It can be snapped free when programming is complete. The debug +module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink +functionality. Combined measurements are 0.65in x 2.2in, while the main board +alone measures 0.65in x 0.95in. External connections terminate in a dual-row +header footprint compatible with both thru-hole and SMT applications. This +board provides a powerful processing subsystem in a very small space that +can be easily integrated into a variety of applications. + +The Zephyr port is running on the MAX32660 MCU. + +Hardware +******** + +- MAX32660 MCU: + + - High-Efficiency Microcontroller for Wearable Devices + + - Internal Oscillator Operates Up to 96MHz + - 256KB Flash Memory + - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode + - 16KB Instruction Cache + - Memory Protection Unit (MPU) + - Low 1.1V VCORE Supply Voltage + - 3.6V GPIO Operating Range + - Internal LDO Provides Operation from Single Supply + - Wide Operating Temperature: -40°C to +105°C + + - Power Management Maximizes Uptime for Battery Applications + + - 85µA/MHz Active Executing from Flash + - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V + - 450nA Ultra-Low Power RTC at VDD=1.8V + - Internal 80kHz Ring Oscillator + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 14 General-Purpose I/O Pins + - Up to Two SPI + - I2S + - Up to Two UARTs + - Up to Two I2C, 3.4Mbps High Speed + - Four-Channel Standard DMA Controller + - Three 32-Bit Timers + - Watchdog Timer + - CMOS-Level 32.768kHz RTC Output + +- Benefits and Features of MAX32660-EVSYS: + + - DIP Breakout Board + + - 100mil Pitch Dual Inline Pin Headers + - Breadboard Compatible + + - Integrated Peripherals + + - Red Indicator LED + - User Pushbutton + + - MAX32625PICO-Based Debug Adapter + + - CMSIS-DAP SWD Debugger + - Virtual UART Console + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +An Arm® debug access port (DAP) provides an external interface for debugging during application +development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial +interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32660EVSYS web page`_ + +.. _MAX32660EVSYS web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32660-evsys.html diff --git a/boards/adi/max32660evsys/max32660evsys.dts b/boards/adi/max32660evsys/max32660evsys.dts new file mode 100644 index 000000000000..f06645f94a1e --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys.dts @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32660EVSYS"; + compatible = "adi,max32660evsys"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + }; + +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p0_10 &uart1_rx_p0_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/adi/max32660evsys/max32660evsys.yaml b/boards/adi/max32660evsys/max32660evsys.yaml new file mode 100644 index 000000000000..da963ef091c6 --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys.yaml @@ -0,0 +1,13 @@ +identifier: max32660evsys +name: max32660evsys +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial +ram: 96 +flash: 256 diff --git a/boards/adi/max32660evsys/max32660evsys_defconfig b/boards/adi/max32660evsys/max32660evsys_defconfig new file mode 100644 index 000000000000..9428e5334a08 --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst index 249c6b4aeaf4..cc3d42c03a98 100644 --- a/boards/adi/max32662evkit/doc/index.rst +++ b/boards/adi/max32662evkit/doc/index.rst @@ -75,39 +75,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32662EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -201,6 +169,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts index 5f204b91bef5..e8cdc4ddb947 100644 --- a/boards/adi/max32662evkit/max32662evkit.dts +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -149,5 +149,5 @@ status = "okay"; pinctrl-0 = <&spi1a_mosi_p0_8 &spi1a_sck_p0_17>; pinctrl-names = "default"; - cs-gpios = <&gpio0 18 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; + cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; }; diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst index 96b43693653f..1569615621db 100644 --- a/boards/adi/max32666evkit/doc/index.rst +++ b/boards/adi/max32666evkit/doc/index.rst @@ -86,40 +86,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32666EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -288,6 +255,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst index b65325f380e9..5136bf589866 100644 --- a/boards/adi/max32666fthr/doc/index.rst +++ b/boards/adi/max32666fthr/doc/index.rst @@ -91,41 +91,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32666FTHR. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -208,6 +174,8 @@ JH4 Pinout Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts index 02b45bda3db5..5aa45a1c5ce2 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -55,6 +55,7 @@ led2 = &led3; sw0 = &pb1; watchdog0 = &wdt0; + sdhc0 = &sdhc0; }; /* Used for accessing other pins */ @@ -134,3 +135,56 @@ pinctrl-0 = <&owm_io_p0_12>; pinctrl-names = "default"; }; + +&sdhc0 { + pinctrl-0 = <&sdhc_dat3_p1_0 &sdhc_cmd_p1_1 &sdhc_dat0_p1_2 &sdhc_clk_p1_3 + &sdhc_dat1_p1_4 &sdhc_dat2_p1_5 &sdhc_wp_p1_6 &sdhc_cdn_p1_7>; + pinctrl-names = "default"; +}; + +&sdhc_dat3_p1_0 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_cmd_p1_1 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat0_p1_2 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_clk_p1_3 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat1_p1_4 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat2_p1_5 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_wp_p1_6 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_cdn_p1_7 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc0 { + status = "okay"; + mmc { + status = "okay"; + }; +}; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml index 71024815819a..9b924a56a6d0 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -20,5 +20,6 @@ supported: - pwm - w1 - flash + - sdhc ram: 560 flash: 1024 diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst index 3fefd9e4119b..4f5b57da3a67 100644 --- a/boards/adi/max32670evkit/doc/index.rst +++ b/boards/adi/max32670evkit/doc/index.rst @@ -84,37 +84,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32670EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -178,6 +148,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst index b4b63a8550a7..745adcd8a720 100644 --- a/boards/adi/max32672evkit/doc/index.rst +++ b/boards/adi/max32672evkit/doc/index.rst @@ -77,40 +77,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32672EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -312,11 +279,9 @@ The I2C ports can independently pulled up to V_AUX (3.3V default) through JP4 (I Programming and Debugging ************************* -The IC can be reset by pushbutton SW1. - +.. zephyr:board-supported-runners:: -Programming and Debugging -************************* +The IC can be reset by pushbutton SW1. Flashing ======== diff --git a/boards/adi/max32672evkit/max32672evkit.dts b/boards/adi/max32672evkit/max32672evkit.dts index 581a9723c1db..737b2e333709 100644 --- a/boards/adi/max32672evkit/max32672evkit.dts +++ b/boards/adi/max32672evkit/max32672evkit.dts @@ -154,7 +154,7 @@ status = "okay"; pinctrl-0 = <&spi0a_mosi_p0_3 &spi0a_miso_p0_2 &spi0a_sck_p0_4>; pinctrl-names = "default"; - cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; }; &rtc_counter { diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst index e4d387728f4e..c772136a8bda 100644 --- a/boards/adi/max32672fthr/doc/index.rst +++ b/boards/adi/max32672fthr/doc/index.rst @@ -83,40 +83,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32672FTHR. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -197,6 +164,8 @@ J7 Pinout Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst index 4028d8bc8e43..6c66e204e0cd 100644 --- a/boards/adi/max32675evkit/doc/index.rst +++ b/boards/adi/max32675evkit/doc/index.rst @@ -68,33 +68,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32675EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -370,6 +344,8 @@ respectively. If the pushbutton is pressed, the attached port pin is pulled low. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst index 10def1215cb8..a3c7d909efdb 100644 --- a/boards/adi/max32680evkit/doc/index.rst +++ b/boards/adi/max32680evkit/doc/index.rst @@ -87,39 +87,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32680EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -136,9 +104,9 @@ Connections and IOs | | | | | +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ | JP2 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ | -| | | | 2-1 | | | Connects the external high-precision voltage refernce to REF0P. | | +| | | | 2-1 | | | Connects the external high-precision voltage reference to REF0P. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | -| | | | 2-3 | | | Connects the internal voltage refernce to REF0P. | | +| | | | 2-3 | | | Connects the internal voltage reference to REF0P. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | | | | | | +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ @@ -164,9 +132,9 @@ Connections and IOs | | | | | +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ | JP6 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ | -| | | | 2-1 | | | Connects the external high-precision voltage refernce to REF1P. | | +| | | | 2-1 | | | Connects the external high-precision voltage reference to REF1P. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | -| | | | 2-3 | | | Connects the internal voltage refernce to REF1P. | | +| | | | 2-3 | | | Connects the internal voltage reference to REF1P. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | | | | | | +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ @@ -319,6 +287,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts index 4547da3459df..d3459098a11a 100644 --- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts @@ -163,7 +163,7 @@ status = "okay"; pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7>; pinctrl-names = "default"; - cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; + cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; }; &w1 { diff --git a/boards/adi/max32690evkit/doc/index.rst b/boards/adi/max32690evkit/doc/index.rst index ab484d1e32e8..796bbeb18398 100644 --- a/boards/adi/max32690evkit/doc/index.rst +++ b/boards/adi/max32690evkit/doc/index.rst @@ -91,42 +91,7 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32690EVKIT. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -276,6 +241,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index d04a91852cdf..8e2aabb71f89 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024 Analog Devices, Inc. + * Copyright (c) 2023-2025 Analog Devices, Inc. * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -95,6 +96,30 @@ mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; }; + + sdram1: sdram1@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM1"; + }; +}; + +&hpb { + pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_rwds_p1_14 &hyp_d0_p1_12 &hyp_d1_p1_15 + &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 + &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; + pinctrl-names = "default"; + enable-emcc; + + mem@0 { + reg = <0>; + base-address = <0x60000000>; + device-type = ; + config-regs = <1>; + config-reg-vals = <2>; + }; }; &clk_ipo { @@ -167,3 +192,7 @@ &rtc_counter { status = "okay"; }; + +zephyr_udc0: &usbhs { + status = "okay"; +}; diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml index 150225890e2a..83c03c9715d8 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -20,5 +20,7 @@ supported: - pwm - w1 - flash + - usbd + - memc ram: 1024 flash: 3072 diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst index ad133537417d..ffbc67d93207 100644 --- a/boards/adi/max32690fthr/doc/index.rst +++ b/boards/adi/max32690fthr/doc/index.rst @@ -63,31 +63,13 @@ Hardware Supported Features ================== -Below interfaces are supported by Zephyr on MAX32690FTHR. - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max32690fthr/doc/max32690fthr.webp b/boards/adi/max32690fthr/doc/max32690fthr.webp new file mode 100644 index 000000000000..cf4062dcbe9a Binary files /dev/null and b/boards/adi/max32690fthr/doc/max32690fthr.webp differ diff --git a/boards/adi/max78000evkit/doc/img/max78000evkit_img1.webp b/boards/adi/max78000evkit/doc/img/max78000evkit.webp similarity index 100% rename from boards/adi/max78000evkit/doc/img/max78000evkit_img1.webp rename to boards/adi/max78000evkit/doc/img/max78000evkit.webp diff --git a/boards/adi/max78000evkit/doc/index.rst b/boards/adi/max78000evkit/doc/index.rst index fb9c2fc8bcd8..18986d881cf7 100644 --- a/boards/adi/max78000evkit/doc/index.rst +++ b/boards/adi/max78000evkit/doc/index.rst @@ -11,10 +11,6 @@ to SPI bridge provides rapid access to onboard memory, allowing large networks o The Zephyr port is running on the MAX78000 MCU. -.. image:: img/max78000evkit_img1.webp - :align: center - :alt: MAX78000 EVKIT - Hardware ******** @@ -59,43 +55,7 @@ Hardware Supported Features ================== -The ``max78000evkit/max78000/m4`` board target supports the following interfaces: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | real time clock | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+--------------------------------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -275,6 +235,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml index f974a60c9959..5f7f52250411 100644 --- a/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml +++ b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml @@ -6,7 +6,6 @@ arch: arm toolchain: - zephyr - gnuarmemb - - xtools supported: - adc - counter diff --git a/boards/adi/max78000fthr/doc/img/max78000fthr_img1.webp b/boards/adi/max78000fthr/doc/img/max78000fthr.webp similarity index 100% rename from boards/adi/max78000fthr/doc/img/max78000fthr_img1.webp rename to boards/adi/max78000fthr/doc/img/max78000fthr.webp diff --git a/boards/adi/max78000fthr/doc/index.rst b/boards/adi/max78000fthr/doc/index.rst index fee925ffae88..1960a00257ed 100644 --- a/boards/adi/max78000fthr/doc/index.rst +++ b/boards/adi/max78000fthr/doc/index.rst @@ -12,10 +12,6 @@ platform for quick proof-of-concepts and early software development to enhance t The Zephyr port is running on the MAX78000 MCU. -.. image:: img/max78000fthr_img1.webp - :align: center - :alt: MAX78000 FTHR - Hardware ******** @@ -60,43 +56,7 @@ Hardware Supported Features ================== -The ``max78000fthr/max78000/m4`` board target supports the following interfaces: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | real time clock | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+--------------------------------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -178,6 +138,8 @@ J4 Pinout Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml index f649928b1bac..116fa9051c58 100644 --- a/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml +++ b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml @@ -6,7 +6,6 @@ arch: arm toolchain: - zephyr - gnuarmemb - - xtools supported: - adc - counter diff --git a/boards/adi/max78002evkit/doc/index.rst b/boards/adi/max78002evkit/doc/index.rst index 9a9d11a93075..ffb55415bf43 100644 --- a/boards/adi/max78002evkit/doc/index.rst +++ b/boards/adi/max78002evkit/doc/index.rst @@ -81,41 +81,7 @@ Hardware Supported Features ================== -The ``max78002evkit/max78002/m4`` board target supports the following interfaces: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock and reset control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma controller | -+-----------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| Timer | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| W1 | on-chip | one wire master | -+-----------+------------+-------------------------------------+ -| Flash | on-chip | flash | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -442,6 +408,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst index 680852f53dd9..d684c53374c9 100644 --- a/boards/adi/sdp_k1/doc/index.rst +++ b/boards/adi/sdp_k1/doc/index.rst @@ -65,23 +65,7 @@ More information about STM32F469NI can be found here: Supported Features ================== -The Zephyr stm32f469i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in -:zephyr_file:`boards/adi/sdp_k1/adi_sdp_k1_defconfig` +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -119,6 +103,8 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected to a STLINK debugger. diff --git a/boards/aesc/elemrv/Kconfig.elemrv b/boards/aesc/elemrv/Kconfig.elemrv new file mode 100644 index 000000000000..9c22c252583c --- /dev/null +++ b/boards/aesc/elemrv/Kconfig.elemrv @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Aesc Silicon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ELEMRV + select SOC_ELEMRV_N diff --git a/boards/aesc/elemrv/board.yml b/boards/aesc/elemrv/board.yml new file mode 100644 index 000000000000..8a4890dd13a8 --- /dev/null +++ b/boards/aesc/elemrv/board.yml @@ -0,0 +1,6 @@ +board: + name: elemrv + full_name: ElemRV-N + vendor: aesc + socs: + - name: elemrv_n diff --git a/boards/aesc/elemrv/doc/index.rst b/boards/aesc/elemrv/doc/index.rst new file mode 100644 index 000000000000..cae642e0a274 --- /dev/null +++ b/boards/aesc/elemrv/doc/index.rst @@ -0,0 +1,72 @@ +.. zephyr:board:: elemrv + +Overview +******** + +ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL. + +Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_. + +For more details, refer to the official `GitHub Project`_. + +.. note:: + The currently supported silicon version is ElemRV-N 0.2. + +Supported Features +****************** + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property. + +CPU +=== + +ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions: + +* M (Integer Multiply/Divide) +* C (Compressed Instructions) + +It also includes the following general-purpose ``Z`` extensions: + +* Zicntr – Base Counter and Timer extensions +* Zicsr – Control and Status Register operations +* Zifencei – Instruction-fetch fence + +The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei`` + +Hart-Level Interrupt Controller (HLIC) +====================================== + +Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs). + +Machine Timer +============= + +A RISC-V compliant machine timer is enabled by default. + +Serial +====== + +The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data. + +By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree. + +To evaluate the UART interface, build and run the following sample: + +.. zephyr-app-commands:: + :board: elemrv/elemrv_n + :zephyr-app: samples/hello_world + :goals: build + +.. _GitHub Project: + https://github.com/aesc-silicon/elemrv + +.. _IHP's Open PDK: + https://github.com/IHP-GmbH/IHP-Open-PDK + +.. _FMD-QNC: + https://www.elektronikforschung.de/projekte/fmd-qnc diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.dts b/boards/aesc/elemrv/elemrv_elemrv_n.dts new file mode 100644 index 000000000000..4b9ea13bf849 --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2025 Aesc Silicon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "ElemRV-N"; + compatible = "aesc,elemrv-n"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &hyperbus; + zephyr,flash = &flash; + }; + + soc { + ocram: memory@80000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x80000000 DT_SIZE_K(1)>; + }; + + hyperbus: memory@90000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x90000000 DT_SIZE_K(32)>; + }; + + flash: flash@a0010000 { + compatible = "soc-nv-flash"; + reg = <0xa0010000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart0 { + clock-frequency = ; + current-speed = <115200>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.yaml b/boards/aesc/elemrv/elemrv_elemrv_n.yaml new file mode 100644 index 000000000000..4c9c3a991749 --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n.yaml @@ -0,0 +1,9 @@ +identifier: elemrv/elemrv_n +name: ElemRV-N +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 32 +flash: 32 diff --git a/boards/aesc/elemrv/elemrv_elemrv_n_defconfig b/boards/aesc/elemrv/elemrv_elemrv_n_defconfig new file mode 100644 index 000000000000..ac046a3cbbc5 --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Aesc Silicon +# SPDX-License-Identifier: Apache-2.0 + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/aesc/index.rst b/boards/aesc/index.rst new file mode 100644 index 000000000000..2471cc5acc01 --- /dev/null +++ b/boards/aesc/index.rst @@ -0,0 +1,10 @@ +.. _boards-aesc: + +Aesc Silicon +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f b/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f new file mode 100644 index 000000000000..9c4fa2f57d72 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f @@ -0,0 +1,6 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_AI_WB2_12F + select SOC_BL602C00Q2I diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi b/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi new file mode 100644 index 000000000000..2ca492092877 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + pinmux = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts new file mode 100644 index 000000000000..d3e99d7a45fa --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ai_wb2_12f-pinctrl.dtsi" + +/ { + model = "Ai-Thinker WB2-12F development board"; + compatible = "bflb,bl602"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0x400000>; + + flash0: flash@0 { + compatible = "zb,25vq32", "jedec,spi-nor"; + status = "disabled"; + size = ; + jedec-id = [5e 40 16]; + reg = <0>; + spi-max-frequency = ; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml new file mode 100644 index 000000000000..e7c5a4dc59e5 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: ai_wb2_12f +name: Ai-Thinker WB2-12F development board +type: mcu +arch: riscv +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +supported: + - pinctrl + - uart +vendor: bflb diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig b/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig new file mode 100644 index 000000000000..7836442f7c45 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_UART_CONSOLE=y diff --git a/boards/aithinker/ai_wb2_12f/board.cmake b/boards/aithinker/ai_wb2_12f/board.cmake new file mode 100644 index 000000000000..82839f838940 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/board.cmake @@ -0,0 +1,25 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") + +board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") +board_runner_args(openocd --gdb-init "set architecture riscv:rv32") +board_runner_args(openocd --gdb-init "set remotetimeout 250") +board_runner_args(openocd --gdb-init "set print asm-demangle on") +board_runner_args(openocd --gdb-init "set backtrace limit 32") +board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") +board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") +board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") +board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") +board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(bflb_mcu_tool --chipname bl602) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/aithinker/ai_wb2_12f/board.yml b/boards/aithinker/ai_wb2_12f/board.yml new file mode 100644 index 000000000000..fad47a56affb --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/board.yml @@ -0,0 +1,6 @@ +board: + name: ai_wb2_12f + full_name: Ai-Thinker WB2-12F development board + vendor: aithinker + socs: + - name: bl602c00q2i diff --git a/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp b/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp new file mode 100644 index 000000000000..ae6ef3f02dc1 Binary files /dev/null and b/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp differ diff --git a/boards/aithinker/ai_wb2_12f/doc/index.rst b/boards/aithinker/ai_wb2_12f/doc/index.rst new file mode 100644 index 000000000000..b68fc820bbc9 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/doc/index.rst @@ -0,0 +1,105 @@ +.. zephyr:board:: ai_wb2_12f + +Overview +******** + +BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used +for low power consumption and high performance application development. The +wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 +baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU +with low power consumption, cache and memory. The power management unit +controls the low power consumption mode. In addition, it also supports +various security features. The external interfaces include SDIO, SPI, UART, +I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. + +This WB2 (BL602) 12F format Module Development Board features a SiFive E24 32 bit +RISC-V CPU with FPU, it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, +2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 +with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed +image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key +Accelerator). + +Hardware +******** + +For more information about the Bouffalo Lab BL-60x MCU: + +- `Bouffalo Lab BL60x MCU Website`_ +- `Bouffalo Lab BL60x MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `ai_wb2_12f Schematics`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The WB2 (BL602) Development Board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``ai_wb2_12f`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ai_wb2_12f + :goals: build flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ screen /dev/ttyUSB0 115200 + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release RST button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0 *** + Hello World! ai_wb2_12f/bl602c00q2i + +Congratulations, you have ``ai_wb2_12f`` configured and running Zephyr. + + +.. _Bouffalo Lab BL60x MCU Website: + https://en.bouffalolab.com/product/?type=detail&id=6 + +.. _Bouffalo Lab BL60x MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _ai_wb2_12f Schematics: + https://docs.ai-thinker.com/en/wb2 + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/aithinker/ai_wb2_12f/support/bl60x.cfg b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg new file mode 100644 index 000000000000..fcabb2c4e7c0 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME riscv +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +if { [info exists WORKAREAADDR] } { + set _WORKAREAADDR $WORKAREAADDR +} else { + set _WORKAREAADDR 0x22020000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x20000c05 +} + +transport select jtag +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME + +$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + + adapter speed 100 + + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x23000000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" + + adapter speed 3000 +} + +$_TARGETNAME.0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME.0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +gdb_memory_map enable +gdb_flash_program enable + +# 'progbuf', 'sysbus' or 'abstract' +riscv set_mem_access sysbus +riscv set_command_timeout_sec 1 + +init +reset init diff --git a/boards/aithinker/ai_wb2_12f/support/openocd.cfg b/boards/aithinker/ai_wb2_12f/support/openocd.cfg new file mode 100644 index 000000000000..9a3b1644e96d --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/support/openocd.cfg @@ -0,0 +1,5 @@ +# For WCH linkE in DAP mode + +interface cmsis-dap + +adapter speed 1000 diff --git a/boards/aithinker/index.rst b/boards/aithinker/index.rst new file mode 100644 index 000000000000..cdefd628132b --- /dev/null +++ b/boards/aithinker/index.rst @@ -0,0 +1,10 @@ +.. _boards-aithinker: + +Ai-Thinker Co. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst index d976ee7740f1..671570b64099 100644 --- a/boards/alientek/pandora_stm32l475/doc/index.rst +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -85,44 +85,7 @@ The STM32L475VE SoC provides the following hardware features: Supported Features ================== -The Zephyr stm32l475ve_pandora board configuration supports the following hardware features: - -+-----------+------------+----------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==============================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+----------------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+----------------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------------------------------+ -| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) | -| | | I2C-ICM2068(light environment sensor) | -+-----------+------------+----------------------------------------------+ -| I2S | on-chip | I2S-ES8388(Audio Decoder) | -+-----------+------------+----------------------------------------------+ -| USB | on-chip | I2S-OTG | -+-----------+------------+----------------------------------------------+ -| SDIO | on-chip | SDIO-AP6181(WIFI) | -+-----------+------------+----------------------------------------------+ -| SPI | on-chip | LCD-TFT | -+-----------+------------+----------------------------------------------+ -| QSPI NOR | on-chip | flash | -+-----------+------------+----------------------------------------------+ -| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter | -+-----------+------------+----------------------------------------------+ -| STLINK-V2 | on-board | STLINK-V2 Debugger | -+-----------+------------+----------------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - :zephyr_file:`boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -158,6 +121,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/altr/index.rst b/boards/altr/index.rst deleted file mode 100644 index 83220f8c905b..000000000000 --- a/boards/altr/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-altera: - -Altera Corporation -################## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 deleted file mode 100644 index b0b39da84487..000000000000 --- a/boards/altr/max10/Kconfig.altera_max10 +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -config BOARD_ALTERA_MAX10 - select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig deleted file mode 100644 index d0617d44c33c..000000000000 --- a/boards/altr/max10/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -if BOARD_ALTERA_MAX10 - -if FLASH - -config SOC_FLASH_NIOS2_QSPI - default y - -endif # FLASH - -endif # BOARD_ALTERA_MAX10 diff --git a/boards/altr/max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts deleted file mode 100644 index 30c7e4425057..000000000000 --- a/boards/altr/max10/altera_max10.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ -/* Copyright (c) 2018 Intel */ - -/dts-v1/; - -#include -#include - -/ { - model = "altera_max10"; - compatible = "altr,nios2-max10"; - - aliases { - uart-0 = &uart0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; -}; - -&qspi { - status = "okay"; - n25q512ax3: n25q512ax3@0 { - compatible = "altr,nios2-qspi-nor"; - size = ; /* in bits */ - reg = <0>; - }; -}; diff --git a/boards/altr/max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml deleted file mode 100644 index eb068f21f47c..000000000000 --- a/boards/altr/max10/altera_max10.yaml +++ /dev/null @@ -1,7 +0,0 @@ -identifier: altera_max10 -name: Altera MAX10 -type: mcu -arch: nios2 -toolchain: - - zephyr -vendor: altr diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig deleted file mode 100644 index ac9a2e96e4d3..000000000000 --- a/boards/altr/max10/altera_max10_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/altr/max10/board.cmake b/boards/altr/max10/board.cmake deleted file mode 100644 index 9e7a8dd873d5..000000000000 --- a/boards/altr/max10/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(nios2 "--cpu-sof=${ZEPHYR_BASE}/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof") -include(${ZEPHYR_BASE}/boards/common/nios2.board.cmake) diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml deleted file mode 100644 index 9106b7e15ec0..000000000000 --- a/boards/altr/max10/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: altera_max10 - full_name: MAX10 - vendor: altr - socs: - - name: zephyr_nios2f diff --git a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg deleted file mode 100644 index 5c71d7bf80d8..000000000000 Binary files a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg deleted file mode 100644 index 51d5424c2f8f..000000000000 Binary files a/boards/altr/max10/doc/img/altera_max10.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst deleted file mode 100644 index 0c16aa329e8e..000000000000 --- a/boards/altr/max10/doc/index.rst +++ /dev/null @@ -1,322 +0,0 @@ -.. zephyr:board:: altera_max10 - -Overview -******** - -The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using -the Nios II Gen 2 soft CPU. - -Hardware -******** - -DIP Switch settings -=================== - -There are two sets of switches on the back of the board. Of particular -importance is SW2: - -* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first - boot image is CFM0 -* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing - scripts won't work -* Switch 4 (HSMC_BYPASSN) should be OFF (up) - -.. image:: img/Altera_MAX10_switches.jpg - :align: center - :alt: Altera's MAX* 10 Switches - -Other switches are user switches, their position is application-specific. - -Necessary Software -================== - -You will need the Altera Quartus SDK in order to work with this device. The -`Altera Lite Distribution`_ of Quartus may be obtained without -charge. - -For your convenience using the SDK tools (such as ``nios2-configure-sof``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export ALTERA_BASE=/opt/altera_lite/16.0 - export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Fedora 23: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-1.2] - 031050DD 10M50DA(.|ES)/10M50DC - 020D10DD VTAP10 - - -Reference CPU -============= - -A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory. - -Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA -configuration file -:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`: - -.. code-block:: console - - $ nios2-configure-sof ghrd_10m50da.sof - -This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. -For any Nios II SOC definition, you can find out more details about the CPU -configuration by inspecting system.h in the SOC's include directory. - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (it will show up in /dev as a ttyUSB node), and then running -minicom with flow control disabled, 115200-8N1 settings. - -JTAG UART ---------- - -You can also have it send its console output to the JTAG UART. -Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: - -.. code-block:: devicetree - - &jtag_uart { - status = "okay"; - current-speed = <115200>; - }; - -To view these messages on your local workstation, run the terminal application -in the SDK: - -.. code-block:: console - - $ nios2-terminal - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Kernel into UFM ------------------------- - -The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the scripts/support/quartus-flash.py script. After it completes the kernel -will immediately boot. - - -Flashing Kernel directly into RAM over JTAG -------------------------------------------- - -The SDK included the nios2-download tool which will let you flash a kernel -directly into RAM and then boot it from the __start symbol. - -In order for this to work, your entire kernel must be located in RAM. Make sure -the following config options are disabled: - -.. code-block:: cfg - - CONFIG_XIP=n - CONFIG_INCLUDE_RESET_VECTOR=n - -Then, after building your kernel, push it into device's RAM by running -this from the build directory: - -.. code-block:: console - - $ nios2-download --go zephyr/zephyr.elf - -If you have a console session running (either minicom or nios2-terminal) you -should see the application's output. There are additional arguments you can pass -to nios2-download so that it spawns a GDB server that you can connect to, -although it's typically simpler to just use nios2-gdb-server as described below. - -Debugging -========= - -The Altera SDK includes a GDB server which can be used to debug a MAX10 board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With UFM Flashed Image --------------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - Nios II GDB server running on port 3335 - Ignoring --stop option because --tcpport also specified - GNU gdb (GDB) 7.11.0.20160511-git - Copyright (C) 2016 Free Software Foundation, Inc. - License GPLv3+: GNU GPL version 3 or later - This is free software: you are free to change and redistribute it. - There is NO WARRANTY, to the extent permitted by law. Type "show copying" - and "show warranty" for details. - This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". - Type "show configuration" for configuration details. - For bug reporting instructions, please see: - . - Find the GDB manual and other documentation resources online at: - . - For help, type "help". - Type "apropos word" to search for commands related to "word"... - Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. - Remote debugging using :3335 - Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 - Resetting and pausing target processor: OK - Listening on port 3335 for connection from GDB: accepted - isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 - 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); - (gdb) b z_prep_c - Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. - (gdb) b z_cstart - Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. - (gdb) c - Continuing. - - Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 - 348 { - (gdb) - -To start debugging manually: - - -.. code-block:: console - - nios2-gdb-server --tcpport 1234 --stop --reset-target - -And then connect with GDB from the build directory: - - -.. code-block:: console - - nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" - -Debugging With JTAG Flashed Image ---------------------------------- - -In order for this to work, execute-in-place must be disabled, since the GDB -'load' command can only put text and data in RAM. Ensure this is in your -configuration: - -.. code-block:: cfg - - CONFIG_XIP=n - -It is OK for this procedure to leave the reset vector enabled, unlike -nios2-download (which errors out if it finds sections outside of SRAM) it will -be ignored. - -In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if -any) is on the device, but you should have at least flashed a CPU using -nios2-configure-sof. You can leave this process running. - -.. code-block:: console - - $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target - -Build your Zephyr kernel, and load it into a GDB built for Nios II (included in -the Zephyr SDK) from the build directory: - -.. code-block:: console - - $ nios2-poky-elf-gdb zephyr/zephyr.elf - -Then connect to the GDB server: - -.. code-block:: console - - (gdb) target remote :1234 - -And then load the kernel image over the wire. The CPU will not start from the -reset vector, instead it will boot from the __start symbol: - - -.. code-block:: console - - (gdb) load - Loading section reset, size 0xc lma 0x0 - Loading section exceptions, size 0x1b0 lma 0x400020 - Loading section text, size 0x8df0 lma 0x4001d0 - Loading section devconfig, size 0x30 lma 0x408fc0 - Loading section rodata, size 0x3f4 lma 0x408ff0 - Loading section datas, size 0x888 lma 0x4093e4 - Loading section initlevel, size 0x30 lma 0x409c6c - Loading section _k_task_list, size 0x58 lma 0x409c9c - Loading section _k_task_ptr, size 0x8 lma 0x409cf4 - Loading section _k_event_list, size 0x10 lma 0x409cfc - Start address 0x408f54, load size 40184 - Transfer rate: 417 KB/sec, 368 bytes/write. - After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. - - - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi index 26cf5e58063e..39db2783c37a 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi @@ -125,7 +125,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <0>; + ambiq,nce-src = <0>; ambiq,iom-num = <6>; }; }; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index bea88a5c3b91..ed7a0494a70a 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -30,7 +30,6 @@ sw1 = &button1; bootloader-led0 = &led0; mcuboot-led0 = &led0; - rtc = &rtc0; }; leds { @@ -139,57 +138,33 @@ status = "okay"; }; -&spi0 { - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; - clock-frequency = ; - status = "okay"; +&iom0 { + spi0: spi { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "disabled"; + }; }; -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; - clock-frequency = ; - scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; +&iom3 { + i2c3: i2c { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; + clock-frequency = ; + scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + status = "disabled"; + }; }; &counter0 { - status = "okay"; -}; - -&counter1 { - status = "okay"; -}; - -&counter2 { - status = "okay"; -}; - -&counter3 { - status = "okay"; -}; - -&counter4 { - status = "okay"; -}; - -&counter5 { - status = "okay"; -}; - -&counter6 { - status = "okay"; -}; - -&counter7 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi index 77e22c5bbb50..7a6ad127efa2 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi +++ b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi @@ -63,5 +63,5 @@ }; }; -ambiq_spi0: &spi0 {}; -ambiq_i2c3: &i2c3 {}; +ambiq_spi0: &iom0 {}; +ambiq_i2c3: &iom3 {}; diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst index 429d973d3781..c8d56b0443b4 100644 --- a/boards/ambiq/apollo3_evb/doc/index.rst +++ b/boards/ambiq/apollo3_evb/doc/index.rst @@ -21,34 +21,13 @@ For more information about the Apollo3 Blue SoC and Apollo3 Blue EVB board: Supported Features ================== -The Apollo3 Blue EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo3_evb/apollo3_evb_defconfig``. +.. zephyr:board-supported-hw:: Programming and Debugging ========================= +.. zephyr:board-supported-runners:: + Flashing an application ----------------------- diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi index 3eea582a3724..f8821a4c2f83 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi @@ -126,7 +126,7 @@ drive-push-pull; drive-strength = "0.5"; ambiq,iom-mspi = <0>; - ambiq,iom-nce-module = <0>; + ambiq,nce-src = <0>; ambiq,iom-num = <0>; }; }; @@ -147,7 +147,7 @@ drive-push-pull; drive-strength = "0.5"; ambiq,iom-mspi = <0>; - ambiq,iom-nce-module = <0>; + ambiq,nce-src = <0>; ambiq,iom-num = <1>; }; }; @@ -164,7 +164,7 @@ drive-push-pull; drive-strength = "0.5"; ambiq,iom-mspi = <0>; - ambiq,iom-nce-module = <0>; + ambiq,nce-src = <0>; ambiq,iom-num = <2>; }; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index 56b9ec15fec9..8b3371389741 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -26,7 +26,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; }; leds { @@ -117,57 +116,33 @@ status = "okay"; }; -&spi0 { - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; - clock-frequency = ; - status = "okay"; +&iom0 { + spi0: spi { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "disabled"; + }; }; -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; - clock-frequency = ; - scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; +&iom3 { + i2c3: i2c { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; + clock-frequency = ; + scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + status = "disabled"; + }; }; &counter0 { - status = "okay"; -}; - -&counter1 { - status = "okay"; -}; - -&counter2 { - status = "okay"; -}; - -&counter3 { - status = "okay"; -}; - -&counter4 { - status = "okay"; -}; - -&counter5 { - status = "okay"; -}; - -&counter6 { - status = "okay"; -}; - -&counter7 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi index fc85edb4a632..73b8d42e107d 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi @@ -88,5 +88,5 @@ }; }; -ambiq_spi0: &spi0 {}; -ambiq_i2c3: &i2c3 {}; +ambiq_spi0: &iom0 {}; +ambiq_i2c3: &iom3 {}; diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst index a5f848c4f2c2..1aa477d785d3 100644 --- a/boards/ambiq/apollo3p_evb/doc/index.rst +++ b/boards/ambiq/apollo3p_evb/doc/index.rst @@ -21,34 +21,13 @@ For more information about the Apollo3 Blue Plus SoC and Apollo3 Blue Plus EVB b Supported Features ================== -The Apollo3 Blue Plus EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo3p_evb/apollo3p_evb_defconfig``. +.. zephyr:board-supported-hw:: Programming and Debugging ========================= +.. zephyr:board-supported-runners:: + Flashing an application ----------------------- diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig index 63595ffddbd5..2bcd67ff17ca 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -19,6 +19,9 @@ config MAIN_STACK_SIZE config BT_BUF_ACL_TX_COUNT default 14 +config BT_BUF_EVT_RX_COUNT + default 15 + config BT_BUF_CMD_TX_SIZE default $(UINT8_MAX) diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi index f8c20b0fad98..2cf596eadcd9 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi @@ -128,7 +128,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <32>; + ambiq,nce-src = <32>; }; }; mspi1_default: mspi1_default{ @@ -141,7 +141,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <34>; + ambiq,nce-src = <34>; }; }; mspi2_default: mspi2_default{ @@ -154,7 +154,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <36>; + ambiq,nce-src = <36>; }; }; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index 1a94e0e25cad..f33e454272e2 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -26,7 +26,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; }; leds { @@ -77,11 +76,11 @@ }; &counter0 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; @@ -89,33 +88,39 @@ status = "okay"; }; -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - clock-frequency = ; - scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; +&iom0 { + i2c0: i2c { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + status = "disabled"; + }; }; -&spi1 { - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; - clock-frequency = ; - status = "okay"; +&iom1 { + spi1: spi { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "disabled"; + }; }; -&spi4 { - pinctrl-0 = <&spi4_default>; - pinctrl-names = "default"; - status = "okay"; +&iom4 { + spi4: spi { + pinctrl-0 = <&spi4_default>; + pinctrl-names = "default"; + status = "okay"; + }; }; &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &flash0 { diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index 81158fba6dbf..b6e891ef53f3 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -23,40 +23,13 @@ For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR E Supported Features ================== -The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig` +.. zephyr:board-supported-hw:: Programming and Debugging ========================= +.. zephyr:board-supported-runners:: + Flashing an application ----------------------- diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi index dbbb233485e9..ccfdfd72974e 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi @@ -142,7 +142,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <32>; + ambiq,nce-src = <32>; }; }; mspi1_default: mspi1_default{ @@ -155,7 +155,7 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <34>; + ambiq,nce-src = <34>; }; }; mspi2_default: mspi2_default{ @@ -168,7 +168,28 @@ pinmux = ; drive-push-pull; drive-strength = "0.5"; - ambiq,iom-nce-module = <36>; + ambiq,nce-src = <36>; + }; + }; + sdio0_default: sdio0_default { + group0 { + pinmux = , + , + , + , + , + ; + drive-strength = "1.0"; + }; + group1 { + pinmux = + , + , + , + ; + drive-strength = "1.0"; + bias-pull-up; + ambiq,pull-up-ohms = <12000>; }; }; }; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index a37974d10b91..567ec2143fe9 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -25,7 +25,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; }; leds { @@ -78,15 +77,15 @@ &adc0 { pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &counter0 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; @@ -94,39 +93,43 @@ status = "okay"; }; -&iom0_i2c { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - clock-frequency = ; - scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; +&iom0 { + i2c0: i2c { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + status = "disabled"; + }; }; -&iom1_spi { - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; - clock-frequency = <1000000>; - status = "okay"; +&iom1 { + spi1: spi { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = <1000000>; + status = "disabled"; + }; }; &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &mspi1 { pinctrl-0 = <&mspi1_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &mspi2 { pinctrl-0 = <&mspi2_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &flash0 { @@ -150,6 +153,19 @@ clk-source = <3>; }; +&sdio0 { + pinctrl-0 = <&sdio0_default>; + pinctrl-names = "default"; + txdelay = <0>; + rxdelay = <0>; + status = "disabled"; + mmc { + compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; + status = "disabled"; + }; +}; + zephyr_udc0: &usb { vddusb33-gpios = <&gpio96_127 7 (GPIO_PULL_UP)>; vddusb0p9-gpios = <&gpio96_127 5 (GPIO_PULL_UP)>; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi index e083db991e24..690ed85437de 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi @@ -118,4 +118,4 @@ }; }; -spi1: &iom1_spi {}; +ambiq_spi1: &iom1 {}; diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst index d2cc43e5bb41..ab8ccfd456a5 100644 --- a/boards/ambiq/apollo4p_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -22,36 +22,13 @@ For more information about the Apollo4 Plus SoC and Apollo4P EVB board: Supported Features ================== -The Apollo4P EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig` +.. zephyr:board-supported-hw:: Programming and Debugging ========================= +.. zephyr:board-supported-runners:: + Flashing an application ----------------------- diff --git a/boards/ambiq/apollo510_evb/CMakeLists.txt b/boards/ambiq/apollo510_evb/CMakeLists.txt new file mode 100644 index 000000000000..218a0602483a --- /dev/null +++ b/boards/ambiq/apollo510_evb/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/ambiq/apollo510_evb/Kconfig b/boards/ambiq/apollo510_evb/Kconfig new file mode 100644 index 000000000000..6929d8941036 --- /dev/null +++ b/boards/ambiq/apollo510_evb/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +config BOARD_APOLLO510_EVB + select BOARD_EARLY_INIT_HOOK diff --git a/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb b/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb new file mode 100644 index 000000000000..38315f5fd69b --- /dev/null +++ b/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +config BOARD_APOLLO510_EVB + select SOC_APOLLO510 diff --git a/boards/ambiq/apollo510_evb/Kconfig.defconfig b/boards/ambiq/apollo510_evb/Kconfig.defconfig new file mode 100644 index 000000000000..8fd84d081a08 --- /dev/null +++ b/boards/ambiq/apollo510_evb/Kconfig.defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +if BOARD_APOLLO510_EVB + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + default 96000000 if CORTEX_M_SYSTICK + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + +if MSPI + +config MSPI_INIT_PRIORITY + default 40 + +endif # MSPI + +endif # BOARD_APOLLO510_EVB diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi new file mode 100644 index 000000000000..2f1472fc061e --- /dev/null +++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + swo_default: swo_default { + group0 { + pinmux = ; + }; + }; + + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c3_default: i2c3_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c5_default: i2c5_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c6_default: i2c6_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c7_default: i2c7_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + spid0_default: spid0_default { + group1 { + pinmux = , , , ; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + }; + + spi2_default: spi2_default { + group1 { + pinmux = , , ; + }; + }; + + spi3_default: spi3_default { + group1 { + pinmux = , , ; + }; + }; + + spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + }; + + spi5_default: spi5_default { + group1 { + pinmux = , , ; + }; + }; + + spi6_default: spi6_default { + group1 { + pinmux = , , ; + }; + }; + + spi7_default: spi7_default { + group1 { + pinmux = , , ; + }; + }; + + mspi0_default: mspi0_default { + group0 { + pinmux = , + , + ; + drive-strength = "0.5"; + }; + + group1 { + pinmux = ; + drive-strength = "0.75"; + }; + }; + + mspi1_default: mspi1_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "0.5"; + }; + }; + + mspi0_sleep: mspi0_sleep { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mspi1_sleep: mspi1_sleep { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mspi0_psram: mspi0_psram { + group0 { + pinmux = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* DQS0 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 */ + , /* D12 */ + , /* D13 */ + , /* D14 */ + , /* D15 */ + , /* DQS1 */ + ; /* CE0 */ + drive-strength = "0.5"; + }; + + group1 { + pinmux = ; /* SCK */ + drive-strength = "0.75"; + }; + }; + + mspi1_flash: mspi1_flash { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + ; + drive-strength = "1.0"; + }; + + group1 { + pinmux = ; + drive-strength = "0.5"; + }; + }; +}; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts new file mode 100644 index 000000000000..4d4b898629c7 --- /dev/null +++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts @@ -0,0 +1,148 @@ +/dts-v1/; +#include +#include "apollo510_evb-pinctrl.dtsi" +#include + +/ { + model = "Ambiq Apollo510 evaluation board"; + compatible = "ambiq,apollo510_evb"; + + chosen { + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-pipe = &uart0; + ambiq,xo32m = &xo32m_xtal; + ambiq,xo32k = &xo32k_xtal; + ambiq,extrefclk = &extrefclk; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &led0; + led1 = &led1; + led2 = &led2; + sw0 = &button0; + sw1 = &button1; + }; + + sram0: memory@SSRAM_BASE_NAME { + compatible = "mmio-sram"; + reg = ; + }; + + sram_no_cache: memory@20280000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20280000 0x100000>; + zephyr,memory-region = "SRAM_NO_CACHE"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio160_191 5 GPIO_ACTIVE_LOW>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpio64_95 25 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + + led2: led_2 { + gpios = <&gpio64_95 28 GPIO_ACTIVE_LOW>; + label = "LED 2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + polling-mode; + + button0: button_0 { + gpios = <&gpio64_95 29 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BTN0"; + zephyr,code = ; + status = "okay"; + }; + + button1: button_1 { + gpios = <&gpio64_95 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BTN1"; + zephyr,code = ; + status = "okay"; + }; + }; +}; + +&xo32m_xtal { + clock-frequency = ; +}; + +&itm { + pinctrl-0 = <&swo_default>; + pinctrl-names = "default"; +}; + +&adc0 { + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&counter0 { + status = "disabled"; +}; + +&rtc0 { + status = "disabled"; + clock = "XTAL"; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&stimer0 { + clk-source = <3>; +}; + +&wdt0 { + status = "okay"; +}; + +&gpio0_31 { + status = "okay"; +}; + +&gpio32_63 { + status = "okay"; +}; + +&gpio64_95 { + status = "okay"; +}; + +&gpio96_127 { + status = "okay"; +}; + +&gpio128_159 { + status = "okay"; +}; + +&gpio160_191 { + status = "okay"; +}; + +&gpio192_223 { + status = "okay"; +}; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.yaml b/boards/ambiq/apollo510_evb/apollo510_evb.yaml new file mode 100644 index 000000000000..ca2353540b48 --- /dev/null +++ b/boards/ambiq/apollo510_evb/apollo510_evb.yaml @@ -0,0 +1,26 @@ +identifier: apollo510_evb +name: Apollo510 EVB +type: mcu +arch: arm +ram: 3072 +flash: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - adc + - watchdog + - counter + - gpio + - spi + - i2c + - rtc + - hwinfo + - clock_control + - mspi +testing: + ignore_tags: + - net + - bluetooth +vendor: ambiq diff --git a/boards/ambiq/apollo510_evb/apollo510_evb_defconfig b/boards/ambiq/apollo510_evb/apollo510_evb_defconfig new file mode 100644 index 000000000000..de397a65fbdc --- /dev/null +++ b/boards/ambiq/apollo510_evb/apollo510_evb_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_ARM_MPU=y +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y diff --git a/boards/ambiq/apollo510_evb/board.c b/boards/ambiq/apollo510_evb/board.c new file mode 100644 index 000000000000..b3cc847698c0 --- /dev/null +++ b/boards/ambiq/apollo510_evb/board.c @@ -0,0 +1,57 @@ +/* + * Copyright 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#if DT_HAS_CHOSEN(ambiq_xo32m) +#define XTAL_HS_FREQ DT_PROP(DT_CHOSEN(ambiq_xo32m), clock_frequency) +#if DT_SAME_NODE(DT_CHOSEN(ambiq_xo32m), DT_NODELABEL(xo32m_xtal)) +#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_XTAL +#elif DT_SAME_NODE(DT_CHOSEN(ambiq_xo32m), DT_NODELABEL(xo32m_ext)) +#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_EXT +#endif +#else +#define XTAL_HS_FREQ 0 +#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_XTAL +#endif + +#if DT_HAS_CHOSEN(ambiq_xo32k) +#define XTAL_LS_FREQ DT_PROP(DT_CHOSEN(ambiq_xo32k), clock_frequency) +#if DT_SAME_NODE(DT_CHOSEN(ambiq_xo32k), DT_NODELABEL(xo32k_xtal)) +#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_XTAL +#elif DT_SAME_NODE(DT_CHOSEN(ambiq_xo32k), DT_NODELABEL(xo32k_ext)) +#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_EXT +#endif +#else +#define XTAL_LS_FREQ 0 +#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_XTAL +#endif + +#if DT_HAS_CHOSEN(ambiq_extrefclk) +#define EXTREFCLK_FREQ DT_PROP(DT_CHOSEN(ambiq_extrefclk), clock_frequency) +#else +#define EXTREFCLK_FREQ 0 +#endif + +void board_early_init_hook(void) +{ + /* Set board related info into clock manager */ + am_hal_clkmgr_board_info_t sClkmgrBoardInfo = {.sXtalHs.eXtalHsMode = XTAL_HS_MODE, + .sXtalHs.ui32XtalHsFreq = XTAL_HS_FREQ, + .sXtalLs.eXtalLsMode = XTAL_LS_MODE, + .sXtalLs.ui32XtalLsFreq = XTAL_LS_FREQ, + .ui32ExtRefClkFreq = EXTREFCLK_FREQ}; + am_hal_clkmgr_board_info_set(&sClkmgrBoardInfo); + + /* Default HFRC and HFRC2 to Free Running clocks */ + am_hal_clkmgr_clock_config(AM_HAL_CLKMGR_CLK_ID_HFRC, + AM_HAL_CLKMGR_HFRC_FREQ_FREE_RUN_APPROX_48MHZ, NULL); + am_hal_clkmgr_clock_config(AM_HAL_CLKMGR_CLK_ID_HFRC2, + AM_HAL_CLKMGR_HFRC2_FREQ_FREE_RUN_APPROX_250MHZ, NULL); + +} diff --git a/boards/ambiq/apollo510_evb/board.cmake b/boards/ambiq/apollo510_evb/board.cmake new file mode 100644 index 000000000000..f4ec9988f02f --- /dev/null +++ b/boards/ambiq/apollo510_evb/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Ambiq Micro Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=AP510NFA-CBR" "--iface=swd" "--speed=1000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ambiq/apollo510_evb/board.yml b/boards/ambiq/apollo510_evb/board.yml new file mode 100644 index 000000000000..b42efb3b4529 --- /dev/null +++ b/boards/ambiq/apollo510_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: apollo510_evb + full_name: Apollo510 SOC Evaluation Board + vendor: ambiq + socs: + - name: apollo510 diff --git a/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg b/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg new file mode 100644 index 000000000000..906b08bae267 Binary files /dev/null and b/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg differ diff --git a/boards/ambiq/apollo510_evb/doc/index.rst b/boards/ambiq/apollo510_evb/doc/index.rst new file mode 100644 index 000000000000..82916942776c --- /dev/null +++ b/boards/ambiq/apollo510_evb/doc/index.rst @@ -0,0 +1,75 @@ +.. zephyr:board:: apollo510_evb + +Apollo510 EVB is a board by Ambiq featuring their ultra-low power Apollo510 SoC. + +Hardware +******** + +- Apollo510 SoC with up to 250 MHz operating frequency +- ARM® Cortex® M55 core +- 64 kB Instruction Cache and 64 kB Data Cache +- Up to 4 MB of non-volatile memory (NVM) for code/data +- Up to 3 MB of low leakage / low power RAM for code/data +- 256 kB Instruction Tightly Coupled RAM (ITCM) +- 512 kB Data Tightly Coupled RAM (DTCM) + +For more information about the Apollo510 SoC and Apollo510 EVB board: + +- `Apollo510 Website`_ +- `Apollo510 Datasheet`_ +- `Apollo510 EVB Website`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +========================= + +.. zephyr:board-supported-runners:: + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo510_evb + :goals: flash + +.. note:: + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo510_evb + +.. _Apollo510 Website: + https://ambiq.com/apollo510/ + +.. _Apollo510 Datasheet: + https://contentportal.ambiq.com/documents/20123/2877485/Apollo510-SoC-Datasheet.pdf + +.. _Apollo510 EVB Website: + For more information, please reach out to Sales and FAE. + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts b/boards/amd/acp_6_0_adsp/acp_6_0_adsp.dts similarity index 100% rename from boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts rename to boards/amd/acp_6_0_adsp/acp_6_0_adsp.dts diff --git a/boards/amd/acp_6_0_adsp/doc/index.rst b/boards/amd/acp_6_0_adsp/doc/index.rst index fcc9221eafc2..2812516f28ef 100644 --- a/boards/amd/acp_6_0_adsp/doc/index.rst +++ b/boards/amd/acp_6_0_adsp/doc/index.rst @@ -26,15 +26,7 @@ Hardware Supported Features ================== -The following hardware features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| I2S | on-chip | I2S controller | -+-----------+------------+-------------------------------------+ -| DMIC(PDM) | on-chip | PDM controller | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System Clock ============ @@ -77,6 +69,8 @@ The bottom three variables are specific to acp_6_0. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Building ======== diff --git a/boards/amd/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst index 9383dbd9df61..d939718e58aa 100644 --- a/boards/amd/kv260_r5/doc/index.rst +++ b/boards/amd/kv260_r5/doc/index.rst @@ -19,20 +19,7 @@ Hardware Supported Features ================== -The following hardware features are supported: - -+--------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+============+======================+ -| GIC | on-chip | generic interrupt | -| | | controller | -+--------------+------------+----------------------+ -| TTC | on-chip | system timer | -+--------------+------------+----------------------+ -| UART | on-chip | serial port | -+--------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. +.. zephyr:board-supported-hw:: Devices ======== @@ -68,6 +55,8 @@ The following platform features are unsupported: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Currently the best way to run this sample is by loading it through remoteproc from the APU, running Linux, to the RPU, assuming the target board has a compatible Linux kernel. diff --git a/boards/amd/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts index 85fb1c268917..53ec1923e5d0 100644 --- a/boards/amd/kv260_r5/kv260_r5.dts +++ b/boards/amd/kv260_r5/kv260_r5.dts @@ -19,6 +19,17 @@ zephyr,shell-uart = &uart1; zephyr,ocm = &ocm; }; + + aliases { + eeprom-0 = &eeprom0; + eeprom-1 = &eeprom1; + }; + + i2c_ref_clk: i2c_ref_clk { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; }; &uart1 { @@ -35,3 +46,29 @@ &psgpio { status = "okay"; }; + +&i2c1 { + status = "okay"; + clocks = <&i2c_ref_clk>; + clock-frequency = <400000>; + + eeprom0: eeprom@50 { + compatible = "st,24c64", "atmel,at24"; + reg = <0x50>; + size = ; + pagesize = <32>; + address-width = <16>; + timeout = <5>; + read-only; + }; + + eeprom1: eeprom@51 { + compatible = "st,24c64", "atmel,at24"; + reg = <0x51>; + size = ; + pagesize = <32>; + address-width = <16>; + timeout = <5>; + read-only; + }; +}; diff --git a/boards/amd/kv260_r5/kv260_r5.yaml b/boards/amd/kv260_r5/kv260_r5.yaml index 9cc92025e91e..aa13a0350d58 100644 --- a/boards/amd/kv260_r5/kv260_r5.yaml +++ b/boards/amd/kv260_r5/kv260_r5.yaml @@ -5,6 +5,10 @@ toolchain: - zephyr ram: 65536 flash: 32768 +supported: + - i2c + - eeprom + - gpio testing: ignore_tags: - net diff --git a/boards/amd/kv260_r5/kv260_r5_defconfig b/boards/amd/kv260_r5/kv260_r5_defconfig index 4b86de20d6b9..f1bfa8f67074 100644 --- a/boards/amd/kv260_r5/kv260_r5_defconfig +++ b/boards/amd/kv260_r5/kv260_r5_defconfig @@ -13,5 +13,9 @@ CONFIG_UART_CONSOLE=y # Enable serial port CONFIG_UART_XLNX_PS=y +# Enable I2C, EEPROM +CONFIG_I2C=y +CONFIG_EEPROM=y + CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_ARM_MPU=y diff --git a/boards/amd/versal2_rpu/CMakeLists.txt b/boards/amd/versal2_rpu/CMakeLists.txt new file mode 100644 index 000000000000..bd0a687ea487 --- /dev/null +++ b/boards/amd/versal2_rpu/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# + +find_package(Dtc 1.4.6 REQUIRED) + +# Check if the board-specific qemu.dts file exists +if(EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts") + # Ensure DTC executable is available + if(DTC_FOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${DTC} -I dts -O dtb -q "${BOARD_DIR}/${BOARD}-qemu.dts" -o "${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb" + ) + else() + message(FATAL_ERROR "DTC not found, but required for compiling ${BOARD}-qemu.dts") + endif() +endif() diff --git a/boards/amd/versal2_rpu/Kconfig.versal2_rpu b/boards/amd/versal2_rpu/Kconfig.versal2_rpu new file mode 100644 index 000000000000..8317003f3ff3 --- /dev/null +++ b/boards/amd/versal2_rpu/Kconfig.versal2_rpu @@ -0,0 +1,8 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_VERSAL2_RPU + select SOC_AMD_VERSAL2_RPU diff --git a/boards/amd/versal2_rpu/board.cmake b/boards/amd/versal2_rpu/board.cmake new file mode 100644 index 000000000000..c03f2a1a98e6 --- /dev/null +++ b/boards/amd/versal2_rpu/board.cmake @@ -0,0 +1,22 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) +set(QEMU_CPU_TYPE_${ARCH} cortex-a78ae) + +set(QEMU_FLAGS_${ARCH} + -machine arm-generic-fdt + -hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb + -device loader,addr=0xEB5E0310,data=0x2,data-len=4 + -nographic + -m 2g +) + +set(QEMU_KERNEL_OPTION + -device loader,cpu-num=8,file=\$ +) diff --git a/boards/amd/versal2_rpu/board.yml b/boards/amd/versal2_rpu/board.yml new file mode 100644 index 000000000000..744fc6acdd58 --- /dev/null +++ b/boards/amd/versal2_rpu/board.yml @@ -0,0 +1,6 @@ +board: + name: versal2_rpu + full_name: Versal 2 RPU development board + vendor: amd + socs: + - name: amd_versal2_rpu diff --git a/boards/amd/versal2_rpu/doc/index.rst b/boards/amd/versal2_rpu/doc/index.rst new file mode 100644 index 000000000000..44e4b707e051 --- /dev/null +++ b/boards/amd/versal2_rpu/doc/index.rst @@ -0,0 +1,73 @@ +.. zephyr:board:: versal2_rpu + +Overview +******** +This configuration provides support for the RPU(R52), real-time processing unit on Xilinx +Versal2 SOC, it can operate as following: + +* Two independent R52 cores with their own TCMs (tightly coupled memories) +* Or as a single dual lock step unit with the TCM. + +This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices: + +* ARM GIC v3 Interrupt Controller +* Global Timer Counter +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The ocm0 memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Only the first core of the R52 subsystem is supported. + +Programming and Debugging +************************* + +Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versal2_rpu + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! versal2_rpu/amd_versal2_rpu + + +References +********** + +1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520) +2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en) diff --git a/boards/amd/versal2_rpu/support/xsdb.cfg b/boards/amd/versal2_rpu/support/xsdb.cfg new file mode 100644 index 000000000000..88313923170d --- /dev/null +++ b/boards/amd/versal2_rpu/support/xsdb.cfg @@ -0,0 +1,78 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc rpu0_core0_rst { {mem "default"} } { + targets -set -filter {name =~ "DAP*"} + #CRL write protect + mwr -force 0xeb5e001c 0x0 + mwr -force 0xEB580000 1 + mwr -force 0xbbf20000 0xeafffffe + # write BASE_HI and BASE_LO + if {$mem eq "ddr"} { + set addr 0x100000 + } elseif {$mem eq "tcm"} { + set addr 0x0 + } elseif {$mem eq "default"} { + set addr 0xbbf20000 + } + mwr -force 0xEB588008 $addr + # write TCMBOOT as one + mask_write 0xEB588000 0x10 0x10 + # reset CORE0A_RESET out of reset A_TOPRESET and CORE0A_POR + mask_write 0xEB5E0310 0x10101 0x1 + # out of reset CORE0A_RESET + mask_write 0xEB5E0310 0x1 0x0 + targets -set -filter {name =~ "Cortex-R52*0" && parent =~ "*0x00100000"} + after 300 + stop + after 1000 + ta +} + + +proc load_image args { + set elf_file [lindex $args 0] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + if { [info exists ::env(PDI_FILE_PATH)] } { + device program $::env(PDI_FILE_PATH) + } else { + puts "Error: env variable PDI_FILE_PATH is not set" + exit + } + + if { [info exists ::env(HW_SERVER_URL)] } { + set hw_server_url [split $::env(HW_SERVER_URL) ":"] + set host [lindex $hw_server_url 0] + set port [lindex $hw_server_url 1] + disconnect + after 2000 + connect -host $host -port $port + after 3000 + ta + } + after 1000 + targets -set -nocase -filter {name =~ "DAP*"} + after 100 + # Configure timestamp generator to run global timer gracefully + # Ideally these registers should be set from bootloader (cdo) + + mwr -force 0xea470020 100000000 + mwr -force 0xea470000 0x1 + after 100 + + rpu0_core0_rst + + after 100 + dow -force $elf_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts new file mode 100644 index 000000000000..f888f1a17c5c --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts @@ -0,0 +1,7832 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + + pmc_ppu0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x248>; + phandle = <0x108>; + }; + + pmc_ppu1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x249>; + phandle = <0x109>; + }; + + psm_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x238>; + phandle = <0x10a>; + }; + + ddrmc_ub0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0x10b>; + }; + + ddrmc_ub1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0x10c>; + }; + + pmc_dma0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x24a>; + phandle = <0x8b>; + }; + + pmc_dma1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x24b>; + phandle = <0x8c>; + }; + + pmc_qspi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x7d>; + }; + + pmc_qspi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x7b>; + }; + + apu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x260>; + phandle = <0xd3>; + }; + + apu0_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x260>; + phandle = <0xd4>; + }; + + apu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x261>; + phandle = <0xd5>; + }; + + apu1_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x261>; + phandle = <0xd6>; + }; + + rpu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x200>; + phandle = <0xe4>; + }; + + rpu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x204>; + phandle = <0xe7>; + }; + + gem0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x18>; + }; + + gem0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x19>; + }; + + gem1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x1d>; + }; + + gem1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x1e>; + }; + + ospi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x81>; + }; + + ospi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x7c>; + }; + + sd0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x77>; + }; + + sd0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x78>; + }; + + sd1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x79>; + }; + + sd1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x7a>; + }; + + usb0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x230>; + phandle = <0x20>; + }; + + amba_root@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0xffff>; + interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x01 +0x04 0x00 0x00 0x02 0x01 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x03 0x04 0x00 0x00 0x04 0x01 +0x00 0x04 0x04 0x00 0x00 0x05 0x01 0x00 0x05 0x04 0x00 0x00 0x06 0x01 0x00 0x06 0x04 0x00 +0x00 0x07 0x01 0x00 0x07 0x04 0x00 0x00 0x08 0x01 0x00 0x08 0x04 0x00 0x00 0x09 0x01 0x00 +0x09 0x04 0x00 0x00 0x0a 0x01 0x00 0x0a 0x04 0x00 0x00 0x0b 0x01 0x00 0x0b 0x04 0x00 0x00 +0x0c 0x01 0x00 0x0c 0x04 0x00 0x00 0x0d 0x01 0x00 0x0d 0x04 0x00 0x00 0x0e 0x01 0x00 0x0e +0x04 0x00 0x00 0x0f 0x01 0x00 0x0f 0x04 0x00 0x00 0x10 0x01 0x00 0x10 0x04 0x00 0x00 0x11 +0x01 0x00 0x11 0x04 0x00 0x00 0x12 0x01 0x00 0x12 0x04 0x00 0x00 0x13 0x01 0x00 0x13 0x04 +0x00 0x00 0x14 0x01 0x00 0x14 0x04 0x00 0x00 0x15 0x01 0x00 0x15 0x04 0x00 0x00 0x16 0x01 +0x00 0x16 0x04 0x00 0x00 0x17 0x01 0x00 0x17 0x04 0x00 0x00 0x18 0x01 0x00 0x18 0x04 0x00 +0x00 0x19 0x01 0x00 0x19 0x04 0x00 0x00 0x1a 0x01 0x00 0x1a 0x04 0x00 0x00 0x1b 0x01 0x00 +0x1b 0x04 0x00 0x00 0x1c 0x01 0x00 0x1c 0x04 0x00 0x00 0x1d 0x01 0x00 0x1d 0x04 0x00 0x00 +0x1e 0x01 0x00 0x1e 0x04 0x00 0x00 0x1f 0x01 0x00 0x1f 0x04 0x00 0x00 0x20 0x01 0x00 0x20 +0x04 0x00 0x00 0x21 0x01 0x00 0x21 0x04 0x00 0x00 0x22 0x01 0x00 0x22 0x04 0x00 0x00 0x23 +0x01 0x00 0x23 0x04 0x00 0x00 0x24 0x01 0x00 0x24 0x04 0x00 0x00 0x25 0x01 0x00 0x25 0x04 +0x00 0x00 0x26 0x01 0x00 0x26 0x04 0x00 0x00 0x27 0x01 0x00 0x27 0x04 0x00 0x00 0x28 0x01 +0x00 0x28 0x04 0x00 0x00 0x29 0x01 0x00 0x29 0x04 0x00 0x00 0x2a 0x01 0x00 0x2a 0x04 0x00 +0x00 0x2b 0x01 0x00 0x2b 0x04 0x00 0x00 0x2c 0x01 0x00 0x2c 0x04 0x00 0x00 0x2d 0x01 0x00 +0x2d 0x04 0x00 0x00 0x2e 0x01 0x00 0x2e 0x04 0x00 0x00 0x2f 0x01 0x00 0x2f 0x04 0x00 0x00 +0x30 0x01 0x00 0x30 0x04 0x00 0x00 0x31 0x01 0x00 0x31 0x04 0x00 0x00 0x32 0x01 0x00 0x32 +0x04 0x00 0x00 0x33 0x01 0x00 0x33 0x04 0x00 0x00 0x34 0x01 0x00 0x34 0x04 0x00 0x00 0x35 +0x01 0x00 0x35 0x04 0x00 0x00 0x36 0x01 0x00 0x36 0x04 0x00 0x00 0x37 0x01 0x00 0x37 0x04 +0x00 0x00 0x38 0x01 0x00 0x38 0x04 0x00 0x00 0x39 0x01 0x00 0x39 0x04 0x00 0x00 0x3a 0x01 +0x00 0x3a 0x04 0x00 0x00 0x3b 0x01 0x00 0x3b 0x04 0x00 0x00 0x3c 0x01 0x00 0x3c 0x04 0x00 +0x00 0x3d 0x01 0x00 0x3d 0x04 0x00 0x00 0x3e 0x01 0x00 0x3e 0x04 0x00 0x00 0x3f 0x01 0x00 +0x3f 0x04 0x00 0x00 0x40 0x01 0x00 0x40 0x04 0x00 0x00 0x41 0x01 0x00 0x41 0x04 0x00 0x00 +0x42 0x01 0x00 0x42 0x04 0x00 0x00 0x43 0x01 0x00 0x43 0x04 0x00 0x00 0x44 0x01 0x00 0x44 +0x04 0x00 0x00 0x45 0x01 0x00 0x45 0x04 0x00 0x00 0x46 0x01 0x00 0x46 0x04 0x00 0x00 0x47 +0x01 0x00 0x47 0x04 0x00 0x00 0x48 0x01 0x00 0x48 0x04 0x00 0x00 0x49 0x01 0x00 0x49 0x04 +0x00 0x00 0x4a 0x01 0x00 0x4a 0x04 0x00 0x00 0x4b 0x01 0x00 0x4b 0x04 0x00 0x00 0x4c 0x01 +0x00 0x4c 0x04 0x00 0x00 0x4d 0x01 0x00 0x4d 0x04 0x00 0x00 0x4e 0x01 0x00 0x4e 0x04 0x00 +0x00 0x4f 0x01 0x00 0x4f 0x04 0x00 0x00 0x50 0x01 0x00 0x50 0x04 0x00 0x00 0x51 0x01 0x00 +0x51 0x04 0x00 0x00 0x52 0x01 0x00 0x52 0x04 0x00 0x00 0x53 0x01 0x00 0x53 0x04 0x00 0x00 +0x54 0x01 0x00 0x54 0x04 0x00 0x00 0x55 0x01 0x00 0x55 0x04 0x00 0x00 0x56 0x01 0x00 0x56 +0x04 0x00 0x00 0x57 0x01 0x00 0x57 0x04 0x00 0x00 0x58 0x01 0x00 0x58 0x04 0x00 0x00 0x59 +0x01 0x00 0x59 0x04 0x00 0x00 0x5a 0x01 0x00 0x5a 0x04 0x00 0x00 0x5b 0x01 0x00 0x5b 0x04 +0x00 0x00 0x5c 0x01 0x00 0x5c 0x04 0x00 0x00 0x5d 0x01 0x00 0x5d 0x04 0x00 0x00 0x5e 0x01 +0x00 0x5e 0x04 0x00 0x00 0x5f 0x01 0x00 0x5f 0x04 0x00 0x00 0x60 0x01 0x00 0x60 0x04 0x00 +0x00 0x61 0x01 0x00 0x61 0x04 0x00 0x00 0x62 0x01 0x00 0x62 0x04 0x00 0x00 0x63 0x01 0x00 +0x63 0x04 0x00 0x00 0x64 0x01 0x00 0x64 0x04 0x00 0x00 0x65 0x01 0x00 0x65 0x04 0x00 0x00 +0x66 0x01 0x00 0x66 0x04 0x00 0x00 0x67 0x01 0x00 0x67 0x04 0x00 0x00 0x68 0x01 0x00 0x68 +0x04 0x00 0x00 0x69 0x01 0x00 0x69 0x04 0x00 0x00 0x6a 0x01 0x00 0x6a 0x04 0x00 0x00 0x6b +0x01 0x00 0x6b 0x04 0x00 0x00 0x6c 0x01 0x00 0x6c 0x04 0x00 0x00 0x6d 0x01 0x00 0x6d 0x04 +0x00 0x00 0x6e 0x01 0x00 0x6e 0x04 0x00 0x00 0x6f 0x01 0x00 0x6f 0x04 0x00 0x00 0x70 0x01 +0x00 0x70 0x04 0x00 0x00 0x71 0x01 0x00 0x71 0x04 0x00 0x00 0x72 0x01 0x00 0x72 0x04 0x00 +0x00 0x73 0x01 0x00 0x73 0x04 0x00 0x00 0x74 0x01 0x00 0x74 0x04 0x00 0x00 0x75 0x01 0x00 +0x75 0x04 0x00 0x00 0x76 0x01 0x00 0x76 0x04 0x00 0x00 0x77 0x01 0x00 0x77 0x04 0x00 0x00 +0x78 0x01 0x00 0x78 0x04 0x00 0x00 0x79 0x01 0x00 0x79 0x04 0x00 0x00 0x7a 0x01 0x00 0x7a +0x04 0x00 0x00 0x7b 0x01 0x00 0x7b 0x04 0x00 0x00 0x7c 0x01 0x00 0x7c 0x04 0x00 0x00 0x7d +0x01 0x00 0x7d 0x04 0x00 0x00 0x7e 0x01 0x00 0x7e 0x04 0x00 0x00 0x7f 0x01 0x00 0x7f 0x04 +0x00 0x00 0x80 0x01 0x00 0x80 0x04 0x00 0x00 0x81 0x01 0x00 0x81 0x04 0x00 0x00 0x82 0x01 +0x00 0x82 0x04 0x00 0x00 0x83 0x01 0x00 0x83 0x04 0x00 0x00 0x84 0x01 0x00 0x84 0x04 0x00 +0x00 0x85 0x01 0x00 0x85 0x04 0x00 0x00 0x86 0x01 0x00 0x86 0x04 0x00 0x00 0x87 0x01 0x00 +0x87 0x04 0x00 0x00 0x88 0x01 0x00 0x88 0x04 0x00 0x00 0x89 0x01 0x00 0x89 0x04 0x00 0x00 +0x8a 0x01 0x00 0x8a 0x04 0x00 0x00 0x8b 0x01 0x00 0x8b 0x04 0x00 0x00 0x8c 0x01 0x00 0x8c +0x04 0x00 0x00 0x8d 0x01 0x00 0x8d 0x04 0x00 0x00 0x8e 0x01 0x00 0x8e 0x04 0x00 0x00 0x8f +0x01 0x00 0x8f 0x04 0x00 0x00 0x90 0x01 0x00 0x90 0x04 0x00 0x00 0x91 0x01 0x00 0x91 0x04 +0x00 0x00 0x92 0x01 0x00 0x92 0x04 0x00 0x00 0x93 0x01 0x00 0x93 0x04 0x00 0x00 0x94 0x01 +0x00 0x94 0x04 0x00 0x00 0x95 0x01 0x00 0x95 0x04 0x00 0x00 0x96 0x01 0x00 0x96 0x04 0x00 +0x00 0x97 0x01 0x00 0x97 0x04 0x00 0x00 0x98 0x01 0x00 0x98 0x04 0x00 0x00 0x99 0x01 0x00 +0x99 0x04 0x00 0x00 0x9a 0x01 0x00 0x9a 0x04 0x00 0x00 0x9b 0x01 0x00 0x9b 0x04 0x00 0x00 +0x9c 0x01 0x00 0x9c 0x04 0x00 0x00 0x9d 0x01 0x00 0x9d 0x04 0x00 0x00 0x9e 0x01 0x00 0x9e +0x04 0x00 0x00 0x9f 0x01 0x00 0x9f 0x04 0x00 0x00 0xa0 0x01 0x00 0xa0 0x04 0x00 0x00 0xa1 +0x01 0x00 0xa1 0x04 0x00 0x00 0xa2 0x01 0x00 0xa2 0x04 0x00 0x00 0xa3 0x01 0x00 0xa3 0x04 +0x00 0x00 0xa4 0x01 0x00 0xa4 0x04 0x00 0x00 0xa5 0x01 0x00 0xa5 0x04 0x00 0x00 0xa6 0x01 +0x00 0xa6 0x04 0x00 0x00 0xa7 0x01 0x00 0xa7 0x04 0x00 0x00 0xa8 0x01 0x00 0xa8 0x04 0x00 +0x00 0xa9 0x01 0x00 0xa9 0x04 0x00 0x00 0xaa 0x01 0x00 0xaa 0x04 0x00 0x00 0xab 0x01 0x00 +0xab 0x04 0x00 0x00 0xac 0x01 0x00 0xac 0x04 0x00 0x00 0xad 0x01 0x00 0xad 0x04 0x00 0x00 +0xae 0x01 0x00 0xae 0x04 0x00 0x00 0xaf 0x01 0x00 0xaf 0x04 0x00 0x00 0xb0 0x01 0x00 0xb0 +0x04 0x00 0x00 0xb1 0x01 0x00 0xb1 0x04 0x00 0x00 0xb2 0x01 0x00 0xb2 0x04 0x00 0x00 0xb3 +0x01 0x00 0xb3 0x04 0x00 0x00 0xb4 0x01 0x00 0xb4 0x04 0x00 0x00 0xb5 0x01 0x00 0xb5 0x04 +0x00 0x00 0xb6 0x01 0x00 0xb6 0x04 0x00 0x00 0xb7 0x01 0x00 0xb7 0x04 0x00 0x00 0xb8 0x01 +0x00 0xb8 0x04 0x00 0x00 0xb9 0x01 0x00 0xb9 0x04 0x00 0x00 0xba 0x01 0x00 0xba 0x04 0x00 +0x00 0xbb 0x01 0x00 0xbb 0x04 0x00 0x00 0xbc 0x01 0x00 0xbc 0x04 0x00 0x00 0xbd 0x01 0x00 +0xbd 0x04 0x00 0x00 0xbe 0x01 0x00 0xbe 0x04 0x00 0x00 0xbf 0x01 0x00 0xbf 0x04 0x00 0x00 +0xc0 0x01 0x00 0xc0 0x04 0x00 0x00 0xc1 0x01 0x00 0xc1 0x04 0x00 0x00 0xc2 0x01 0x00 0xc2 +0x04 0x00 0x00 0xc3 0x01 0x00 0xc3 0x04 0x00 0x00 0xc4 0x01 0x00 0xc4 0x04 0x00 0x00 0xc5 +0x01 0x00 0xc5 0x04 0x00 0x00 0xc6 0x01 0x00 0xc6 0x04 0x00 0x00 0xc7 0x01 0x00 0xc7 0x04 +0x00 0x00 0xc8 0x01 0x00 0xc8 0x04 0x00 0x00 0xc9 0x01 0x00 0xc9 0x04 0x00 0x00 0xca 0x01 +0x00 0xca 0x04 0x00 0x00 0xcb 0x01 0x00 0xcb 0x04 0x00 0x00 0xcc 0x01 0x00 0xcc 0x04 0x00 +0x00 0xcd 0x01 0x00 0xcd 0x04 0x00 0x00 0xce 0x01 0x00 0xce 0x04 0x00 0x00 0xcf 0x01 0x00 +0xcf 0x04 0x00 0x00 0xd0 0x01 0x00 0xd0 0x04 0x00 0x00 0xd1 0x01 0x00 0xd1 0x04 0x00 0x00 +0xd2 0x01 0x00 0xd2 0x04 0x00 0x00 0xd3 0x01 0x00 0xd3 0x04 0x00 0x00 0xd4 0x01 0x00 0xd4 +0x04 0x00 0x00 0xd5 0x01 0x00 0xd5 0x04 0x00 0x00 0xd6 0x01 0x00 0xd6 0x04 0x00 0x00 0xd7 +0x01 0x00 0xd7 0x04 0x00 0x00 0xd8 0x01 0x00 0xd8 0x04 0x00 0x00 0xd9 0x01 0x00 0xd8 0x04 +0x00 0x00 0xda 0x01 0x00 0xda 0x04 0x00 0x00 0xdb 0x01 0x00 0xdb 0x04 0x00 0x00 0xdc 0x01 +0x00 0xdc 0x04 0x00 0x00 0xdd 0x01 0x00 0xdd 0x04 0x00 0x00 0xde 0x01 0x00 0xde 0x04 0x00 +0x00 0xdf 0x01 0x00 0xdf 0x04 0x00 0x00 0xe0 0x01 0x00 0xe0 0x04 0x00 0x00 0xe1 0x01 0x00 +0xe1 0x04 0x00 0x00 0xe2 0x01 0x00 0xe2 0x04 0x00 0x00 0xe3 0x01 0x00 0xe3 0x04 0x00 0x00 +0xe4 0x01 0x00 0xe4 0x04 0x00 0x00 0xe5 0x01 0x00 0xe5 0x04 0x00 0x00 0xe6 0x01 0x00 0xe6 +0x04 0x00 0x00 0xe7 0x01 0x00 0xe7 0x04 0x00 0x00 0xe8 0x01 0x00 0xe8 0x04 0x00 0x00 0xe9 +0x01 0x00 0xe9 0x04 0x00 0x00 0xea 0x01 0x00 0xea 0x04 0x00 0x00 0xeb 0x01 0x00 0xeb 0x04 +0x00 0x00 0xec 0x01 0x00 0xec 0x04 0x00 0x00 0xed 0x01 0x00 0xed 0x04 0x00 0x00 0xee 0x01 +0x00 0xee 0x04 0x00 0x00 0xef 0x01 0x00 0xef 0x04 0x00 0x00 0xf0 0x01 0x00 0xf0 0x04 0x00 +0x00 0xf1 0x01 0x00 0xf1 0x04 0x00 0x00 0xf2 0x01 0x00 0xf2 0x04 0x00 0x00 0xf3 0x01 0x00 +0xf3 0x04 0x00 0x00 0xf4 0x01 0x00 0xf4 0x04 0x00 0x00 0xf5 0x01 0x00 0xf5 0x04 0x00 0x00 +0xf6 0x01 0x00 0xf6 0x04 0x00 0x00 0xf7 0x01 0x00 0xf7 0x04 0x00 0x00 0xf8 0x01 0x00 0xf8 +0x04 0x00 0x00 0xf9 0x01 0x00 0xf9 0x04 0x00 0x00 0xfa 0x01 0x00 0xfa 0x04 0x00 0x00 0xfb +0x01 0x00 0xfb 0x04 0x00 0x00 0xfc 0x01 0x00 0xfc 0x04 0x00 0x00 0xfd 0x01 0x00 0xfd 0x04 +0x00 0x00 0xfe 0x01 0x00 0xfe 0x04 0x00 0x00 0xff 0x01 0x00 0xff 0x04 0x00 0x00 0xa0 0x01 +0x00 0xa0 0x04 0x00 0x00 0x00 0x02 0x00 0x00 0x04 0x00 0x00 0x01 0x02 0x00 0x01 0x04 0x00 +0x00 0x02 0x02 0x00 0x02 0x04 0x00 0x00 0x03 0x02 0x00 0x03 0x04 0x00 0x00 0x04 0x02 0x00 +0x04 0x04 0x00 0x00 0x05 0x02 0x00 0x05 0x04 0x00 0x00 0x06 0x02 0x00 0x06 0x04 0x00 0x00 +0x07 0x02 0x00 0x07 0x04 0x00 0x00 0x08 0x02 0x00 0x08 0x04 0x00 0x00 0x09 0x02 0x00 0x09 +0x04 0x00 0x00 0x0a 0x02 0x00 0x0a 0x04 0x00 0x00 0x0b 0x02 0x00 0x0b 0x04 0x00 0x00 0x0c +0x02 0x00 0x0c 0x04 0x00 0x00 0x0d 0x02 0x00 0x0d 0x04 0x00 0x00 0x0e 0x02 0x00 0x0e 0x04 +0x00 0x00 0x0f 0x02 0x00 0x0f 0x04 0x00 0x00 0x10 0x02 0x00 0x10 0x04 0x00 0x00 0x11 0x02 +0x00 0x11 0x04 0x00 0x00 0x12 0x02 0x00 0x12 0x04 0x00 0x00 0x13 0x02 0x00 0x13 0x04 0x00 +0x00 0x14 0x02 0x00 0x14 0x04 0x00 0x00 0x15 0x02 0x00 0x15 0x04 0x00 0x00 0x16 0x02 0x00 +0x16 0x04 0x00 0x00 0x17 0x02 0x00 0x17 0x04 0x00 0x00 0x18 0x02 0x00 0x18 0x04 0x00 0x00 +0x19 0x02 0x00 0x19 0x04 0x00 0x00 0x1a 0x02 0x00 0x1a 0x04 0x00 0x00 0x1b 0x02 0x00 0x1b +0x04 0x00 0x00 0x1c 0x02 0x00 0x1c 0x04 0x00 0x00 0x1d 0x02 0x00 0x1d 0x04 0x00 0x00 0x1e +0x02 0x00 0x1e 0x04 0x00 0x00 0x1f 0x02 0x00 0x1f 0x04 0x00 0x00 0x20 0x02 0x00 0x20 0x04 +0x00 0x00 0x21 0x02 0x00 0x21 0x04 0x00 0x00 0x22 0x02 0x00 0x22 0x04 0x00 0x00 0x23 0x02 +0x00 0x23 0x04 0x00 0x00 0x24 0x02 0x00 0x24 0x04 0x00 0x00 0x25 0x02 0x00 0x25 0x04 0x00 +0x00 0x26 0x02 0x00 0x26 0x04 0x00 0x00 0x27 0x02 0x00 0x27 0x04 0x00 0x00 0x28 0x02 0x00 +0x28 0x04 0x00 0x00 0x29 0x02 0x00 0x29 0x04 0x00 0x00 0x2a 0x02 0x00 0x2a 0x04 0x00 0x00 +0x2b 0x02 0x00 0x2b 0x04 0x00 0x00 0x2c 0x02 0x00 0x2c 0x04 0x00 0x00 0x2d 0x02 0x00 0x2d +0x04 0x00 0x00 0x2e 0x02 0x00 0x2e 0x04 0x00 0x00 0x2f 0x02 0x00 0x2f 0x04 0x00 0x00 0x30 +0x02 0x00 0x30 0x04 0x00 0x00 0x31 0x02 0x00 0x31 0x04 0x00 0x00 0x32 0x02 0x00 0x32 0x04 +0x00 0x00 0x33 0x02 0x00 0x33 0x04 0x00 0x00 0x34 0x02 0x00 0x34 0x04 0x00 0x00 0x35 0x02 +0x00 0x35 0x04 0x00 0x00 0x36 0x02 0x00 0x36 0x04 0x00 0x00 0x37 0x02 0x00 0x37 0x04 0x00 +0x00 0x38 0x02 0x00 0x38 0x04 0x00 0x00 0x39 0x02 0x00 0x39 0x04 0x00 0x00 0x3a 0x02 0x00 +0x3a 0x04 0x00 0x00 0x3b 0x02 0x00 0x3b 0x04 0x00 0x00 0x3c 0x02 0x00 0x3c 0x04 0x00 0x00 +0x3d 0x02 0x00 0x3d 0x04 0x00 0x00 0x3e 0x02 0x00 0x3e 0x04 0x00 0x00 0x3f 0x02 0x00 0x3f +0x04 0x00 0x00 0x40 0x02 0x00 0x40 0x04 0x00 0x00 0x41 0x02 0x00 0x41 0x04 0x00 0x00 0x42 +0x02 0x00 0x42 0x04 0x00 0x00 0x43 0x02 0x00 0x43 0x04 0x00 0x00 0x44 0x02 0x00 0x44 0x04 +0x00 0x00 0x45 0x02 0x00 0x45 0x04 0x00 0x00 0x46 0x02 0x00 0x46 0x04 0x00 0x00 0x47 0x02 +0x00 0x47 0x04 0x00 0x00 0x48 0x02 0x00 0x48 0x04 0x00 0x00 0x49 0x02 0x00 0x49 0x04 0x00 +0x00 0x4a 0x02 0x00 0x4a 0x04 0x00 0x00 0x4b 0x02 0x00 0x4b 0x04 0x00 0x00 0x4c 0x02 0x00 +0x4c 0x04 0x00 0x00 0x4d 0x02 0x00 0x4d 0x04 0x00 0x00 0x4e 0x02 0x00 0x4e 0x04 0x00 0x00 +0x4f 0x02 0x00 0x4f 0x04 0x00 0x00 0x50 0x02 0x00 0x50 0x04 0x00 0x00 0x51 0x02 0x00 0x51 +0x04 0x00 0x00 0x52 0x02 0x00 0x52 0x04 0x00 0x00 0x53 0x02 0x00 0x53 0x04 0x00 0x00 0x54 +0x02 0x00 0x54 0x04 0x00 0x00 0x55 0x02 0x00 0x55 0x04 0x00 0x00 0x56 0x02 0x00 0x56 0x04 +0x00 0x00 0x57 0x02 0x00 0x57 0x04 0x00 0x00 0x58 0x02 0x00 0x58 0x04 0x00 0x00 0x59 0x02 +0x00 0x59 0x04 0x00 0x00 0x5a 0x02 0x00 0x5a 0x04 0x00 0x00 0x5b 0x02 0x00 0x5b 0x04 0x00 +0x00 0x5c 0x02 0x00 0x5c 0x04 0x00 0x00 0x5d 0x02 0x00 0x5d 0x04 0x00 0x00 0x5e 0x02 0x00 +0x5e 0x04 0x00 0x00 0x5f 0x02 0x00 0x5f 0x04 0x00 0x00 0x60 0x02 0x00 0x60 0x04 0x00 0x00 +0x61 0x02 0x00 0x61 0x04 0x00 0x00 0x62 0x02 0x00 0x62 0x04 0x00 0x00 0x63 0x02 0x00 0x63 +0x04 0x00 0x00 0x64 0x02 0x00 0x64 0x04 0x00 0x00 0x65 0x02 0x00 0x65 0x04 0x00 0x00 0x66 +0x02 0x00 0x66 0x04 0x00 0x00 0x67 0x02 0x00 0x67 0x04 0x00 0x00 0x68 0x02 0x00 0x68 0x04 +0x00 0x00 0x69 0x02 0x00 0x69 0x04 0x00 0x00 0x6a 0x02 0x00 0x6a 0x04 0x00 0x00 0x6b 0x02 +0x00 0x6b 0x04 0x00 0x00 0x6c 0x02 0x00 0x6c 0x04 0x00 0x00 0x6d 0x02 0x00 0x6d 0x04 0x00 +0x00 0x6e 0x02 0x00 0x6e 0x04 0x00 0x00 0x6f 0x02 0x00 0x6f 0x04 0x00 0x00 0x70 0x02 0x00 +0x70 0x04 0x00 0x00 0x71 0x02 0x00 0x71 0x04 0x00 0x00 0x72 0x02 0x00 0x72 0x04 0x00 0x00 +0x73 0x02 0x00 0x73 0x04 0x00 0x00 0x74 0x02 0x00 0x74 0x04 0x00 0x00 0x75 0x02 0x00 0x75 +0x04 0x00 0x00 0x76 0x02 0x00 0x76 0x04 0x00 0x00 0x77 0x02 0x00 0x77 0x04 0x00 0x00 0x78 +0x02 0x00 0x78 0x04 0x00 0x00 0x79 0x02 0x00 0x79 0x04 0x00 0x00 0x7a 0x02 0x00 0x7a 0x04 +0x00 0x00 0x7b 0x02 0x00 0x7b 0x04 0x00 0x00 0x7c 0x02 0x00 0x7c 0x04 0x00 0x00 0x7d 0x02 +0x00 0x7d 0x04 0x00 0x00 0x7e 0x02 0x00 0x7e 0x04 0x00 0x00 0x7f 0x02 0x00 0x7f 0x04 0x00 +0x00 0x80 0x02 0x00 0x80 0x04 0x00 0x00 0x81 0x02 0x00 0x81 0x04 0x00 0x00 0x82 0x02 0x00 +0x82 0x04 0x00 0x00 0x83 0x02 0x00 0x83 0x04 0x00 0x00 0x84 0x02 0x00 0x84 0x04 0x00 0x00 +0x85 0x02 0x00 0x85 0x04 0x00 0x00 0x86 0x02 0x00 0x86 0x04 0x00 0x00 0x87 0x02 0x00 0x87 +0x04 0x00 0x00 0x88 0x02 0x00 0x88 0x04 0x00 0x00 0x89 0x02 0x00 0x89 0x04 0x00 0x00 0x8a +0x02 0x00 0x8a 0x04 0x00 0x00 0x8b 0x02 0x00 0x8b 0x04 0x00 0x00 0x8c 0x02 0x00 0x8c 0x04 +0x00 0x00 0x8d 0x02 0x00 0x8d 0x04 0x00 0x00 0x8e 0x02 0x00 0x8e 0x04 0x00 0x00 0x8f 0x02 +0x00 0x8f 0x04 0x00 0x00 0x90 0x02 0x00 0x90 0x04 0x00 0x00 0x91 0x02 0x00 0x91 0x04 0x00 +0x00 0x92 0x02 0x00 0x92 0x04 0x00 0x00 0x93 0x02 0x00 0x93 0x04 0x00 0x00 0x94 0x02 0x00 +0x94 0x04 0x00 0x00 0x95 0x02 0x00 0x95 0x04 0x00 0x00 0x96 0x02 0x00 0x96 0x04 0x00 0x00 +0x97 0x02 0x00 0x97 0x04 0x00 0x00 0x98 0x02 0x00 0x98 0x04 0x00 0x00 0x99 0x02 0x00 0x99 +0x04 0x00 0x00 0x9a 0x02 0x00 0x9a 0x04 0x00 0x00 0x9b 0x02 0x00 0x9b 0x04 0x00 0x00 0x9c +0x02 0x00 0x9c 0x04 0x00 0x00 0x9d 0x02 0x00 0x9d 0x04 0x00 0x00 0x9e 0x02 0x00 0x9e 0x04 +0x00 0x00 0x9f 0x02 0x00 0x9f 0x04 0x00 0x00 0xa0 0x02 0x00 0xa0 0x04 0x00 0x00 0xa1 0x02 +0x00 0xa1 0x04 0x00 0x00 0xa2 0x02 0x00 0xa2 0x04 0x00 0x00 0xa3 0x02 0x00 0xa3 0x04 0x00 +0x00 0xa4 0x02 0x00 0xa4 0x04 0x00 0x00 0xa5 0x02 0x00 0xa5 0x04 0x00 0x00 0xa6 0x02 0x00 +0xa6 0x04 0x00 0x00 0xa7 0x02 0x00 0xa7 0x04 0x00 0x00 0xa8 0x02 0x00 0xa8 0x04 0x00 0x00 +0xa9 0x02 0x00 0xa9 0x04 0x00 0x00 0xaa 0x02 0x00 0xaa 0x04 0x00 0x00 0xab 0x02 0x00 0xab +0x04 0x00 0x00 0xac 0x02 0x00 0xac 0x04 0x00 0x00 0xad 0x02 0x00 0xad 0x04 0x00 0x00 0xae +0x02 0x00 0xae 0x04 0x00 0x00 0xaf 0x02 0x00 0xaf 0x04 0x00 0x00 0xb0 0x02 0x00 0xb0 0x04 +0x00 0x00 0xb1 0x02 0x00 0xb1 0x04 0x00 0x00 0xb2 0x02 0x00 0xb2 0x04 0x00 0x00 0xb3 0x02 +0x00 0xb3 0x04 0x00 0x00 0xb4 0x02 0x00 0xb4 0x04 0x00 0x00 0xb5 0x02 0x00 0xb5 0x04 0x00 +0x00 0xb6 0x02 0x00 0xb6 0x04 0x00 0x00 0xb7 0x02 0x00 0xb7 0x04 0x00 0x00 0xb8 0x02 0x00 +0xb8 0x04 0x00 0x00 0xb9 0x02 0x00 0xb9 0x04 0x00 0x00 0xba 0x02 0x00 0xba 0x04 0x00 0x00 +0xbb 0x02 0x00 0xbb 0x04 0x00 0x00 0xbc 0x02 0x00 0xbc 0x04 0x00 0x00 0xbd 0x02 0x00 0xbd +0x04 0x00 0x00 0xbe 0x02 0x00 0xbe 0x04 0x00 0x00 0xbf 0x02 0x00 0xbf 0x04 0x00 0x00 0xc0 +0x02 0x00 0xc0 0x04 0x00 0x00 0xc1 0x02 0x00 0xc1 0x04 0x00 0x00 0xc2 0x02 0x00 0xc2 0x04 +0x00 0x00 0xc3 0x02 0x00 0xc3 0x04 0x00 0x00 0xc4 0x02 0x00 0xc4 0x04 0x00 0x00 0xc5 0x02 +0x00 0xc5 0x04 0x00 0x00 0xc6 0x02 0x00 0xc6 0x04 0x00 0x00 0xc7 0x02 0x00 0xc7 0x04 0x00 +0x00 0xc8 0x02 0x00 0xc8 0x04 0x00 0x00 0xc9 0x02 0x00 0xc9 0x04 0x00 0x00 0xca 0x02 0x00 +0xca 0x04 0x00 0x00 0xcb 0x02 0x00 0xcb 0x04 0x00 0x00 0xcc 0x02 0x00 0xcc 0x04 0x00 0x00 +0xcd 0x02 0x00 0xcd 0x04 0x00 0x00 0xce 0x02 0x00 0xce 0x04 0x00 0x00 0xcf 0x02 0x00 0xcf +0x04 0x00 0x00 0xd0 0x02 0x00 0xd0 0x04 0x00 0x00 0xd1 0x02 0x00 0xd1 0x04 0x00 0x00 0xd2 +0x02 0x00 0xd2 0x04 0x00 0x00 0xd3 0x02 0x00 0xd3 0x04 0x00 0x00 0xd4 0x02 0x00 0xd4 0x04 +0x00 0x00 0xd5 0x02 0x00 0xd5 0x04 0x00 0x00 0xd6 0x02 0x00 0xd6 0x04 0x00 0x00 0xd7 0x02 +0x00 0xd7 0x04 0x00 0x00 0xd8 0x02 0x00 0xd8 0x04 0x00 0x00 0xd9 0x02 0x00 0xd8 0x04 0x00 +0x00 0xda 0x02 0x00 0xda 0x04 0x00 0x00 0xdb 0x02 0x00 0xdb 0x04 0x00 0x00 0xdc 0x02 0x00 +0xdc 0x04 0x00 0x00 0xdd 0x02 0x00 0xdd 0x04 0x00 0x00 0xde 0x02 0x00 0xde 0x04 0x00 0x00 +0xdf 0x02 0x00 0xdf 0x04 0x00 0x00 0xe0 0x02 0x00 0xe0 0x04 0x00 0x00 0xe1 0x02 0x00 0xe1 +0x04 0x00 0x00 0xe2 0x02 0x00 0xe2 0x04 0x00 0x00 0xe3 0x02 0x00 0xe3 0x04 0x00 0x00 0xe4 +0x02 0x00 0xe4 0x04 0x00 0x00 0xe5 0x02 0x00 0xe5 0x04 0x00 0x00 0xe6 0x02 0x00 0xe6 0x04 +0x00 0x00 0xe7 0x02 0x00 0xe7 0x04 0x00 0x00 0xe8 0x02 0x00 0xe8 0x04 0x00 0x00 0xe9 0x02 +0x00 0xe9 0x04 0x00 0x00 0xea 0x02 0x00 0xea 0x04 0x00 0x00 0xeb 0x02 0x00 0xeb 0x04 0x00 +0x00 0xec 0x02 0x00 0xec 0x04 0x00 0x00 0xed 0x02 0x00 0xed 0x04 0x00 0x00 0xee 0x02 0x00 +0xee 0x04 0x00 0x00 0xef 0x02 0x00 0xef 0x04 0x00 0x00 0xf0 0x02 0x00 0xf0 0x04 0x00 0x00 +0xf1 0x02 0x00 0xf1 0x04 0x00 0x00 0xf2 0x02 0x00 0xf2 0x04 0x00 0x00 0xf3 0x02 0x00 0xf3 +0x04 0x00 0x00 0xf4 0x02 0x00 0xf4 0x04 0x00 0x00 0xf5 0x02 0x00 0xf5 0x04 0x00 0x00 0xf6 +0x02 0x00 0xf6 0x04 0x00 0x00 0xf7 0x02 0x00 0xf7 0x04 0x00 0x00 0xf8 0x02 0x00 0xf8 0x04 +0x00 0x00 0xf9 0x02 0x00 0xf9 0x04 0x00 0x00 0xfa 0x02 0x00 0xfa 0x04 0x00 0x00 0xfb 0x02 +0x00 0xfb 0x04 0x00 0x00 0xfc 0x02 0x00 0xfc 0x04 0x00 0x00 0xfd 0x02 0x00 0xfd 0x04 0x00 +0x00 0xfe 0x02 0x00 0xfe 0x04 0x00 0x00 0xff 0x02 0x00 0xff 0x04 0x00 0x00 0xa0 0x02 0x00 +0xa0 0x04 0x00 0x00 0x00 0x03 0x00 0x00 0x04 0x00 0x00 0x01 0x03 0x00 0x01 0x04 0x00 0x00 +0x02 0x03 0x00 0x02 0x04 0x00 0x00 0x03 0x03 0x00 0x03 0x04 0x00 0x00 0x04 0x03 0x00 0x04 +0x04 0x00 0x00 0x05 0x03 0x00 0x05 0x04 0x00 0x00 0x06 0x03 0x00 0x06 0x04 0x00 0x00 0x07 +0x03 0x00 0x07 0x04 0x00 0x00 0x08 0x03 0x00 0x08 0x04 0x00 0x00 0x09 0x03 0x00 0x09 0x04 +0x00 0x00 0x0a 0x03 0x00 0x0a 0x04 0x00 0x00 0x0b 0x03 0x00 0x0b 0x04 0x00 0x00 0x0c 0x03 +0x00 0x0c 0x04 0x00 0x00 0x0d 0x03 0x00 0x0d 0x04 0x00 0x00 0x0e 0x03 0x00 0x0e 0x04 0x00 +0x00 0x0f 0x03 0x00 0x0f 0x04 0x00 0x00 0x10 0x03 0x00 0x10 0x04 0x00 0x00 0x11 0x03 0x00 +0x11 0x04 0x00 0x00 0x12 0x03 0x00 0x12 0x04 0x00 0x00 0x13 0x03 0x00 0x13 0x04 0x00 0x00 +0x14 0x03 0x00 0x14 0x04 0x00 0x00 0x15 0x03 0x00 0x15 0x04 0x00 0x00 0x16 0x03 0x00 0x16 +0x04 0x00 0x00 0x17 0x03 0x00 0x17 0x04 0x00 0x00 0x18 0x03 0x00 0x18 0x04 0x00 0x00 0x19 +0x03 0x00 0x19 0x04 0x00 0x00 0x1a 0x03 0x00 0x1a 0x04 0x00 0x00 0x1b 0x03 0x00 0x1b 0x04 +0x00 0x00 0x1c 0x03 0x00 0x1c 0x04 0x00 0x00 0x1d 0x03 0x00 0x1d 0x04 0x00 0x00 0x1e 0x03 +0x00 0x1e 0x04 0x00 0x00 0x1f 0x03 0x00 0x1f 0x04 0x00 0x00 0x20 0x03 0x00 0x20 0x04 0x00 +0x00 0x21 0x03 0x00 0x21 0x04 0x00 0x00 0x22 0x03 0x00 0x22 0x04 0x00 0x00 0x23 0x03 0x00 +0x23 0x04 0x00 0x00 0x24 0x03 0x00 0x24 0x04 0x00 0x00 0x25 0x03 0x00 0x25 0x04 0x00 0x00 +0x26 0x03 0x00 0x26 0x04 0x00 0x00 0x27 0x03 0x00 0x27 0x04 0x00 0x00 0x28 0x03 0x00 0x28 +0x04 0x00 0x00 0x29 0x03 0x00 0x29 0x04 0x00 0x00 0x2a 0x03 0x00 0x2a 0x04 0x00 0x00 0x2b +0x03 0x00 0x2b 0x04 0x00 0x00 0x2c 0x03 0x00 0x2c 0x04 0x00 0x00 0x2d 0x03 0x00 0x2d 0x04 +0x00 0x00 0x2e 0x03 0x00 0x2e 0x04 0x00 0x00 0x2f 0x03 0x00 0x2f 0x04 0x00 0x00 0x30 0x03 +0x00 0x30 0x04 0x00 0x00 0x31 0x03 0x00 0x31 0x04 0x00 0x00 0x32 0x03 0x00 0x32 0x04 0x00 +0x00 0x33 0x03 0x00 0x33 0x04 0x00 0x00 0x34 0x03 0x00 0x34 0x04 0x00 0x00 0x35 0x03 0x00 +0x35 0x04 0x00 0x00 0x36 0x03 0x00 0x36 0x04 0x00 0x00 0x37 0x03 0x00 0x37 0x04 0x00 0x00 +0x38 0x03 0x00 0x38 0x04 0x00 0x00 0x39 0x03 0x00 0x39 0x04 0x00 0x00 0x3a 0x03 0x00 0x3a +0x04 0x00 0x00 0x3b 0x03 0x00 0x3b 0x04 0x00 0x00 0x3c 0x03 0x00 0x3c 0x04 0x00 0x00 0x3d +0x03 0x00 0x3d 0x04 0x00 0x00 0x3e 0x03 0x00 0x3e 0x04 0x00 0x00 0x3f 0x03 0x00 0x3f 0x04 +0x00 0x00 0x40 0x03 0x00 0x40 0x04 0x00 0x00 0x41 0x03 0x00 0x41 0x04 0x00 0x00 0x42 0x03 +0x00 0x42 0x04 0x00 0x00 0x43 0x03 0x00 0x43 0x04 0x00 0x00 0x44 0x03 0x00 0x44 0x04 0x00 +0x00 0x45 0x03 0x00 0x45 0x04 0x00 0x00 0x46 0x03 0x00 0x46 0x04 0x00 0x00 0x47 0x03 0x00 +0x47 0x04 0x00 0x00 0x48 0x03 0x00 0x48 0x04 0x00 0x00 0x49 0x03 0x00 0x49 0x04 0x00 0x00 +0x4a 0x03 0x00 0x4a 0x04 0x00 0x00 0x4b 0x03 0x00 0x4b 0x04 0x00 0x00 0x4c 0x03 0x00 0x4c +0x04 0x00 0x00 0x4d 0x03 0x00 0x4d 0x04 0x00 0x00 0x4e 0x03 0x00 0x4e 0x04 0x00 0x00 0x4f +0x03 0x00 0x4f 0x04 0x00 0x00 0x50 0x03 0x00 0x50 0x04 0x00 0x00 0x51 0x03 0x00 0x51 0x04 +0x00 0x00 0x52 0x03 0x00 0x52 0x04 0x00 0x00 0x53 0x03 0x00 0x53 0x04 0x00 0x00 0x54 0x03 +0x00 0x54 0x04 0x00 0x00 0x55 0x03 0x00 0x55 0x04 0x00 0x00 0x56 0x03 0x00 0x56 0x04 0x00 +0x00 0x57 0x03 0x00 0x57 0x04 0x00 0x00 0x58 0x03 0x00 0x58 0x04 0x00 0x00 0x59 0x03 0x00 +0x59 0x04 0x00 0x00 0x5a 0x03 0x00 0x5a 0x04 0x00 0x00 0x5b 0x03 0x00 0x5b 0x04 0x00 0x00 +0x5c 0x03 0x00 0x5c 0x04 0x00 0x00 0x5d 0x03 0x00 0x5d 0x04 0x00 0x00 0x5e 0x03 0x00 0x5e +0x04 0x00 0x00 0x5f 0x03 0x00 0x5f 0x04 0x00 0x00 0x60 0x03 0x00 0x60 0x04 0x00 0x00 0x61 +0x03 0x00 0x61 0x04 0x00 0x00 0x62 0x03 0x00 0x62 0x04 0x00 0x00 0x63 0x03 0x00 0x63 0x04 +0x00 0x00 0x64 0x03 0x00 0x64 0x04 0x00 0x00 0x65 0x03 0x00 0x65 0x04 0x00 0x00 0x66 0x03 +0x00 0x66 0x04 0x00 0x00 0x67 0x03 0x00 0x67 0x04 0x00 0x00 0x68 0x03 0x00 0x68 0x04 0x00 +0x00 0x69 0x03 0x00 0x69 0x04 0x00 0x00 0x6a 0x03 0x00 0x6a 0x04 0x00 0x00 0x6b 0x03 0x00 +0x6b 0x04 0x00 0x00 0x6c 0x03 0x00 0x6c 0x04 0x00 0x00 0x6d 0x03 0x00 0x6d 0x04 0x00 0x00 +0x6e 0x03 0x00 0x6e 0x04 0x00 0x00 0x6f 0x03 0x00 0x6f 0x04 0x00 0x00 0x70 0x03 0x00 0x70 +0x04 0x00 0x00 0x71 0x03 0x00 0x71 0x04 0x00 0x00 0x72 0x03 0x00 0x72 0x04 0x00 0x00 0x73 +0x03 0x00 0x73 0x04 0x00 0x00 0x74 0x03 0x00 0x74 0x04 0x00 0x00 0x75 0x03 0x00 0x75 0x04 +0x00 0x00 0x76 0x03 0x00 0x76 0x04 0x00 0x00 0x77 0x03 0x00 0x77 0x04 0x00 0x00 0x78 0x03 +0x00 0x78 0x04 0x00 0x00 0x79 0x03 0x00 0x79 0x04 0x00 0x00 0x7a 0x03 0x00 0x7a 0x04 0x00 +0x00 0x7b 0x03 0x00 0x7b 0x04 0x00 0x00 0x7c 0x03 0x00 0x7c 0x04 0x00 0x00 0x7d 0x03 0x00 +0x7d 0x04 0x00 0x00 0x7e 0x03 0x00 0x7e 0x04 0x00 0x00 0x7f 0x03 0x00 0x7f 0x04 0x00 0x00 +0x80 0x03 0x00 0x80 0x04 0x00 0x00 0x81 0x03 0x00 0x81 0x04 0x00 0x00 0x82 0x03 0x00 0x82 +0x04 0x00 0x00 0x83 0x03 0x00 0x83 0x04 0x00 0x00 0x84 0x03 0x00 0x84 0x04 0x00 0x00 0x85 +0x03 0x00 0x85 0x04 0x00 0x00 0x86 0x03 0x00 0x86 0x04 0x00 0x00 0x87 0x03 0x00 0x87 0x04 +0x00 0x00 0x88 0x03 0x00 0x88 0x04 0x00 0x00 0x89 0x03 0x00 0x89 0x04 0x00 0x00 0x8a 0x03 +0x00 0x8a 0x04 0x00 0x00 0x8b 0x03 0x00 0x8b 0x04 0x00 0x00 0x8c 0x03 0x00 0x8c 0x04 0x00 +0x00 0x8d 0x03 0x00 0x8d 0x04 0x00 0x00 0x8e 0x03 0x00 0x8e 0x04 0x00 0x00 0x8f 0x03 0x00 +0x8f 0x04 0x00 0x00 0x90 0x03 0x00 0x90 0x04 0x00 0x00 0x91 0x03 0x00 0x91 0x04 0x00 0x00 +0x92 0x03 0x00 0x92 0x04 0x00 0x00 0x93 0x03 0x00 0x93 0x04 0x00 0x00 0x94 0x03 0x00 0x94 +0x04 0x00 0x00 0x95 0x03 0x00 0x95 0x04 0x00 0x00 0x96 0x03 0x00 0x96 0x04 0x00 0x00 0x97 +0x03 0x00 0x97 0x04 0x00 0x00 0x98 0x03 0x00 0x98 0x04 0x00 0x00 0x99 0x03 0x00 0x99 0x04 +0x00 0x00 0x9a 0x03 0x00 0x9a 0x04 0x00 0x00 0x9b 0x03 0x00 0x9b 0x04 0x00 0x00 0x9c 0x03 +0x00 0x9c 0x04 0x00 0x00 0x9d 0x03 0x00 0x9d 0x04 0x00 0x00 0x9e 0x03 0x00 0x9e 0x04 0x00 +0x00 0x9f 0x03 0x00 0x9f 0x04 0x00 0x00 0xa0 0x03 0x00 0xa0 0x04 0x00 0x00 0xa1 0x03 0x00 +0xa1 0x04 0x00 0x00 0xa2 0x03 0x00 0xa2 0x04 0x00 0x00 0xa3 0x03 0x00 0xa3 0x04 0x00 0x00 +0xa4 0x03 0x00 0xa4 0x04 0x00 0x00 0xa5 0x03 0x00 0xa5 0x04 0x00 0x00 0xa6 0x03 0x00 0xa6 +0x04 0x00 0x00 0xa7 0x03 0x00 0xa7 0x04 0x00 0x00 0xa8 0x03 0x00 0xa8 0x04 0x00 0x00 0xa9 +0x03 0x00 0xa9 0x04 0x00 0x00 0xaa 0x03 0x00 0xaa 0x04 0x00 0x00 0xab 0x03 0x00 0xab 0x04 +0x00 0x00 0xac 0x03 0x00 0xac 0x04 0x00 0x00 0xad 0x03 0x00 0xad 0x04 0x00 0x00 0xae 0x03 +0x00 0xae 0x04 0x00 0x00 0xaf 0x03 0x00 0xaf 0x04 0x00 0x00 0xb0 0x03 0x00 0xb0 0x04 0x00 +0x00 0xb1 0x03 0x00 0xb1 0x04 0x00 0x00 0xb2 0x03 0x00 0xb2 0x04 0x00 0x00 0xb3 0x03 0x00 +0xb3 0x04 0x00 0x00 0xb4 0x03 0x00 0xb4 0x04 0x00 0x00 0xb5 0x03 0x00 0xb5 0x04 0x00 0x00 +0xb6 0x03 0x00 0xb6 0x04 0x00 0x00 0xb7 0x03 0x00 0xb7 0x04 0x00 0x00 0xb8 0x03 0x00 0xb8 +0x04 0x00 0x00 0xb9 0x03 0x00 0xb9 0x04 0x00 0x00 0xba 0x03 0x00 0xba 0x04 0x00 0x00 0xbb +0x03 0x00 0xbb 0x04 0x00 0x00 0xbc 0x03 0x00 0xbc 0x04 0x00 0x00 0xbd 0x03 0x00 0xbd 0x04 +0x00 0x00 0xbe 0x03 0x00 0xbe 0x04 0x00 0x00 0xbf 0x03 0x00 0xbf 0x04 0x00 0x00 0xc0 0x03 +0x00 0xc0 0x04 0x00 0x00 0xc1 0x03 0x00 0xc1 0x04 0x00 0x00 0xc2 0x03 0x00 0xc2 0x04 0x00 +0x00 0xc3 0x03 0x00 0xc3 0x04 0x00 0x00 0xc4 0x03 0x00 0xc4 0x04 0x00 0x00 0xc5 0x03 0x00 +0xc5 0x04 0x00 0x00 0xc6 0x03 0x00 0xc6 0x04 0x00 0x00 0xc7 0x03 0x00 0xc7 0x04 0x00 0x00 +0xc8 0x03 0x00 0xc8 0x04 0x00 0x00 0xc9 0x03 0x00 0xc9 0x04 0x00 0x00 0xca 0x03 0x00 0xca +0x04 0x00 0x00 0xcb 0x03 0x00 0xcb 0x04 0x00 0x00 0xcc 0x03 0x00 0xcc 0x04 0x00 0x00 0xcd +0x03 0x00 0xcd 0x04 0x00 0x00 0xce 0x03 0x00 0xce 0x04 0x00 0x00 0xcf 0x03 0x00 0xcf 0x04 +0x00 0x00 0xd0 0x03 0x00 0xd0 0x04 0x00 0x00 0xd1 0x03 0x00 0xd1 0x04 0x00 0x00 0xd2 0x03 +0x00 0xd2 0x04 0x00 0x00 0xd3 0x03 0x00 0xd3 0x04 0x00 0x00 0xd4 0x03 0x00 0xd4 0x04 0x00 +0x00 0xd5 0x03 0x00 0xd5 0x04 0x00 0x00 0xd6 0x03 0x00 0xd6 0x04 0x00 0x00 0xd7 0x03 0x00 +0xd7 0x04 0x00 0x00 0xd8 0x03 0x00 0xd8 0x04 0x00 0x00 0xd9 0x03 0x00 0xd8 0x04 0x00 0x00 +0xda 0x03 0x00 0xda 0x04 0x00 0x00 0xdb 0x03 0x00 0xdb 0x04 0x00 0x00 0xdc 0x03 0x00 0xdc +0x04 0x00 0x00 0xdd 0x03 0x00 0xdd 0x04 0x00 0x00 0xde 0x03 0x00 0xde 0x04 0x00 0x00 0xdf +0x03 0x00 0xdf 0x04 0x00 0x00 0xe0 0x03 0x00 0xe0 0x04 0x00 0x00 0xe1 0x03 0x00 0xe1 0x04 +0x00 0x00 0xe2 0x03 0x00 0xe2 0x04 0x00 0x00 0xe3 0x03 0x00 0xe3 0x04 0x00 0x00 0xe4 0x03 +0x00 0xe4 0x04 0x00 0x00 0xe5 0x03 0x00 0xe5 0x04 0x00 0x00 0xe6 0x03 0x00 0xe6 0x04 0x00 +0x00 0xe7 0x03 0x00 0xe7 0x04 0x00 0x00 0xe8 0x03 0x00 0xe8 0x04 0x00 0x00 0xe9 0x03 0x00 +0xe9 0x04 0x00 0x00 0xea 0x03 0x00 0xea 0x04 0x00 0x00 0xeb 0x03 0x00 0xeb 0x04 0x00 0x00 +0xec 0x03 0x00 0xec 0x04 0x00 0x00 0xed 0x03 0x00 0xed 0x04 0x00 0x00 0xee 0x03 0x00 0xee +0x04 0x00 0x00 0xef 0x03 0x00 0xef 0x04 0x00 0x00 0xf0 0x03 0x00 0xf0 0x04 0x00 0x00 0xf1 +0x03 0x00 0xf1 0x04 0x00 0x00 0xf2 0x03 0x00 0xf2 0x04 0x00 0x00 0xf3 0x03 0x00 0xf3 0x04 +0x00 0x00 0xf4 0x03 0x00 0xf4 0x04 0x00 0x00 0xf5 0x03 0x00 0xf5 0x04 0x00 0x00 0xf6 0x03 +0x00 0xf6 0x04 0x00 0x00 0xf7 0x03 0x00 0xf7 0x04 0x00 0x00 0xf8 0x03 0x00 0xf8 0x04 0x00 +0x00 0xf9 0x03 0x00 0xf9 0x04 0x00 0x00 0xfa 0x03 0x00 0xfa 0x04 0x00 0x00 0xfb 0x03 0x00 +0xfb 0x04 0x00 0x00 0xfc 0x03 0x00 0xfc 0x04 0x00 0x00 0xfd 0x03 0x00 0xfd 0x04 0x00 0x00 +0xfe 0x03 0x00 0xfe 0x04 0x00 0x00 0xff 0x03 0x00 0xff 0x04 0x00 0x00 0xa0 0x03 0x00 0xa0 +0x04 0x00 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 0x01 0x04 0x00 0x01 0x04 0x00 0x00 0x02 +0x04 0x00 0x02 0x04 0x00 0x00 0x03 0x04 0x00 0x03 0x04 0x00 0x00 0x04 0x04 0x00 0x04 0x04 +0x00 0x00 0x05 0x04 0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00 0x06 0x04 0x00 0x00 0x07 0x04 +0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00 0x08 0x04 0x00 0x00 0x09 0x04 0x00 0x09 0x04 0x00 +0x00 0x0a 0x04 0x00 0x0a 0x04 0x00 0x00 0x0b 0x04 0x00 0x0b 0x04 0x00 0x00 0x0c 0x04 0x00 +0x0c 0x04 0x00 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x00 0x0e 0x04 0x00 0x0e 0x04 0x00 0x00 +0x0f 0x04 0x00 0x0f 0x04 0x00 0x00 0x10 0x04 0x00 0x10 0x04 0x00 0x00 0x11 0x04 0x00 0x11 +0x04 0x00 0x00 0x12 0x04 0x00 0x12 0x04 0x00 0x00 0x13 0x04 0x00 0x13 0x04 0x00 0x00 0x14 +0x04 0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x15 0x04 0x00 0x00 0x16 0x04 0x00 0x16 0x04 +0x00 0x00 0x17 0x04 0x00 0x17 0x04 0x00 0x00 0x18 0x04 0x00 0x18 0x04 0x00 0x00 0x19 0x04 +0x00 0x19 0x04 0x00 0x00 0x1a 0x04 0x00 0x1a 0x04 0x00 0x00 0x1b 0x04 0x00 0x1b 0x04 0x00 +0x00 0x1c 0x04 0x00 0x1c 0x04 0x00 0x00 0x1d 0x04 0x00 0x1d 0x04 0x00 0x00 0x1e 0x04 0x00 +0x1e 0x04 0x00 0x00 0x1f 0x04 0x00 0x1f 0x04 0x00 0x00 0x20 0x04 0x00 0x20 0x04 0x00 0x00 +0x21 0x04 0x00 0x21 0x04 0x00 0x00 0x22 0x04 0x00 0x22 0x04 0x00 0x00 0x23 0x04 0x00 0x23 +0x04 0x00 0x00 0x24 0x04 0x00 0x24 0x04 0x00 0x00 0x25 0x04 0x00 0x25 0x04 0x00 0x00 0x26 +0x04 0x00 0x26 0x04 0x00 0x00 0x27 0x04 0x00 0x27 0x04 0x00 0x00 0x28 0x04 0x00 0x28 0x04 +0x00 0x00 0x29 0x04 0x00 0x29 0x04 0x00 0x00 0x2a 0x04 0x00 0x2a 0x04 0x00 0x00 0x2b 0x04 +0x00 0x2b 0x04 0x00 0x00 0x2c 0x04 0x00 0x2c 0x04 0x00 0x00 0x2d 0x04 0x00 0x2d 0x04 0x00 +0x00 0x2e 0x04 0x00 0x2e 0x04 0x00 0x00 0x2f 0x04 0x00 0x2f 0x04 0x00 0x00 0x30 0x04 0x00 +0x30 0x04 0x00 0x00 0x31 0x04 0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x32 0x04 0x00 0x00 +0x33 0x04 0x00 0x33 0x04 0x00 0x00 0x34 0x04 0x00 0x34 0x04 0x00 0x00 0x35 0x04 0x00 0x35 +0x04 0x00 0x00 0x36 0x04 0x00 0x36 0x04 0x00 0x00 0x37 0x04 0x00 0x37 0x04 0x00 0x00 0x38 +0x04 0x00 0x38 0x04 0x00 0x00 0x39 0x04 0x00 0x39 0x04 0x00 0x00 0x3a 0x04 0x00 0x3a 0x04 +0x00 0x00 0x3b 0x04 0x00 0x3b 0x04 0x00 0x00 0x3c 0x04 0x00 0x3c 0x04 0x00 0x00 0x3d 0x04 +0x00 0x3d 0x04 0x00 0x00 0x3e 0x04 0x00 0x3e 0x04 0x00 0x00 0x3f 0x04 0x00 0x3f 0x04 0x00 +0x00 0x40 0x04 0x00 0x40 0x04 0x00 0x00 0x41 0x04 0x00 0x41 0x04 0x00 0x00 0x42 0x04 0x00 +0x42 0x04 0x00 0x00 0x43 0x04 0x00 0x43 0x04 0x00 0x00 0x44 0x04 0x00 0x44 0x04 0x00 0x00 +0x45 0x04 0x00 0x45 0x04 0x00 0x00 0x46 0x04 0x00 0x46 0x04 0x00 0x00 0x47 0x04 0x00 0x47 +0x04 0x00 0x00 0x48 0x04 0x00 0x48 0x04 0x00 0x00 0x49 0x04 0x00 0x49 0x04 0x00 0x00 0x4a +0x04 0x00 0x4a 0x04 0x00 0x00 0x4b 0x04 0x00 0x4b 0x04 0x00 0x00 0x4c 0x04 0x00 0x4c 0x04 +0x00 0x00 0x4d 0x04 0x00 0x4d 0x04 0x00 0x00 0x4e 0x04 0x00 0x4e 0x04 0x00 0x00 0x4f 0x04 +0x00 0x4f 0x04 0x00 0x00 0x50 0x04 0x00 0x50 0x04 0x00 0x00 0x51 0x04 0x00 0x51 0x04 0x00 +0x00 0x52 0x04 0x00 0x52 0x04 0x00 0x00 0x53 0x04 0x00 0x53 0x04 0x00 0x00 0x54 0x04 0x00 +0x54 0x04 0x00 0x00 0x55 0x04 0x00 0x55 0x04 0x00 0x00 0x56 0x04 0x00 0x56 0x04 0x00 0x00 +0x57 0x04 0x00 0x57 0x04 0x00 0x00 0x58 0x04 0x00 0x58 0x04 0x00 0x00 0x59 0x04 0x00 0x59 +0x04 0x00 0x00 0x5a 0x04 0x00 0x5a 0x04 0x00 0x00 0x5b 0x04 0x00 0x5b 0x04 0x00 0x00 0x5c +0x04 0x00 0x5c 0x04 0x00 0x00 0x5d 0x04 0x00 0x5d 0x04 0x00 0x00 0x5e 0x04 0x00 0x5e 0x04 +0x00 0x00 0x5f 0x04 0x00 0x5f 0x04 0x00 0x00 0x60 0x04 0x00 0x60 0x04 0x00 0x00 0x61 0x04 +0x00 0x61 0x04 0x00 0x00 0x62 0x04 0x00 0x62 0x04 0x00 0x00 0x63 0x04 0x00 0x63 0x04 0x00 +0x00 0x64 0x04 0x00 0x64 0x04 0x00 0x00 0x65 0x04 0x00 0x65 0x04 0x00 0x00 0x66 0x04 0x00 +0x66 0x04 0x00 0x00 0x67 0x04 0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x68 0x04 0x00 0x00 +0x69 0x04 0x00 0x69 0x04 0x00 0x00 0x6a 0x04 0x00 0x6a 0x04 0x00 0x00 0x6b 0x04 0x00 0x6b +0x04 0x00 0x00 0x6c 0x04 0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x6d 0x04 0x00 0x00 0x6e +0x04 0x00 0x6e 0x04 0x00 0x00 0x6f 0x04 0x00 0x6f 0x04 0x00 0x00 0x70 0x04 0x00 0x70 0x04 +0x00 0x00 0x71 0x04 0x00 0x71 0x04 0x00 0x00 0x72 0x04 0x00 0x72 0x04 0x00 0x00 0x73 0x04 +0x00 0x73 0x04 0x00 0x00 0x74 0x04 0x00 0x74 0x04 0x00 0x00 0x75 0x04 0x00 0x75 0x04 0x00 +0x00 0x76 0x04 0x00 0x76 0x04 0x00 0x00 0x77 0x04 0x00 0x77 0x04 0x00 0x00 0x78 0x04 0x00 +0x78 0x04 0x00 0x00 0x79 0x04 0x00 0x79 0x04 0x00 0x00 0x7a 0x04 0x00 0x7a 0x04 0x00 0x00 +0x7b 0x04 0x00 0x7b 0x04 0x00 0x00 0x7c 0x04 0x00 0x7c 0x04 0x00 0x00 0x7d 0x04 0x00 0x7d +0x04 0x00 0x00 0x7e 0x04 0x00 0x7e 0x04 0x00 0x00 0x7f 0x04 0x00 0x7f 0x04 0x00 0x00 0x80 +0x04 0x00 0x80 0x04 0x00 0x00 0x81 0x04 0x00 0x81 0x04 0x00 0x00 0x82 0x04 0x00 0x82 0x04 +0x00 0x00 0x83 0x04 0x00 0x83 0x04 0x00 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x00 0x85 0x04 +0x00 0x85 0x04 0x00 0x00 0x86 0x04 0x00 0x86 0x04 0x00 0x00 0x87 0x04 0x00 0x87 0x04 0x00 +0x00 0x88 0x04 0x00 0x88 0x04 0x00 0x00 0x89 0x04 0x00 0x89 0x04 0x00 0x00 0x8a 0x04 0x00 +0x8a 0x04 0x00 0x00 0x8b 0x04 0x00 0x8b 0x04 0x00 0x00 0x8c 0x04 0x00 0x8c 0x04 0x00 0x00 +0x8d 0x04 0x00 0x8d 0x04 0x00 0x00 0x8e 0x04 0x00 0x8e 0x04 0x00 0x00 0x8f 0x04 0x00 0x8f +0x04 0x00 0x00 0x90 0x04 0x00 0x90 0x04 0x00 0x00 0x91 0x04 0x00 0x91 0x04 0x00 0x00 0x92 +0x04 0x00 0x92 0x04 0x00 0x00 0x93 0x04 0x00 0x93 0x04 0x00 0x00 0x94 0x04 0x00 0x94 0x04 +0x00 0x00 0x95 0x04 0x00 0x95 0x04 0x00 0x00 0x96 0x04 0x00 0x96 0x04 0x00 0x00 0x97 0x04 +0x00 0x97 0x04 0x00 0x00 0x98 0x04 0x00 0x98 0x04 0x00 0x00 0x99 0x04 0x00 0x99 0x04 0x00 +0x00 0x9a 0x04 0x00 0x9a 0x04 0x00 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x00 0x9c 0x04 0x00 +0x9c 0x04 0x00 0x00 0x9d 0x04 0x00 0x9d 0x04 0x00 0x00 0x9e 0x04 0x00 0x9e 0x04 0x00 0x00 +0x9f 0x04 0x00 0x9f 0x04 0x00 0x00 0xa0 0x04 0x00 0xa0 0x04 0x00 0x00 0xa1 0x04 0x00 0xa1 +0x04 0x00 0x00 0xa2 0x04 0x00 0xa2 0x04 0x00 0x00 0xa3 0x04 0x00 0xa3 0x04 0x00 0x00 0xa4 +0x04 0x00 0xa4 0x04 0x00 0x00 0xa5 0x04 0x00 0xa5 0x04 0x00 0x00 0xa6 0x04 0x00 0xa6 0x04 +0x00 0x00 0xa7 0x04 0x00 0xa7 0x04 0x00 0x00 0xa8 0x04 0x00 0xa8 0x04 0x00 0x00 0xa9 0x04 +0x00 0xa9 0x04 0x00 0x00 0xaa 0x04 0x00 0xaa 0x04 0x00 0x00 0xab 0x04 0x00 0xab 0x04 0x00 +0x00 0xac 0x04 0x00 0xac 0x04 0x00 0x00 0xad 0x04 0x00 0xad 0x04 0x00 0x00 0xae 0x04 0x00 +0xae 0x04 0x00 0x00 0xaf 0x04 0x00 0xaf 0x04 0x00 0x00 0xb0 0x04 0x00 0xb0 0x04 0x00 0x00 +0xb1 0x04 0x00 0xb1 0x04 0x00 0x00 0xb2 0x04 0x00 0xb2 0x04 0x00 0x00 0xb3 0x04 0x00 0xb3 +0x04 0x00 0x00 0xb4 0x04 0x00 0xb4 0x04 0x00 0x00 0xb5 0x04 0x00 0xb5 0x04 0x00 0x00 0xb6 +0x04 0x00 0xb6 0x04 0x00 0x00 0xb7 0x04 0x00 0xb7 0x04 0x00 0x00 0xb8 0x04 0x00 0xb8 0x04 +0x00 0x00 0xb9 0x04 0x00 0xb9 0x04 0x00 0x00 0xba 0x04 0x00 0xba 0x04 0x00 0x00 0xbb 0x04 +0x00 0xbb 0x04 0x00 0x00 0xbc 0x04 0x00 0xbc 0x04 0x00 0x00 0xbd 0x04 0x00 0xbd 0x04 0x00 +0x00 0xbe 0x04 0x00 0xbe 0x04 0x00 0x00 0xbf 0x04 0x00 0xbf 0x04 0x00 0x00 0xc0 0x04 0x00 +0xc0 0x04 0x00 0x00 0xc1 0x04 0x00 0xc1 0x04 0x00 0x00 0xc2 0x04 0x00 0xc2 0x04 0x00 0x00 +0xc3 0x04 0x00 0xc3 0x04 0x00 0x00 0xc4 0x04 0x00 0xc4 0x04 0x00 0x00 0xc5 0x04 0x00 0xc5 +0x04 0x00 0x00 0xc6 0x04 0x00 0xc6 0x04 0x00 0x00 0xc7 0x04 0x00 0xc7 0x04 0x00 0x00 0xc8 +0x04 0x00 0xc8 0x04 0x00 0x00 0xc9 0x04 0x00 0xc9 0x04 0x00 0x00 0xca 0x04 0x00 0xca 0x04 +0x00 0x00 0xcb 0x04 0x00 0xcb 0x04 0x00 0x00 0xcc 0x04 0x00 0xcc 0x04 0x00 0x00 0xcd 0x04 +0x00 0xcd 0x04 0x00 0x00 0xce 0x04 0x00 0xce 0x04 0x00 0x00 0xcf 0x04 0x00 0xcf 0x04 0x00 +0x00 0xd0 0x04 0x00 0xd0 0x04 0x00 0x00 0xd1 0x04 0x00 0xd1 0x04 0x00 0x00 0xd2 0x04 0x00 +0xd2 0x04 0x00 0x00 0xd3 0x04 0x00 0xd3 0x04 0x00 0x00 0xd4 0x04 0x00 0xd4 0x04 0x00 0x00 +0xd5 0x04 0x00 0xd5 0x04 0x00 0x00 0xd6 0x04 0x00 0xd6 0x04 0x00 0x00 0xd7 0x04 0x00 0xd7 +0x04 0x00 0x00 0xd8 0x04 0x00 0xd8 0x04 0x00 0x00 0xd9 0x04 0x00 0xd8 0x04 0x00 0x00 0xda +0x04 0x00 0xda 0x04 0x00 0x00 0xdb 0x04 0x00 0xdb 0x04 0x00 0x00 0xdc 0x04 0x00 0xdc 0x04 +0x00 0x00 0xdd 0x04 0x00 0xdd 0x04 0x00 0x00 0xde 0x04 0x00 0xde 0x04 0x00 0x00 0xdf 0x04 +0x00 0xdf 0x04 0x00 0x00 0xe0 0x04 0x00 0xe0 0x04 0x00 0x00 0xe1 0x04 0x00 0xe1 0x04 0x00 +0x00 0xe2 0x04 0x00 0xe2 0x04 0x00 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0x00 0xe4 0x04 0x00 +0xe4 0x04 0x00 0x00 0xe5 0x04 0x00 0xe5 0x04 0x00 0x00 0xe6 0x04 0x00 0xe6 0x04 0x00 0x00 +0xe7 0x04 0x00 0xe7 0x04 0x00 0x00 0xe8 0x04 0x00 0xe8 0x04 0x00 0x00 0xe9 0x04 0x00 0xe9 +0x04 0x00 0x00 0xea 0x04 0x00 0xea 0x04 0x00 0x00 0xeb 0x04 0x00 0xeb 0x04 0x00 0x00 0xec +0x04 0x00 0xec 0x04 0x00 0x00 0xed 0x04 0x00 0xed 0x04 0x00 0x00 0xee 0x04 0x00 0xee 0x04 +0x00 0x00 0xef 0x04 0x00 0xef 0x04 0x00 0x00 0xf0 0x04 0x00 0xf0 0x04 0x00 0x00 0xf1 0x04 +0x00 0xf1 0x04 0x00 0x00 0xf2 0x04 0x00 0xf2 0x04 0x00 0x00 0xf3 0x04 0x00 0xf3 0x04 0x00 +0x00 0xf4 0x04 0x00 0xf4 0x04 0x00 0x00 0xf5 0x04 0x00 0xf5 0x04 0x00 0x00 0xf6 0x04 0x00 +0xf6 0x04 0x00 0x00 0xf7 0x04 0x00 0xf7 0x04 0x00 0x00 0xf8 0x04 0x00 0xf8 0x04 0x00 0x00 +0xf9 0x04 0x00 0xf9 0x04 0x00 0x00 0xfa 0x04 0x00 0xfa 0x04 0x00 0x00 0xfb 0x04 0x00 0xfb +0x04 0x00 0x00 0xfc 0x04 0x00 0xfc 0x04 0x00 0x00 0xfd 0x04 0x00 0xfd 0x04 0x00 0x00 0xfe +0x04 0x00 0xfe 0x04 0x00 0x00 0xff 0x04 0x00 0xff 0x04 0x00 0x00 0xa0 0x04 0x00 0xa0 0x04 +0x00 0x00 0x00 0x05 0x00 0x00 0x04 0x00 0x00 0x01 0x05 0x00 0x01 0x04 0x00 0x00 0x02 0x05 +0x00 0x02 0x04 0x00 0x00 0x03 0x05 0x00 0x03 0x04 0x00 0x00 0x04 0x05 0x00 0x04 0x04 0x00 +0x00 0x05 0x05 0x00 0x05 0x04 0x00 0x00 0x06 0x05 0x00 0x06 0x04 0x00 0x00 0x07 0x05 0x00 +0x07 0x04 0x00 0x00 0x08 0x05 0x00 0x08 0x04 0x00 0x00 0x09 0x05 0x00 0x09 0x04 0x00 0x00 +0x0a 0x05 0x00 0x0a 0x04 0x00 0x00 0x0b 0x05 0x00 0x0b 0x04 0x00 0x00 0x0c 0x05 0x00 0x0c +0x04 0x00 0x00 0x0d 0x05 0x00 0x0d 0x04 0x00 0x00 0x0e 0x05 0x00 0x0e 0x04 0x00 0x00 0x0f +0x05 0x00 0x0f 0x04 0x00 0x00 0x10 0x05 0x00 0x10 0x04 0x00 0x00 0x11 0x05 0x00 0x11 0x04 +0x00 0x00 0x12 0x05 0x00 0x12 0x04 0x00 0x00 0x13 0x05 0x00 0x13 0x04 0x00 0x00 0x14 0x05 +0x00 0x14 0x04 0x00 0x00 0x15 0x05 0x00 0x15 0x04 0x00 0x00 0x16 0x05 0x00 0x16 0x04 0x00 +0x00 0x17 0x05 0x00 0x17 0x04 0x00 0x00 0x18 0x05 0x00 0x18 0x04 0x00 0x00 0x19 0x05 0x00 +0x19 0x04 0x00 0x00 0x1a 0x05 0x00 0x1a 0x04 0x00 0x00 0x1b 0x05 0x00 0x1b 0x04 0x00 0x00 +0x1c 0x05 0x00 0x1c 0x04 0x00 0x00 0x1d 0x05 0x00 0x1d 0x04 0x00 0x00 0x1e 0x05 0x00 0x1e +0x04 0x00 0x00 0x1f 0x05 0x00 0x1f 0x04 0x00 0x00 0x20 0x05 0x00 0x20 0x04 0x00 0x00 0x21 +0x05 0x00 0x21 0x04 0x00 0x00 0x22 0x05 0x00 0x22 0x04 0x00 0x00 0x23 0x05 0x00 0x23 0x04 +0x00 0x00 0x24 0x05 0x00 0x24 0x04 0x00 0x00 0x25 0x05 0x00 0x25 0x04 0x00 0x00 0x26 0x05 +0x00 0x26 0x04 0x00 0x00 0x27 0x05 0x00 0x27 0x04 0x00 0x00 0x28 0x05 0x00 0x28 0x04 0x00 +0x00 0x29 0x05 0x00 0x29 0x04 0x00 0x00 0x2a 0x05 0x00 0x2a 0x04 0x00 0x00 0x2b 0x05 0x00 +0x2b 0x04 0x00 0x00 0x2c 0x05 0x00 0x2c 0x04 0x00 0x00 0x2d 0x05 0x00 0x2d 0x04 0x00 0x00 +0x2e 0x05 0x00 0x2e 0x04 0x00 0x00 0x2f 0x05 0x00 0x2f 0x04 0x00 0x00 0x30 0x05 0x00 0x30 +0x04 0x00 0x00 0x31 0x05 0x00 0x31 0x04 0x00 0x00 0x32 0x05 0x00 0x32 0x04 0x00 0x00 0x33 +0x05 0x00 0x33 0x04 0x00 0x00 0x34 0x05 0x00 0x34 0x04 0x00 0x00 0x35 0x05 0x00 0x35 0x04 +0x00 0x00 0x36 0x05 0x00 0x36 0x04 0x00 0x00 0x37 0x05 0x00 0x37 0x04 0x00 0x00 0x38 0x05 +0x00 0x38 0x04 0x00 0x00 0x39 0x05 0x00 0x39 0x04 0x00 0x00 0x3a 0x05 0x00 0x3a 0x04 0x00 +0x00 0x3b 0x05 0x00 0x3b 0x04 0x00 0x00 0x3c 0x05 0x00 0x3c 0x04 0x00 0x00 0x3d 0x05 0x00 +0x3d 0x04 0x00 0x00 0x3e 0x05 0x00 0x3e 0x04 0x00 0x00 0x3f 0x05 0x00 0x3f 0x04 0x00 0x00 +0x40 0x05 0x00 0x40 0x04 0x00 0x00 0x41 0x05 0x00 0x41 0x04 0x00 0x00 0x42 0x05 0x00 0x42 +0x04 0x00 0x00 0x43 0x05 0x00 0x43 0x04 0x00 0x00 0x44 0x05 0x00 0x44 0x04 0x00 0x00 0x45 +0x05 0x00 0x45 0x04 0x00 0x00 0x46 0x05 0x00 0x46 0x04 0x00 0x00 0x47 0x05 0x00 0x47 0x04 +0x00 0x00 0x48 0x05 0x00 0x48 0x04 0x00 0x00 0x49 0x05 0x00 0x49 0x04 0x00 0x00 0x4a 0x05 +0x00 0x4a 0x04 0x00 0x00 0x4b 0x05 0x00 0x4b 0x04 0x00 0x00 0x4c 0x05 0x00 0x4c 0x04 0x00 +0x00 0x4d 0x05 0x00 0x4d 0x04 0x00 0x00 0x4e 0x05 0x00 0x4e 0x04 0x00 0x00 0x4f 0x05 0x00 +0x4f 0x04 0x00 0x00 0x50 0x05 0x00 0x50 0x04 0x00 0x00 0x51 0x05 0x00 0x51 0x04 0x00 0x00 +0x52 0x05 0x00 0x52 0x04 0x00 0x00 0x53 0x05 0x00 0x53 0x04 0x00 0x00 0x54 0x05 0x00 0x54 +0x04 0x00 0x00 0x55 0x05 0x00 0x55 0x04 0x00 0x00 0x56 0x05 0x00 0x56 0x04 0x00 0x00 0x57 +0x05 0x00 0x57 0x04 0x00 0x00 0x58 0x05 0x00 0x58 0x04 0x00 0x00 0x59 0x05 0x00 0x59 0x04 +0x00 0x00 0x5a 0x05 0x00 0x5a 0x04 0x00 0x00 0x5b 0x05 0x00 0x5b 0x04 0x00 0x00 0x5c 0x05 +0x00 0x5c 0x04 0x00 0x00 0x5d 0x05 0x00 0x5d 0x04 0x00 0x00 0x5e 0x05 0x00 0x5e 0x04 0x00 +0x00 0x5f 0x05 0x00 0x5f 0x04 0x00 0x00 0x60 0x05 0x00 0x60 0x04 0x00 0x00 0x61 0x05 0x00 +0x61 0x04 0x00 0x00 0x62 0x05 0x00 0x62 0x04 0x00 0x00 0x63 0x05 0x00 0x63 0x04 0x00 0x00 +0x64 0x05 0x00 0x64 0x04 0x00 0x00 0x65 0x05 0x00 0x65 0x04 0x00 0x00 0x66 0x05 0x00 0x66 +0x04 0x00 0x00 0x67 0x05 0x00 0x67 0x04 0x00 0x00 0x68 0x05 0x00 0x68 0x04 0x00 0x00 0x69 +0x05 0x00 0x69 0x04 0x00 0x00 0x6a 0x05 0x00 0x6a 0x04 0x00 0x00 0x6b 0x05 0x00 0x6b 0x04 +0x00 0x00 0x6c 0x05 0x00 0x6c 0x04 0x00 0x00 0x6d 0x05 0x00 0x6d 0x04 0x00 0x00 0x6e 0x05 +0x00 0x6e 0x04 0x00 0x00 0x6f 0x05 0x00 0x6f 0x04 0x00 0x00 0x70 0x05 0x00 0x70 0x04 0x00 +0x00 0x71 0x05 0x00 0x71 0x04 0x00 0x00 0x72 0x05 0x00 0x72 0x04 0x00 0x00 0x73 0x05 0x00 +0x73 0x04 0x00 0x00 0x74 0x05 0x00 0x74 0x04 0x00 0x00 0x75 0x05 0x00 0x75 0x04 0x00 0x00 +0x76 0x05 0x00 0x76 0x04 0x00 0x00 0x77 0x05 0x00 0x77 0x04 0x00 0x00 0x78 0x05 0x00 0x78 +0x04 0x00 0x00 0x79 0x05 0x00 0x79 0x04 0x00 0x00 0x7a 0x05 0x00 0x7a 0x04 0x00 0x00 0x7b +0x05 0x00 0x7b 0x04 0x00 0x00 0x7c 0x05 0x00 0x7c 0x04 0x00 0x00 0x7d 0x05 0x00 0x7d 0x04 +0x00 0x00 0x7e 0x05 0x00 0x7e 0x04 0x00 0x00 0x7f 0x05 0x00 0x7f 0x04 0x00 0x00 0x80 0x05 +0x00 0x80 0x04 0x00 0x00 0x81 0x05 0x00 0x81 0x04 0x00 0x00 0x82 0x05 0x00 0x82 0x04 0x00 +0x00 0x83 0x05 0x00 0x83 0x04 0x00 0x00 0x84 0x05 0x00 0x84 0x04 0x00 0x00 0x85 0x05 0x00 +0x85 0x04 0x00 0x00 0x86 0x05 0x00 0x86 0x04 0x00 0x00 0x87 0x05 0x00 0x87 0x04 0x00 0x00 +0x88 0x05 0x00 0x88 0x04 0x00 0x00 0x89 0x05 0x00 0x89 0x04 0x00 0x00 0x8a 0x05 0x00 0x8a +0x04 0x00 0x00 0x8b 0x05 0x00 0x8b 0x04 0x00 0x00 0x8c 0x05 0x00 0x8c 0x04 0x00 0x00 0x8d +0x05 0x00 0x8d 0x04 0x00 0x00 0x8e 0x05 0x00 0x8e 0x04 0x00 0x00 0x8f 0x05 0x00 0x8f 0x04 +0x00 0x00 0x90 0x05 0x00 0x90 0x04 0x00 0x00 0x91 0x05 0x00 0x91 0x04 0x00 0x00 0x92 0x05 +0x00 0x92 0x04 0x00 0x00 0x93 0x05 0x00 0x93 0x04 0x00 0x00 0x94 0x05 0x00 0x94 0x04 0x00 +0x00 0x95 0x05 0x00 0x95 0x04 0x00 0x00 0x96 0x05 0x00 0x96 0x04 0x00 0x00 0x97 0x05 0x00 +0x97 0x04 0x00 0x00 0x98 0x05 0x00 0x98 0x04 0x00 0x00 0x99 0x05 0x00 0x99 0x04 0x00 0x00 +0x9a 0x05 0x00 0x9a 0x04 0x00 0x00 0x9b 0x05 0x00 0x9b 0x04 0x00 0x00 0x9c 0x05 0x00 0x9c +0x04 0x00 0x00 0x9d 0x05 0x00 0x9d 0x04 0x00 0x00 0x9e 0x05 0x00 0x9e 0x04 0x00 0x00 0x9f +0x05 0x00 0x9f 0x04 0x00 0x00 0xa0 0x05 0x00 0xa0 0x04 0x00 0x00 0xa1 0x05 0x00 0xa1 0x04 +0x00 0x00 0xa2 0x05 0x00 0xa2 0x04 0x00 0x00 0xa3 0x05 0x00 0xa3 0x04 0x00 0x00 0xa4 0x05 +0x00 0xa4 0x04 0x00 0x00 0xa5 0x05 0x00 0xa5 0x04 0x00 0x00 0xa6 0x05 0x00 0xa6 0x04 0x00 +0x00 0xa7 0x05 0x00 0xa7 0x04 0x00 0x00 0xa8 0x05 0x00 0xa8 0x04 0x00 0x00 0xa9 0x05 0x00 +0xa9 0x04 0x00 0x00 0xaa 0x05 0x00 0xaa 0x04 0x00 0x00 0xab 0x05 0x00 0xab 0x04 0x00 0x00 +0xac 0x05 0x00 0xac 0x04 0x00 0x00 0xad 0x05 0x00 0xad 0x04 0x00 0x00 0xae 0x05 0x00 0xae +0x04 0x00 0x00 0xaf 0x05 0x00 0xaf 0x04 0x00 0x00 0xb0 0x05 0x00 0xb0 0x04 0x00 0x00 0xb1 +0x05 0x00 0xb1 0x04 0x00 0x00 0xb2 0x05 0x00 0xb2 0x04 0x00 0x00 0xb3 0x05 0x00 0xb3 0x04 +0x00 0x00 0xb4 0x05 0x00 0xb4 0x04 0x00 0x00 0xb5 0x05 0x00 0xb5 0x04 0x00 0x00 0xb6 0x05 +0x00 0xb6 0x04 0x00 0x00 0xb7 0x05 0x00 0xb7 0x04 0x00 0x00 0xb8 0x05 0x00 0xb8 0x04 0x00 +0x00 0xb9 0x05 0x00 0xb9 0x04 0x00 0x00 0xba 0x05 0x00 0xba 0x04 0x00 0x00 0xbb 0x05 0x00 +0xbb 0x04 0x00 0x00 0xbc 0x05 0x00 0xbc 0x04 0x00 0x00 0xbd 0x05 0x00 0xbd 0x04 0x00 0x00 +0xbe 0x05 0x00 0xbe 0x04 0x00 0x00 0xbf 0x05 0x00 0xbf 0x04 0x00 0x00 0xc0 0x05 0x00 0xc0 +0x04 0x00 0x00 0xc1 0x05 0x00 0xc1 0x04 0x00 0x00 0xc2 0x05 0x00 0xc2 0x04 0x00 0x00 0xc3 +0x05 0x00 0xc3 0x04 0x00 0x00 0xc4 0x05 0x00 0xc4 0x04 0x00 0x00 0xc5 0x05 0x00 0xc5 0x04 +0x00 0x00 0xc6 0x05 0x00 0xc6 0x04 0x00 0x00 0xc7 0x05 0x00 0xc7 0x04 0x00 0x00 0xc8 0x05 +0x00 0xc8 0x04 0x00 0x00 0xc9 0x05 0x00 0xc9 0x04 0x00 0x00 0xca 0x05 0x00 0xca 0x04 0x00 +0x00 0xcb 0x05 0x00 0xcb 0x04 0x00 0x00 0xcc 0x05 0x00 0xcc 0x04 0x00 0x00 0xcd 0x05 0x00 +0xcd 0x04 0x00 0x00 0xce 0x05 0x00 0xce 0x04 0x00 0x00 0xcf 0x05 0x00 0xcf 0x04 0x00 0x00 +0xd0 0x05 0x00 0xd0 0x04 0x00 0x00 0xd1 0x05 0x00 0xd1 0x04 0x00 0x00 0xd2 0x05 0x00 0xd2 +0x04 0x00 0x00 0xd3 0x05 0x00 0xd3 0x04 0x00 0x00 0xd4 0x05 0x00 0xd4 0x04 0x00 0x00 0xd5 +0x05 0x00 0xd5 0x04 0x00 0x00 0xd6 0x05 0x00 0xd6 0x04 0x00 0x00 0xd7 0x05 0x00 0xd7 0x04 +0x00 0x00 0xd8 0x05 0x00 0xd8 0x04 0x00 0x00 0xd9 0x05 0x00 0xd8 0x04 0x00 0x00 0xda 0x05 +0x00 0xda 0x04 0x00 0x00 0xdb 0x05 0x00 0xdb 0x04 0x00 0x00 0xdc 0x05 0x00 0xdc 0x04 0x00 +0x00 0xdd 0x05 0x00 0xdd 0x04 0x00 0x00 0xde 0x05 0x00 0xde 0x04 0x00 0x00 0xdf 0x05 0x00 +0xdf 0x04 0x00 0x00 0xe0 0x05 0x00 0xe0 0x04 0x00 0x00 0xe1 0x05 0x00 0xe1 0x04 0x00 0x00 +0xe2 0x05 0x00 0xe2 0x04 0x00 0x00 0xe3 0x05 0x00 0xe3 0x04 0x00 0x00 0xe4 0x05 0x00 0xe4 +0x04 0x00 0x00 0xe5 0x05 0x00 0xe5 0x04 0x00 0x00 0xe6 0x05 0x00 0xe6 0x04 0x00 0x00 0xe7 +0x05 0x00 0xe7 0x04 0x00 0x00 0xe8 0x05 0x00 0xe8 0x04 0x00 0x00 0xe9 0x05 0x00 0xe9 0x04 +0x00 0x00 0xea 0x05 0x00 0xea 0x04 0x00 0x00 0xeb 0x05 0x00 0xeb 0x04 0x00 0x00 0xec 0x05 +0x00 0xec 0x04 0x00 0x00 0xed 0x05 0x00 0xed 0x04 0x00 0x00 0xee 0x05 0x00 0xee 0x04 0x00 +0x00 0xef 0x05 0x00 0xef 0x04 0x00 0x00 0xf0 0x05 0x00 0xf0 0x04 0x00 0x00 0xf1 0x05 0x00 +0xf1 0x04 0x00 0x00 0xf2 0x05 0x00 0xf2 0x04 0x00 0x00 0xf3 0x05 0x00 0xf3 0x04 0x00 0x00 +0xf4 0x05 0x00 0xf4 0x04 0x00 0x00 0xf5 0x05 0x00 0xf5 0x04 0x00 0x00 0xf6 0x05 0x00 0xf6 +0x04 0x00 0x00 0xf7 0x05 0x00 0xf7 0x04 0x00 0x00 0xf8 0x05 0x00 0xf8 0x04 0x00 0x00 0xf9 +0x05 0x00 0xf9 0x04 0x00 0x00 0xfa 0x05 0x00 0xfa 0x04 0x00 0x00 0xfb 0x05 0x00 0xfb 0x04 +0x00 0x00 0xfc 0x05 0x00 0xfc 0x04 0x00 0x00 0xfd 0x05 0x00 0xfd 0x04 0x00 0x00 0xfe 0x05 +0x00 0xfe 0x04 0x00 0x00 0xff 0x05 0x00 0xff 0x04 0x00 0x00 0xa0 0x05 0x00 0xa0 0x04 0x00 +0x00 0x00 0x06 0x00 0x00 0x04 0x00 0x00 0x01 0x06 0x00 0x01 0x04 0x00 0x00 0x02 0x06 0x00 +0x02 0x04 0x00 0x00 0x03 0x06 0x00 0x03 0x04 0x00 0x00 0x04 0x06 0x00 0x04 0x04 0x00 0x00 +0x05 0x06 0x00 0x05 0x04 0x00 0x00 0x06 0x06 0x00 0x06 0x04 0x00 0x00 0x07 0x06 0x00 0x07 +0x04 0x00 0x00 0x08 0x06 0x00 0x08 0x04 0x00 0x00 0x09 0x06 0x00 0x09 0x04 0x00 0x00 0x0a +0x06 0x00 0x0a 0x04 0x00 0x00 0x0b 0x06 0x00 0x0b 0x04 0x00 0x00 0x0c 0x06 0x00 0x0c 0x04 +0x00 0x00 0x0d 0x06 0x00 0x0d 0x04 0x00 0x00 0x0e 0x06 0x00 0x0e 0x04 0x00 0x00 0x0f 0x06 +0x00 0x0f 0x04 0x00 0x00 0x10 0x06 0x00 0x10 0x04 0x00 0x00 0x11 0x06 0x00 0x11 0x04 0x00 +0x00 0x12 0x06 0x00 0x12 0x04 0x00 0x00 0x13 0x06 0x00 0x13 0x04 0x00 0x00 0x14 0x06 0x00 +0x14 0x04 0x00 0x00 0x15 0x06 0x00 0x15 0x04 0x00 0x00 0x16 0x06 0x00 0x16 0x04 0x00 0x00 +0x17 0x06 0x00 0x17 0x04 0x00 0x00 0x18 0x06 0x00 0x18 0x04 0x00 0x00 0x19 0x06 0x00 0x19 +0x04 0x00 0x00 0x1a 0x06 0x00 0x1a 0x04 0x00 0x00 0x1b 0x06 0x00 0x1b 0x04 0x00 0x00 0x1c +0x06 0x00 0x1c 0x04 0x00 0x00 0x1d 0x06 0x00 0x1d 0x04 0x00 0x00 0x1e 0x06 0x00 0x1e 0x04 +0x00 0x00 0x1f 0x06 0x00 0x1f 0x04 0x00 0x00 0x20 0x06 0x00 0x20 0x04 0x00 0x00 0x21 0x06 +0x00 0x21 0x04 0x00 0x00 0x22 0x06 0x00 0x22 0x04 0x00 0x00 0x23 0x06 0x00 0x23 0x04 0x00 +0x00 0x24 0x06 0x00 0x24 0x04 0x00 0x00 0x25 0x06 0x00 0x25 0x04 0x00 0x00 0x26 0x06 0x00 +0x26 0x04 0x00 0x00 0x27 0x06 0x00 0x27 0x04 0x00 0x00 0x28 0x06 0x00 0x28 0x04 0x00 0x00 +0x29 0x06 0x00 0x29 0x04 0x00 0x00 0x2a 0x06 0x00 0x2a 0x04 0x00 0x00 0x2b 0x06 0x00 0x2b +0x04 0x00 0x00 0x2c 0x06 0x00 0x2c 0x04 0x00 0x00 0x2d 0x06 0x00 0x2d 0x04 0x00 0x00 0x2e +0x06 0x00 0x2e 0x04 0x00 0x00 0x2f 0x06 0x00 0x2f 0x04 0x00 0x00 0x30 0x06 0x00 0x30 0x04 +0x00 0x00 0x31 0x06 0x00 0x31 0x04 0x00 0x00 0x32 0x06 0x00 0x32 0x04 0x00 0x00 0x33 0x06 +0x00 0x33 0x04 0x00 0x00 0x34 0x06 0x00 0x34 0x04 0x00 0x00 0x35 0x06 0x00 0x35 0x04 0x00 +0x00 0x36 0x06 0x00 0x36 0x04 0x00 0x00 0x37 0x06 0x00 0x37 0x04 0x00 0x00 0x38 0x06 0x00 +0x38 0x04 0x00 0x00 0x39 0x06 0x00 0x39 0x04 0x00 0x00 0x3a 0x06 0x00 0x3a 0x04 0x00 0x00 +0x3b 0x06 0x00 0x3b 0x04 0x00 0x00 0x3c 0x06 0x00 0x3c 0x04 0x00 0x00 0x3d 0x06 0x00 0x3d +0x04 0x00 0x00 0x3e 0x06 0x00 0x3e 0x04 0x00 0x00 0x3f 0x06 0x00 0x3f 0x04 0x00 0x00 0x40 +0x06 0x00 0x40 0x04 0x00 0x00 0x41 0x06 0x00 0x41 0x04 0x00 0x00 0x42 0x06 0x00 0x42 0x04 +0x00 0x00 0x43 0x06 0x00 0x43 0x04 0x00 0x00 0x44 0x06 0x00 0x44 0x04 0x00 0x00 0x45 0x06 +0x00 0x45 0x04 0x00 0x00 0x46 0x06 0x00 0x46 0x04 0x00 0x00 0x47 0x06 0x00 0x47 0x04 0x00 +0x00 0x48 0x06 0x00 0x48 0x04 0x00 0x00 0x49 0x06 0x00 0x49 0x04 0x00 0x00 0x4a 0x06 0x00 +0x4a 0x04 0x00 0x00 0x4b 0x06 0x00 0x4b 0x04 0x00 0x00 0x4c 0x06 0x00 0x4c 0x04 0x00 0x00 +0x4d 0x06 0x00 0x4d 0x04 0x00 0x00 0x4e 0x06 0x00 0x4e 0x04 0x00 0x00 0x4f 0x06 0x00 0x4f +0x04 0x00 0x00 0x50 0x06 0x00 0x50 0x04 0x00 0x00 0x51 0x06 0x00 0x51 0x04 0x00 0x00 0x52 +0x06 0x00 0x52 0x04 0x00 0x00 0x53 0x06 0x00 0x53 0x04 0x00 0x00 0x54 0x06 0x00 0x54 0x04 +0x00 0x00 0x55 0x06 0x00 0x55 0x04 0x00 0x00 0x56 0x06 0x00 0x56 0x04 0x00 0x00 0x57 0x06 +0x00 0x57 0x04 0x00 0x00 0x58 0x06 0x00 0x58 0x04 0x00 0x00 0x59 0x06 0x00 0x59 0x04 0x00 +0x00 0x5a 0x06 0x00 0x5a 0x04 0x00 0x00 0x5b 0x06 0x00 0x5b 0x04 0x00 0x00 0x5c 0x06 0x00 +0x5c 0x04 0x00 0x00 0x5d 0x06 0x00 0x5d 0x04 0x00 0x00 0x5e 0x06 0x00 0x5e 0x04 0x00 0x00 +0x5f 0x06 0x00 0x5f 0x04 0x00 0x00 0x60 0x06 0x00 0x60 0x04 0x00 0x00 0x61 0x06 0x00 0x61 +0x04 0x00 0x00 0x62 0x06 0x00 0x62 0x04 0x00 0x00 0x63 0x06 0x00 0x63 0x04 0x00 0x00 0x64 +0x06 0x00 0x64 0x04 0x00 0x00 0x65 0x06 0x00 0x65 0x04 0x00 0x00 0x66 0x06 0x00 0x66 0x04 +0x00 0x00 0x67 0x06 0x00 0x67 0x04 0x00 0x00 0x68 0x06 0x00 0x68 0x04 0x00 0x00 0x69 0x06 +0x00 0x69 0x04 0x00 0x00 0x6a 0x06 0x00 0x6a 0x04 0x00 0x00 0x6b 0x06 0x00 0x6b 0x04 0x00 +0x00 0x6c 0x06 0x00 0x6c 0x04 0x00 0x00 0x6d 0x06 0x00 0x6d 0x04 0x00 0x00 0x6e 0x06 0x00 +0x6e 0x04 0x00 0x00 0x6f 0x06 0x00 0x6f 0x04 0x00 0x00 0x70 0x06 0x00 0x70 0x04 0x00 0x00 +0x71 0x06 0x00 0x71 0x04 0x00 0x00 0x72 0x06 0x00 0x72 0x04 0x00 0x00 0x73 0x06 0x00 0x73 +0x04 0x00 0x00 0x74 0x06 0x00 0x74 0x04 0x00 0x00 0x75 0x06 0x00 0x75 0x04 0x00 0x00 0x76 +0x06 0x00 0x76 0x04 0x00 0x00 0x77 0x06 0x00 0x77 0x04 0x00 0x00 0x78 0x06 0x00 0x78 0x04 +0x00 0x00 0x79 0x06 0x00 0x79 0x04 0x00 0x00 0x7a 0x06 0x00 0x7a 0x04 0x00 0x00 0x7b 0x06 +0x00 0x7b 0x04 0x00 0x00 0x7c 0x06 0x00 0x7c 0x04 0x00 0x00 0x7d 0x06 0x00 0x7d 0x04 0x00 +0x00 0x7e 0x06 0x00 0x7e 0x04 0x00 0x00 0x7f 0x06 0x00 0x7f 0x04 0x00 0x00 0x80 0x06 0x00 +0x80 0x04 0x00 0x00 0x81 0x06 0x00 0x81 0x04 0x00 0x00 0x82 0x06 0x00 0x82 0x04 0x00 0x00 +0x83 0x06 0x00 0x83 0x04 0x00 0x00 0x84 0x06 0x00 0x84 0x04 0x00 0x00 0x85 0x06 0x00 0x85 +0x04 0x00 0x00 0x86 0x06 0x00 0x86 0x04 0x00 0x00 0x87 0x06 0x00 0x87 0x04 0x00 0x00 0x88 +0x06 0x00 0x88 0x04 0x00 0x00 0x89 0x06 0x00 0x89 0x04 0x00 0x00 0x8a 0x06 0x00 0x8a 0x04 +0x00 0x00 0x8b 0x06 0x00 0x8b 0x04 0x00 0x00 0x8c 0x06 0x00 0x8c 0x04 0x00 0x00 0x8d 0x06 +0x00 0x8d 0x04 0x00 0x00 0x8e 0x06 0x00 0x8e 0x04 0x00 0x00 0x8f 0x06 0x00 0x8f 0x04 0x00 +0x00 0x90 0x06 0x00 0x90 0x04 0x00 0x00 0x91 0x06 0x00 0x91 0x04 0x00 0x00 0x92 0x06 0x00 +0x92 0x04 0x00 0x00 0x93 0x06 0x00 0x93 0x04 0x00 0x00 0x94 0x06 0x00 0x94 0x04 0x00 0x00 +0x95 0x06 0x00 0x95 0x04 0x00 0x00 0x96 0x06 0x00 0x96 0x04 0x00 0x00 0x97 0x06 0x00 0x97 +0x04 0x00 0x00 0x98 0x06 0x00 0x98 0x04 0x00 0x00 0x99 0x06 0x00 0x99 0x04 0x00 0x00 0x9a +0x06 0x00 0x9a 0x04 0x00 0x00 0x9b 0x06 0x00 0x9b 0x04 0x00 0x00 0x9c 0x06 0x00 0x9c 0x04 +0x00 0x00 0x9d 0x06 0x00 0x9d 0x04 0x00 0x00 0x9e 0x06 0x00 0x9e 0x04 0x00 0x00 0x9f 0x06 +0x00 0x9f 0x04 0x00 0x00 0xa0 0x06 0x00 0xa0 0x04 0x00 0x00 0xa1 0x06 0x00 0xa1 0x04 0x00 +0x00 0xa2 0x06 0x00 0xa2 0x04 0x00 0x00 0xa3 0x06 0x00 0xa3 0x04 0x00 0x00 0xa4 0x06 0x00 +0xa4 0x04 0x00 0x00 0xa5 0x06 0x00 0xa5 0x04 0x00 0x00 0xa6 0x06 0x00 0xa6 0x04 0x00 0x00 +0xa7 0x06 0x00 0xa7 0x04 0x00 0x00 0xa8 0x06 0x00 0xa8 0x04 0x00 0x00 0xa9 0x06 0x00 0xa9 +0x04 0x00 0x00 0xaa 0x06 0x00 0xaa 0x04 0x00 0x00 0xab 0x06 0x00 0xab 0x04 0x00 0x00 0xac +0x06 0x00 0xac 0x04 0x00 0x00 0xad 0x06 0x00 0xad 0x04 0x00 0x00 0xae 0x06 0x00 0xae 0x04 +0x00 0x00 0xaf 0x06 0x00 0xaf 0x04 0x00 0x00 0xb0 0x06 0x00 0xb0 0x04 0x00 0x00 0xb1 0x06 +0x00 0xb1 0x04 0x00 0x00 0xb2 0x06 0x00 0xb2 0x04 0x00 0x00 0xb3 0x06 0x00 0xb3 0x04 0x00 +0x00 0xb4 0x06 0x00 0xb4 0x04 0x00 0x00 0xb5 0x06 0x00 0xb5 0x04 0x00 0x00 0xb6 0x06 0x00 +0xb6 0x04 0x00 0x00 0xb7 0x06 0x00 0xb7 0x04 0x00 0x00 0xb8 0x06 0x00 0xb8 0x04 0x00 0x00 +0xb9 0x06 0x00 0xb9 0x04 0x00 0x00 0xba 0x06 0x00 0xba 0x04 0x00 0x00 0xbb 0x06 0x00 0xbb +0x04 0x00 0x00 0xbc 0x06 0x00 0xbc 0x04 0x00 0x00 0xbd 0x06 0x00 0xbd 0x04 0x00 0x00 0xbe +0x06 0x00 0xbe 0x04 0x00 0x00 0xbf 0x06 0x00 0xbf 0x04 0x00 0x00 0xc0 0x06 0x00 0xc0 0x04 +0x00 0x00 0xc1 0x06 0x00 0xc1 0x04 0x00 0x00 0xc2 0x06 0x00 0xc2 0x04 0x00 0x00 0xc3 0x06 +0x00 0xc3 0x04 0x00 0x00 0xc4 0x06 0x00 0xc4 0x04 0x00 0x00 0xc5 0x06 0x00 0xc5 0x04 0x00 +0x00 0xc6 0x06 0x00 0xc6 0x04 0x00 0x00 0xc7 0x06 0x00 0xc7 0x04 0x00 0x00 0xc8 0x06 0x00 +0xc8 0x04 0x00 0x00 0xc9 0x06 0x00 0xc9 0x04 0x00 0x00 0xca 0x06 0x00 0xca 0x04 0x00 0x00 +0xcb 0x06 0x00 0xcb 0x04 0x00 0x00 0xcc 0x06 0x00 0xcc 0x04 0x00 0x00 0xcd 0x06 0x00 0xcd +0x04 0x00 0x00 0xce 0x06 0x00 0xce 0x04 0x00 0x00 0xcf 0x06 0x00 0xcf 0x04 0x00 0x00 0xd0 +0x06 0x00 0xd0 0x04 0x00 0x00 0xd1 0x06 0x00 0xd1 0x04 0x00 0x00 0xd2 0x06 0x00 0xd2 0x04 +0x00 0x00 0xd3 0x06 0x00 0xd3 0x04 0x00 0x00 0xd4 0x06 0x00 0xd4 0x04 0x00 0x00 0xd5 0x06 +0x00 0xd5 0x04 0x00 0x00 0xd6 0x06 0x00 0xd6 0x04 0x00 0x00 0xd7 0x06 0x00 0xd7 0x04 0x00 +0x00 0xd8 0x06 0x00 0xd8 0x04 0x00 0x00 0xd9 0x06 0x00 0xd8 0x04 0x00 0x00 0xda 0x06 0x00 +0xda 0x04 0x00 0x00 0xdb 0x06 0x00 0xdb 0x04 0x00 0x00 0xdc 0x06 0x00 0xdc 0x04 0x00 0x00 +0xdd 0x06 0x00 0xdd 0x04 0x00 0x00 0xde 0x06 0x00 0xde 0x04 0x00 0x00 0xdf 0x06 0x00 0xdf +0x04 0x00 0x00 0xe0 0x06 0x00 0xe0 0x04 0x00 0x00 0xe1 0x06 0x00 0xe1 0x04 0x00 0x00 0xe2 +0x06 0x00 0xe2 0x04 0x00 0x00 0xe3 0x06 0x00 0xe3 0x04 0x00 0x00 0xe4 0x06 0x00 0xe4 0x04 +0x00 0x00 0xe5 0x06 0x00 0xe5 0x04 0x00 0x00 0xe6 0x06 0x00 0xe6 0x04 0x00 0x00 0xe7 0x06 +0x00 0xe7 0x04 0x00 0x00 0xe8 0x06 0x00 0xe8 0x04 0x00 0x00 0xe9 0x06 0x00 0xe9 0x04 0x00 +0x00 0xea 0x06 0x00 0xea 0x04 0x00 0x00 0xeb 0x06 0x00 0xeb 0x04 0x00 0x00 0xec 0x06 0x00 +0xec 0x04 0x00 0x00 0xed 0x06 0x00 0xed 0x04 0x00 0x00 0xee 0x06 0x00 0xee 0x04 0x00 0x00 +0xef 0x06 0x00 0xef 0x04 0x00 0x00 0xf0 0x06 0x00 0xf0 0x04 0x00 0x00 0xf1 0x06 0x00 0xf1 +0x04 0x00 0x00 0xf2 0x06 0x00 0xf2 0x04 0x00 0x00 0xf3 0x06 0x00 0xf3 0x04 0x00 0x00 0xf4 +0x06 0x00 0xf4 0x04 0x00 0x00 0xf5 0x06 0x00 0xf5 0x04 0x00 0x00 0xf6 0x06 0x00 0xf6 0x04 +0x00 0x00 0xf7 0x06 0x00 0xf7 0x04 0x00 0x00 0xf8 0x06 0x00 0xf8 0x04 0x00 0x00 0xf9 0x06 +0x00 0xf9 0x04 0x00 0x00 0xfa 0x06 0x00 0xfa 0x04 0x00 0x00 0xfb 0x06 0x00 0xfb 0x04 0x00 +0x00 0xfc 0x06 0x00 0xfc 0x04 0x00 0x00 0xfd 0x06 0x00 0xfd 0x04 0x00 0x00 0xfe 0x06 0x00 +0xfe 0x04 0x00 0x00 0xff 0x06 0x00 0xff 0x04 0x00 0x00 0xa0 0x06 0x00 0xa0 0x04 0x00 0x00 +0x00 0x07 0x00 0x00 0x04 0x00 0x00 0x01 0x07 0x00 0x01 0x04 0x00 0x00 0x02 0x07 0x00 0x02 +0x04 0x00 0x00 0x03 0x07 0x00 0x03 0x04 0x00 0x00 0x04 0x07 0x00 0x04 0x04 0x00 0x00 0x05 +0x07 0x00 0x05 0x04 0x00 0x00 0x06 0x07 0x00 0x06 0x04 0x00 0x00 0x07 0x07 0x00 0x07 0x04 +0x00 0x00 0x08 0x07 0x00 0x08 0x04 0x00 0x00 0x09 0x07 0x00 0x09 0x04 0x00 0x00 0x0a 0x07 +0x00 0x0a 0x04 0x00 0x00 0x0b 0x07 0x00 0x0b 0x04 0x00 0x00 0x0c 0x07 0x00 0x0c 0x04 0x00 +0x00 0x0d 0x07 0x00 0x0d 0x04 0x00 0x00 0x0e 0x07 0x00 0x0e 0x04 0x00 0x00 0x0f 0x07 0x00 +0x0f 0x04 0x00 0x00 0x10 0x07 0x00 0x10 0x04 0x00 0x00 0x11 0x07 0x00 0x11 0x04 0x00 0x00 +0x12 0x07 0x00 0x12 0x04 0x00 0x00 0x13 0x07 0x00 0x13 0x04 0x00 0x00 0x14 0x07 0x00 0x14 +0x04 0x00 0x00 0x15 0x07 0x00 0x15 0x04 0x00 0x00 0x16 0x07 0x00 0x16 0x04 0x00 0x00 0x17 +0x07 0x00 0x17 0x04 0x00 0x00 0x18 0x07 0x00 0x18 0x04 0x00 0x00 0x19 0x07 0x00 0x19 0x04 +0x00 0x00 0x1a 0x07 0x00 0x1a 0x04 0x00 0x00 0x1b 0x07 0x00 0x1b 0x04 0x00 0x00 0x1c 0x07 +0x00 0x1c 0x04 0x00 0x00 0x1d 0x07 0x00 0x1d 0x04 0x00 0x00 0x1e 0x07 0x00 0x1e 0x04 0x00 +0x00 0x1f 0x07 0x00 0x1f 0x04 0x00 0x00 0x20 0x07 0x00 0x20 0x04 0x00 0x00 0x21 0x07 0x00 +0x21 0x04 0x00 0x00 0x22 0x07 0x00 0x22 0x04 0x00 0x00 0x23 0x07 0x00 0x23 0x04 0x00 0x00 +0x24 0x07 0x00 0x24 0x04 0x00 0x00 0x25 0x07 0x00 0x25 0x04 0x00 0x00 0x26 0x07 0x00 0x26 +0x04 0x00 0x00 0x27 0x07 0x00 0x27 0x04 0x00 0x00 0x28 0x07 0x00 0x28 0x04 0x00 0x00 0x29 +0x07 0x00 0x29 0x04 0x00 0x00 0x2a 0x07 0x00 0x2a 0x04 0x00 0x00 0x2b 0x07 0x00 0x2b 0x04 +0x00 0x00 0x2c 0x07 0x00 0x2c 0x04 0x00 0x00 0x2d 0x07 0x00 0x2d 0x04 0x00 0x00 0x2e 0x07 +0x00 0x2e 0x04 0x00 0x00 0x2f 0x07 0x00 0x2f 0x04 0x00 0x00 0x30 0x07 0x00 0x30 0x04 0x00 +0x00 0x31 0x07 0x00 0x31 0x04 0x00 0x00 0x32 0x07 0x00 0x32 0x04 0x00 0x00 0x33 0x07 0x00 +0x33 0x04 0x00 0x00 0x34 0x07 0x00 0x34 0x04 0x00 0x00 0x35 0x07 0x00 0x35 0x04 0x00 0x00 +0x36 0x07 0x00 0x36 0x04 0x00 0x00 0x37 0x07 0x00 0x37 0x04 0x00 0x00 0x38 0x07 0x00 0x38 +0x04 0x00 0x00 0x39 0x07 0x00 0x39 0x04 0x00 0x00 0x3a 0x07 0x00 0x3a 0x04 0x00 0x00 0x3b +0x07 0x00 0x3b 0x04 0x00 0x00 0x3c 0x07 0x00 0x3c 0x04 0x00 0x00 0x3d 0x07 0x00 0x3d 0x04 +0x00 0x00 0x3e 0x07 0x00 0x3e 0x04 0x00 0x00 0x3f 0x07 0x00 0x3f 0x04 0x00 0x00 0x40 0x07 +0x00 0x40 0x04 0x00 0x00 0x41 0x07 0x00 0x41 0x04 0x00 0x00 0x42 0x07 0x00 0x42 0x04 0x00 +0x00 0x43 0x07 0x00 0x43 0x04 0x00 0x00 0x44 0x07 0x00 0x44 0x04 0x00 0x00 0x45 0x07 0x00 +0x45 0x04 0x00 0x00 0x46 0x07 0x00 0x46 0x04 0x00 0x00 0x47 0x07 0x00 0x47 0x04 0x00 0x00 +0x48 0x07 0x00 0x48 0x04 0x00 0x00 0x49 0x07 0x00 0x49 0x04 0x00 0x00 0x4a 0x07 0x00 0x4a +0x04 0x00 0x00 0x4b 0x07 0x00 0x4b 0x04 0x00 0x00 0x4c 0x07 0x00 0x4c 0x04 0x00 0x00 0x4d +0x07 0x00 0x4d 0x04 0x00 0x00 0x4e 0x07 0x00 0x4e 0x04 0x00 0x00 0x4f 0x07 0x00 0x4f 0x04 +0x00 0x00 0x50 0x07 0x00 0x50 0x04 0x00 0x00 0x51 0x07 0x00 0x51 0x04 0x00 0x00 0x52 0x07 +0x00 0x52 0x04 0x00 0x00 0x53 0x07 0x00 0x53 0x04 0x00 0x00 0x54 0x07 0x00 0x54 0x04 0x00 +0x00 0x55 0x07 0x00 0x55 0x04 0x00 0x00 0x56 0x07 0x00 0x56 0x04 0x00 0x00 0x57 0x07 0x00 +0x57 0x04 0x00 0x00 0x58 0x07 0x00 0x58 0x04 0x00 0x00 0x59 0x07 0x00 0x59 0x04 0x00 0x00 +0x5a 0x07 0x00 0x5a 0x04 0x00 0x00 0x5b 0x07 0x00 0x5b 0x04 0x00 0x00 0x5c 0x07 0x00 0x5c +0x04 0x00 0x00 0x5d 0x07 0x00 0x5d 0x04 0x00 0x00 0x5e 0x07 0x00 0x5e 0x04 0x00 0x00 0x5f +0x07 0x00 0x5f 0x04 0x00 0x00 0x60 0x07 0x00 0x60 0x04 0x00 0x00 0x61 0x07 0x00 0x61 0x04 +0x00 0x00 0x62 0x07 0x00 0x62 0x04 0x00 0x00 0x63 0x07 0x00 0x63 0x04 0x00 0x00 0x64 0x07 +0x00 0x64 0x04 0x00 0x00 0x65 0x07 0x00 0x65 0x04 0x00 0x00 0x66 0x07 0x00 0x66 0x04 0x00 +0x00 0x67 0x07 0x00 0x67 0x04 0x00 0x00 0x68 0x07 0x00 0x68 0x04 0x00 0x00 0x69 0x07 0x00 +0x69 0x04 0x00 0x00 0x6a 0x07 0x00 0x6a 0x04 0x00 0x00 0x6b 0x07 0x00 0x6b 0x04 0x00 0x00 +0x6c 0x07 0x00 0x6c 0x04 0x00 0x00 0x6d 0x07 0x00 0x6d 0x04 0x00 0x00 0x6e 0x07 0x00 0x6e +0x04 0x00 0x00 0x6f 0x07 0x00 0x6f 0x04 0x00 0x00 0x70 0x07 0x00 0x70 0x04 0x00 0x00 0x71 +0x07 0x00 0x71 0x04 0x00 0x00 0x72 0x07 0x00 0x72 0x04 0x00 0x00 0x73 0x07 0x00 0x73 0x04 +0x00 0x00 0x74 0x07 0x00 0x74 0x04 0x00 0x00 0x75 0x07 0x00 0x75 0x04 0x00 0x00 0x76 0x07 +0x00 0x76 0x04 0x00 0x00 0x77 0x07 0x00 0x77 0x04 0x00 0x00 0x78 0x07 0x00 0x78 0x04 0x00 +0x00 0x79 0x07 0x00 0x79 0x04 0x00 0x00 0x7a 0x07 0x00 0x7a 0x04 0x00 0x00 0x7b 0x07 0x00 +0x7b 0x04 0x00 0x00 0x7c 0x07 0x00 0x7c 0x04 0x00 0x00 0x7d 0x07 0x00 0x7d 0x04 0x00 0x00 +0x7e 0x07 0x00 0x7e 0x04 0x00 0x00 0x7f 0x07 0x00 0x7f 0x04 0x00 0x00 0x80 0x07 0x00 0x80 +0x04 0x00 0x00 0x81 0x07 0x00 0x81 0x04 0x00 0x00 0x82 0x07 0x00 0x82 0x04 0x00 0x00 0x83 +0x07 0x00 0x83 0x04 0x00 0x00 0x84 0x07 0x00 0x84 0x04 0x00 0x00 0x85 0x07 0x00 0x85 0x04 +0x00 0x00 0x86 0x07 0x00 0x86 0x04 0x00 0x00 0x87 0x07 0x00 0x87 0x04 0x00 0x00 0x88 0x07 +0x00 0x88 0x04 0x00 0x00 0x89 0x07 0x00 0x89 0x04 0x00 0x00 0x8a 0x07 0x00 0x8a 0x04 0x00 +0x00 0x8b 0x07 0x00 0x8b 0x04 0x00 0x00 0x8c 0x07 0x00 0x8c 0x04 0x00 0x00 0x8d 0x07 0x00 +0x8d 0x04 0x00 0x00 0x8e 0x07 0x00 0x8e 0x04 0x00 0x00 0x8f 0x07 0x00 0x8f 0x04 0x00 0x00 +0x90 0x07 0x00 0x90 0x04 0x00 0x00 0x91 0x07 0x00 0x91 0x04 0x00 0x00 0x92 0x07 0x00 0x92 +0x04 0x00 0x00 0x93 0x07 0x00 0x93 0x04 0x00 0x00 0x94 0x07 0x00 0x94 0x04 0x00 0x00 0x95 +0x07 0x00 0x95 0x04 0x00 0x00 0x96 0x07 0x00 0x96 0x04 0x00 0x00 0x97 0x07 0x00 0x97 0x04 +0x00 0x00 0x98 0x07 0x00 0x98 0x04 0x00 0x00 0x99 0x07 0x00 0x99 0x04 0x00 0x00 0x9a 0x07 +0x00 0x9a 0x04 0x00 0x00 0x9b 0x07 0x00 0x9b 0x04 0x00 0x00 0x9c 0x07 0x00 0x9c 0x04 0x00 +0x00 0x9d 0x07 0x00 0x9d 0x04 0x00 0x00 0x9e 0x07 0x00 0x9e 0x04 0x00 0x00 0x9f 0x07 0x00 +0x9f 0x04 0x00 0x00 0xa0 0x07 0x00 0xa0 0x04 0x00 0x00 0xa1 0x07 0x00 0xa1 0x04 0x00 0x00 +0xa2 0x07 0x00 0xa2 0x04 0x00 0x00 0xa3 0x07 0x00 0xa3 0x04 0x00 0x00 0xa4 0x07 0x00 0xa4 +0x04 0x00 0x00 0xa5 0x07 0x00 0xa5 0x04 0x00 0x00 0xa6 0x07 0x00 0xa6 0x04 0x00 0x00 0xa7 +0x07 0x00 0xa7 0x04 0x00 0x00 0xa8 0x07 0x00 0xa8 0x04 0x00 0x00 0xa9 0x07 0x00 0xa9 0x04 +0x00 0x00 0xaa 0x07 0x00 0xaa 0x04 0x00 0x00 0xab 0x07 0x00 0xab 0x04 0x00 0x00 0xac 0x07 +0x00 0xac 0x04 0x00 0x00 0xad 0x07 0x00 0xad 0x04 0x00 0x00 0xae 0x07 0x00 0xae 0x04 0x00 +0x00 0xaf 0x07 0x00 0xaf 0x04 0x00 0x00 0xb0 0x07 0x00 0xb0 0x04 0x00 0x00 0xb1 0x07 0x00 +0xb1 0x04 0x00 0x00 0xb2 0x07 0x00 0xb2 0x04 0x00 0x00 0xb3 0x07 0x00 0xb3 0x04 0x00 0x00 +0xb4 0x07 0x00 0xb4 0x04 0x00 0x00 0xb5 0x07 0x00 0xb5 0x04 0x00 0x00 0xb6 0x07 0x00 0xb6 +0x04 0x00 0x00 0xb7 0x07 0x00 0xb7 0x04 0x00 0x00 0xb8 0x07 0x00 0xb8 0x04 0x00 0x00 0xb9 +0x07 0x00 0xb9 0x04 0x00 0x00 0xba 0x07 0x00 0xba 0x04 0x00 0x00 0xbb 0x07 0x00 0xbb 0x04 +0x00 0x00 0xbc 0x07 0x00 0xbc 0x04 0x00 0x00 0xbd 0x07 0x00 0xbd 0x04 0x00 0x00 0xbe 0x07 +0x00 0xbe 0x04 0x00 0x00 0xbf 0x07 0x00 0xbf 0x04 0x00 0x00 0xc0 0x07 0x00 0xc0 0x04 0x00 +0x00 0xc1 0x07 0x00 0xc1 0x04 0x00 0x00 0xc2 0x07 0x00 0xc2 0x04 0x00 0x00 0xc3 0x07 0x00 +0xc3 0x04 0x00 0x00 0xc4 0x07 0x00 0xc4 0x04 0x00 0x00 0xc5 0x07 0x00 0xc5 0x04 0x00 0x00 +0xc6 0x07 0x00 0xc6 0x04 0x00 0x00 0xc7 0x07 0x00 0xc7 0x04 0x00 0x00 0xc8 0x07 0x00 0xc8 +0x04 0x00 0x00 0xc9 0x07 0x00 0xc9 0x04 0x00 0x00 0xca 0x07 0x00 0xca 0x04 0x00 0x00 0xcb +0x07 0x00 0xcb 0x04 0x00 0x00 0xcc 0x07 0x00 0xcc 0x04 0x00 0x00 0xcd 0x07 0x00 0xcd 0x04 +0x00 0x00 0xce 0x07 0x00 0xce 0x04 0x00 0x00 0xcf 0x07 0x00 0xcf 0x04 0x00 0x00 0xd0 0x07 +0x00 0xd0 0x04 0x00 0x00 0xd1 0x07 0x00 0xd1 0x04 0x00 0x00 0xd2 0x07 0x00 0xd2 0x04 0x00 +0x00 0xd3 0x07 0x00 0xd3 0x04 0x00 0x00 0xd4 0x07 0x00 0xd4 0x04 0x00 0x00 0xd5 0x07 0x00 +0xd5 0x04 0x00 0x00 0xd6 0x07 0x00 0xd6 0x04 0x00 0x00 0xd7 0x07 0x00 0xd7 0x04 0x00 0x00 +0xd8 0x07 0x00 0xd8 0x04 0x00 0x00 0xd9 0x07 0x00 0xd8 0x04 0x00 0x00 0xda 0x07 0x00 0xda +0x04 0x00 0x00 0xdb 0x07 0x00 0xdb 0x04 0x00 0x00 0xdc 0x07 0x00 0xdc 0x04 0x00 0x00 0xdd +0x07 0x00 0xdd 0x04 0x00 0x00 0xde 0x07 0x00 0xde 0x04 0x00 0x00 0xdf 0x07 0x00 0xdf 0x04 +0x00 0x00 0xe0 0x07 0x00 0xe0 0x04 0x00 0x00 0xe1 0x07 0x00 0xe1 0x04 0x00 0x00 0xe2 0x07 +0x00 0xe2 0x04 0x00 0x00 0xe3 0x07 0x00 0xe3 0x04 0x00 0x00 0xe4 0x07 0x00 0xe4 0x04 0x00 +0x00 0xe5 0x07 0x00 0xe5 0x04 0x00 0x00 0xe6 0x07 0x00 0xe6 0x04 0x00 0x00 0xe7 0x07 0x00 +0xe7 0x04 0x00 0x00 0xe8 0x07 0x00 0xe8 0x04 0x00 0x00 0xe9 0x07 0x00 0xe9 0x04 0x00 0x00 +0xea 0x07 0x00 0xea 0x04 0x00 0x00 0xeb 0x07 0x00 0xeb 0x04 0x00 0x00 0xec 0x07 0x00 0xec +0x04 0x00 0x00 0xed 0x07 0x00 0xed 0x04 0x00 0x00 0xee 0x07 0x00 0xee 0x04 0x00 0x00 0xef +0x07 0x00 0xef 0x04 0x00 0x00 0xf0 0x07 0x00 0xf0 0x04 0x00 0x00 0xf1 0x07 0x00 0xf1 0x04 +0x00 0x00 0xf2 0x07 0x00 0xf2 0x04 0x00 0x00 0xf3 0x07 0x00 0xf3 0x04 0x00 0x00 0xf4 0x07 +0x00 0xf4 0x04 0x00 0x00 0xf5 0x07 0x00 0xf5 0x04 0x00 0x00 0xf6 0x07 0x00 0xf6 0x04 0x00 +0x00 0xf7 0x07 0x00 0xf7 0x04 0x00 0x00 0xf8 0x07 0x00 0xf8 0x04 0x00 0x00 0xf9 0x07 0x00 +0xf9 0x04 0x00 0x00 0xfa 0x07 0x00 0xfa 0x04 0x00 0x00 0xfb 0x07 0x00 0xfb 0x04 0x00 0x00 +0xfc 0x07 0x00 0xfc 0x04 0x00 0x00 0xfd 0x07 0x00 0xfd 0x04 0x00 0x00 0xfe 0x07 0x00 0xfe +0x04 0x00 0x00 0xff 0x07 0x00 0xff 0x04 0x00 0x00 0xa0 0x07 0x00 0xa0 0x04 0x00 0x00 0xbca +0x08 0x12 0x00 0x00 0xbd4 0x08 0x1c 0x00 0x00 0xbd5 0x08 0x1d 0x00 0x00 0xfbc 0x09 0x1c>; + phandle = <0x10d>; + + amba@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0d>; + + downstream_amba_lpd { + compatible = "qemu:memory-region"; + alias = <0x0a>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_fpd { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0c>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_ocm@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb400000 0x00 0x10000 0x00 0x0d 0x00 +0xbbf00000 0x00 0x80000 0x02>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbf00000>; + phandle = <0x10e>; + }; + + xmpu_ocm2@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb9e0000 0x00 0x10000 0x00 0x0d 0x00 +0xbbe00000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbe00000>; + phandle = <0x10f>; + }; + + loader_write_cpu0_0x1@0xF1110880 { + compatible = "loader"; + addr = <0xf1110880>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x110>; + }; + + loader_write_cpu0_0x5@0xFD1A0050 { + compatible = "loader"; + addr = <0xfd1a0050>; + data = <0x05>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x111>; + }; + + loader_write_cpu0_0xFF@0xF111010C { + compatible = "loader"; + addr = <0xf111010c>; + data = <0xff>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x112>; + }; + + s_axi_tcm_a@0 { + compatible = "qemu:memory-region"; + alias = <0x0f>; + reg = <0x00 0xeba00000 0x00 0x800000 0x00>; + phandle = <0x34>; + }; + + s_axi_tcm_b@0 { + compatible = "qemu:memory-region"; + alias = <0x10>; + reg = <0x00 0xeba80000 0x00 0x800000 0x00>; + phandle = <0x38>; + }; + + s_axi_tcm_c@0 { + compatible = "qemu:memory-region"; + alias = <0x11>; + reg = <0x00 0xebb00000 0x00 0x800000 0x00>; + phandle = <0x3c>; + }; + + s_axi_tcm_d@0 { + compatible = "qemu:memory-region"; + alias = <0x12>; + reg = <0x00 0xebb80000 0x00 0x800000 0x00>; + phandle = <0x40>; + }; + + s_axi_tcm_e@0 { + compatible = "qemu:memory-region"; + alias = <0x13>; + reg = <0x00 0xebc00000 0x00 0x800000 0x00>; + phandle = <0x44>; + }; + + loader_write_cpu0_0x80C@0xF12B0100 { + compatible = "loader"; + addr = <0xf12b0100>; + data = <0x80c>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x113>; + }; + + loader_write_cpu0_0x77@0xF1260320 { + compatible = "loader"; + addr = <0xf1260320>; + data = <0x77>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x114>; + }; + + xmpu_ocm1@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb980000 0x00 0x10000 0x00 0x0d 0x00 +0xbbf80000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbf80000>; + phandle = <0x115>; + }; + + xmpu_ocm3@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeaa10000 0x00 0x10000 0x00 0x0d 0x00 +0xbbe80000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbe80000>; + phandle = <0x116>; + }; + }; + + amba_lpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0a>; + + downstream_amba_psm { + compatible = "qemu:memory-region"; + alias = <0x14>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_xram { + compatible = "qemu:memory-region"; + alias = <0x15>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xppu_lpd@0xeb990000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0a 0x00 0xeb990000 0x00 0x10000 0x00 0x16 0x00 +0xeb000000 0x00 0x1000000 0x02 0x16 0x00 0xea000000 0x00 0x1000000 0x02>; + mr = <0x0a>; + interrupts = <0x13>; + phandle = <0x117>; + }; + + ethernet@0xf1a60000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x27 0x27>; + dma = <0x17>; + memattr = <0x18>; + memattr-write = <0x19>; + reg = <0x00 0xf1a60000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x1a 0x01>; + power-gpios = <0x1b 0x2c>; + mdio = <0x1c>; + phandle = <0x118>; + }; + + ethernet@0xf1a70000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x29 0x29>; + dma = <0x17>; + memattr = <0x1d>; + memattr-write = <0x1e>; + reg = <0x00 0xf1a70000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x1a 0x02>; + power-gpios = <0x1b 0x2d>; + mdio = <0x1c>; + phandle = <0x119>; + }; + + serial@0xf1920000 { + compatible = "pl011"; + interrupts = <0x19>; + reg = <0x00 0xf1920000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x05>; + chardev = "serial2"; + phandle = <0x11a>; + }; + + serial@0xf1930000 { + compatible = "pl011"; + interrupts = <0x1a>; + reg = <0x00 0xf1930000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x06>; + chardev = "con"; + phandle = <0x11b>; + }; + + canfdbus@0 { + compatible = "can-bus"; + phandle = <0x1f>; + }; + + can@0xf19e0000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x1b>; + reg = <0x00 0xf19e0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x09>; + phandle = <0x11c>; + }; + + can@0xf19f0000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x1c>; + reg = <0x00 0xf19f0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0a>; + phandle = <0x11d>; + }; + + crl@0xeb5e0000 { + compatible = "xlnx,psxc_crl"; + reg = <0x00 0xeb5e0000 0x00 0x300000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a>; + }; + + slcr@0xf1a20000 { + compatible = "xlnx,versal-lpd-iou-slcr"; + reg = <0x00 0xf1a20000 0x00 0x20000 0x00>; + phandle = <0x11e>; + }; + + ipi@0xeb300000 { + compatible = "xlnx,versal-ipi"; + reg = <0x00 0xeb300000 0x00 0x100000 0x00>; + interrupts = <0xfbc 0xbd4 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0xbd5 +0x46 0x40 0x41 0x42 0x43 0x44 0x45>; + reset-gpios = <0x1a 0x19>; + num-master-ids = <0x20>; + phandle = <0x11f>; + }; + + spi@0xf19c0000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x17>; + num-ss-bits = <0x04>; + reg = <0x00 0xf19c0000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x1a 0x07>; + phandle = <0x120>; + + spi0_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi0_flash0"; + phandle = <0x121>; + + spi0_flash0@0x00000000 { + label = "spi0_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + spi@0xf19d0000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x18>; + num-ss-bits = <0x04>; + reg = <0x00 0xf19d0000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x1a 0x08>; + phandle = <0x122>; + + spi1_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi1_flash0"; + phandle = <0x123>; + + spi1_flash0@0x00000000 { + label = "spi1_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + usb2@USB2_0_XHCI { + compatible = "usb_dwc3"; + reg = <0x00 0xf1b0c100 0x00 0x600 0x00 0x00 0xf1b00000 0x00 +0x100000 0x00>; + interrupts = <0x1d 0x1e 0x1f 0x20>; + dma = <0x17>; + memattr = <0x20>; + reset-gpios = <0x1a 0x03>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0x124>; + }; + + timer@0xf1e60000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2b 0x2b 0x2b>; + reg = <0x00 0xf1e60000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x12>; + phandle = <0x125>; + }; + + timer@0xf1e70000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2c 0x2c 0x2c>; + reg = <0x00 0xf1e70000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x13>; + phandle = <0x126>; + }; + + timer@0xf1e80000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2d 0x2d 0x2d>; + reg = <0x00 0xf1e80000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x14>; + phandle = <0x127>; + }; + + timer@0xf1e90000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2e 0x2e 0x2e>; + reg = <0x00 0xf1e90000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x15>; + phandle = <0x128>; + }; + + adma0mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x210>; + phandle = <0x21>; + }; + + dma-controller@0xebd00000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd00000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x48>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x21>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x00>; + phandle = <0x129>; + }; + + adma1mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x212>; + phandle = <0x23>; + }; + + dma-controller@0xebd10000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd10000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x49>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x23>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x01>; + phandle = <0x12a>; + }; + + adma2mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x214>; + phandle = <0x24>; + }; + + dma-controller@0xebd20000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd20000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4a>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x24>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x02>; + phandle = <0x12b>; + }; + + adma3mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x216>; + phandle = <0x25>; + }; + + dma-controller@0xebd30000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd30000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4b>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x25>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x03>; + phandle = <0x12c>; + }; + + adma4mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x218>; + phandle = <0x26>; + }; + + dma-controller@0xebd40000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd40000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4c>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x26>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x04>; + phandle = <0x12d>; + }; + + adma5mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21a>; + phandle = <0x27>; + }; + + dma-controller@0xebd50000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd50000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4d>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x27>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x05>; + phandle = <0x12e>; + }; + + adma6mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21c>; + phandle = <0x28>; + }; + + dma-controller@0xebd60000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd60000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4e>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x28>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x06>; + phandle = <0x12f>; + }; + + adma7mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21e>; + phandle = <0x29>; + }; + + dma-controller@0xebd70000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd70000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4f>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x29>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x07>; + phandle = <0x130>; + }; + + afi_fm@0xeb9b0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xeb9b0000 0x00 0x10000 0x00>; + }; + + lpd_i2c_wrapper { + + ps_i2c@0xf1940000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x15>; + reg-extended = <0x0a 0x00 0xf1940000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0b>; + phandle = <0x131>; + }; + + ps_i2c@0xf1950000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x16>; + reg-extended = <0x0a 0x00 0xf1950000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0c>; + phandle = <0x132>; + }; + + ps_i2c@0xf1960000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0b>; + reg-extended = <0x0a 0x00 0xf1960000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x30>; + phandle = <0x133>; + }; + + ps_i2c@0xf1970000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0c>; + reg-extended = <0x0a 0x00 0xf1970000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x31>; + phandle = <0x134>; + }; + + ps_i2c@0xf1980000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0d>; + reg-extended = <0x0a 0x00 0xf1980000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x32>; + phandle = <0x135>; + }; + + ps_i2c@0xf1990000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x64>; + reg-extended = <0x0a 0x00 0xf1990000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x33>; + phandle = <0x136>; + }; + + ps_i2c@0xf19a0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x65>; + reg-extended = <0x0a 0x00 0xf19a0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x34>; + phandle = <0x137>; + }; + + ps_i2c@0xf19b0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x66>; + reg-extended = <0x0a 0x00 0xf19b0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x35>; + phandle = <0x138>; + }; + }; + + ocm_ctrl@OCM { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x10>; + memsize = <0x80000>; + reg = <0x00 0xeb5d0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x18>; + phandle = <0x139>; + }; + + lpd_slcr@0xeb410000 { + compatible = "xlnx.psxc-lpx-slcr"; + reg = <0x00 0xeb410000 0x00 0x100000 0x00>; + interrupt-parent = <0x08>; + interrupts = <0x1e>; + #gpio-cells = <0x01>; + gpio-controller; + num-rpu = <0x0a>; + core-0 = <0x2a>; + core-1 = <0x2b>; + core-2 = <0x2c>; + core-3 = <0x2d>; + core-4 = <0x2e>; + core-5 = <0x2f>; + core-6 = <0x30>; + core-7 = <0x31>; + core-8 = <0x32>; + core-9 = <0x33>; + phandle = <0x1b>; + }; + + lpd_slcr_secure@0xeb510000 { + compatible = "xlnx.versal2-psxc-lpx-slcr-secure"; + reg = <0x00 0xeb510000 0x00 0x40000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x22>; + }; + + lpd_iou_slcr_secure@0xf1a40000 { + compatible = "xlnx,versal-lpd-iou-slcr-secure"; + reg = <0x00 0xf1a40000 0x00 0x10000 0x00>; + memattr-gem0 = <0x18>; + memattr-write-gem0 = <0x19>; + memattr-gem1 = <0x1d>; + memattr-write-gem1 = <0x1e>; + phandle = <0x13a>; + }; + + wwdt@0xeb000000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xeb000000 0x00 0x10000 0x00>; + interrupts = <0xec 0xed 0xee 0xef>; + pclk = <0x5f5e100>; + reset-gpios = <0x1a 0x17>; + phandle = <0x13b>; + }; + + lpd_gpio@0xf1a50000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0x14>; + reg = <0x00 0xf1a50000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x11>; + phandle = <0x13c>; + }; + + virtio_mmio_0 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e00000 0x00 0x1000 0x00>; + interrupts = <0x10e>; + }; + + virtio_mmio_1 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e01000 0x00 0x1000 0x00>; + interrupts = <0x10f>; + }; + + virtio_mmio_2 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e02000 0x00 0x1000 0x00>; + interrupts = <0x110>; + }; + + virtio_mmio_3 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e03000 0x00 0x1000 0x00>; + interrupts = <0x111>; + }; + + virtio_mmio_4 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e04000 0x00 0x1000 0x00>; + interrupts = <0x112>; + }; + + virtio_mmio_5 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e05000 0x00 0x1000 0x00>; + interrupts = <0x113>; + }; + + virtio_mmio_6 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e06000 0x00 0x1000 0x00>; + interrupts = <0x114>; + }; + + virtio_mmio_7 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e07000 0x00 0x1000 0x00>; + interrupts = <0x115>; + }; + + rpu_ctrl@0 { + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x13d>; + }; + + rpu_cluster@0xeb580000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb580000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x34>; + phandle = <0x36>; + }; + + rpu_ctrl_a0@0xeb588000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb588000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x23>; + core = <0x2a>; + tcm-mr = <0x35>; + phandle = <0xe5>; + }; + + rpu_ctrl_a1@0xeb58c000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb58c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x24 0x36 0x00>; + core = <0x2b>; + tcm-mr = <0x37>; + phandle = <0xe8>; + }; + + rpu_cluster@0xeb590000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb590000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x38>; + phandle = <0x3a>; + }; + + rpu_ctrl_b0@0xeb598000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb598000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x25>; + core = <0x2c>; + tcm-mr = <0x39>; + phandle = <0xeb>; + }; + + rpu_ctrl_b1@0xeb59c000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb59c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x26 0x3a 0x00>; + core = <0x2d>; + tcm-mr = <0x3b>; + phandle = <0xee>; + }; + + rpu_cluster@0xeb5a0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5a0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x3c>; + phandle = <0x3e>; + }; + + rpu_ctrl_c0@0xeb5a8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5a8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x27>; + core = <0x2e>; + tcm-mr = <0x3d>; + phandle = <0xf1>; + }; + + rpu_ctrl_c1@0xeb5ac000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5ac000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x28 0x3e 0x00>; + core = <0x2f>; + tcm-mr = <0x3f>; + phandle = <0xf4>; + }; + + rpu_cluster@0xeb5b0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5b0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x40>; + phandle = <0x42>; + }; + + rpu_ctrl_d0@0xeb5b8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5b8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x29>; + core = <0x30>; + tcm-mr = <0x41>; + phandle = <0xf7>; + }; + + rpu_ctrl_d1@0xeb5bc000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5bc000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2a 0x42 0x00>; + core = <0x31>; + tcm-mr = <0x43>; + phandle = <0xfa>; + }; + + rpu_cluster@0xeb5c0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5c0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x44>; + phandle = <0x46>; + }; + + rpu_ctrl_e0@0xeb5c8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5c8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2b>; + core = <0x32>; + tcm-mr = <0x45>; + phandle = <0xfd>; + }; + + rpu_ctrl_e1@0xeb5cc000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5cc000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2c 0x46 0x00>; + core = <0x33>; + tcm-mr = <0x47>; + phandle = <0x100>; + }; + + usb2@USB2_0_XHCI1 { + compatible = "usb_dwc3"; + reg = <0x00 0xf1c0c100 0x00 0x600 0x00 0x00 0xf1c00000 0x00 +0x100000 0x00>; + interrupts = <0x22 0x23 0x24 0x25>; + dma = <0x17>; + memattr = <0x48>; + reset-gpios = <0x1a 0x04>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0x13e>; + }; + + i3c0@0xf1940000 { + compatible = "dwc.i3c"; + reg = <0x00 0xf1948000 0x00 0x10000 0x00>; + num-devices = <0x0b>; + interrupts = <0x15>; + phandle = <0x13f>; + }; + + i3c1@0xf1950000 { + compatible = "dwc.i3c"; + reg = <0x00 0xf1958000 0x00 0x10000 0x00>; + slave-static-addr-en = <0x01>; + device-id = <0x01>; + interrupts = <0x16>; + phandle = <0x140>; + }; + + ocm_ctrl@0xeb960000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x11>; + memsize = <0x80000>; + reg = <0x00 0xeb960000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf1>; + phandle = <0x141>; + }; + + ocm_ctrl@0xeb9d0000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x0e>; + memsize = <0x80000>; + reg = <0x00 0xeb9d0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf2>; + phandle = <0x142>; + }; + + ocm_ctrl@0xeaa00000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x0f>; + memsize = <0x80000>; + reg = <0x00 0xeaa00000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf3>; + phandle = <0x143>; + }; + + can@0xf1a00000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x5f>; + reg = <0x00 0xf1a00000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x2e>; + phandle = <0x144>; + }; + + can@0xf1a10000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x60>; + reg = <0x00 0xf1a10000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x2f>; + phandle = <0x145>; + }; + + timer@0xf1ea0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2f 0x2f 0x2f>; + reg = <0x00 0xf1ea0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x36>; + phandle = <0x146>; + }; + + timer@0xf1eb0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x30 0x30 0x30>; + reg = <0x00 0xf1eb0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x37>; + phandle = <0x147>; + }; + + timer@0xf1ec0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x31 0x31 0x31>; + reg = <0x00 0xf1ec0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x38>; + phandle = <0x148>; + }; + + timer@0xf1ed0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x32 0x32 0x32>; + reg = <0x00 0xf1ed0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x39>; + phandle = <0x149>; + }; + + sdma0mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x220>; + phandle = <0x49>; + }; + + dma-controller@0xebd80000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd80000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x70>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x49>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x08>; + phandle = <0x14a>; + }; + + sdma1mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x222>; + phandle = <0x4a>; + }; + + dma-controller@0xebd90000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd90000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x71>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4a>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x09>; + phandle = <0x14b>; + }; + + sdma2mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x224>; + phandle = <0x4b>; + }; + + dma-controller@0xebda0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebda0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x72>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4b>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0a>; + phandle = <0x14c>; + }; + + sdma3mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x226>; + phandle = <0x4c>; + }; + + dma-controller@0xebdb0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdb0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x73>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4c>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0b>; + phandle = <0x14d>; + }; + + sdma4mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x228>; + phandle = <0x4d>; + }; + + dma-controller@0xebdc0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdc0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x74>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4d>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0c>; + phandle = <0x14e>; + }; + + sdma5mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22a>; + phandle = <0x4e>; + }; + + dma-controller@0xebdd0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdd0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x75>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4e>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0d>; + phandle = <0x14f>; + }; + + sdma6mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22c>; + phandle = <0x4f>; + }; + + dma-controller@0xebde0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebde0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x76>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4f>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0e>; + phandle = <0x150>; + }; + + sdma7mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22e>; + phandle = <0x50>; + }; + + dma-controller@0xebdf0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdf0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x77>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x50>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0f>; + phandle = <0x151>; + }; + + wwdt@0xeb010000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xeb010000 0x00 0x10000 0x00>; + interrupts = <0xf0 0xf1 0xf2 0xf3>; + pclk = <0x5f5e100>; + reset-gpios = <0x1a 0x3a>; + phandle = <0x152>; + }; + + lpd_afi_fs@0xeb560000 { + compatible = "xlnx.psxc_afi_fs"; + reg = <0x00 0xeb560000 0x00 0x8000 0x00>; + phandle = <0x153>; + }; + + downstream_amba_asu { + compatible = "qemu:memory-region"; + alias = <0x51>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_fpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0b>; + + afi_fm@0xec880000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec880000 0x00 0x10000 0x00>; + }; + + afi_fm@0xec8a0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec8a0000 0x00 0x10000 0x00>; + }; + + cpm_crcpm@0xfca00000 { + compatible = "xlnx,versal_cpm_crcpm"; + reg = <0x00 0xfca00000 0x00 0x10000 0x00>; + }; + + cpm_pcsr@0xfcff0000 { + compatible = "xlnx,versal_cpm_pcsr"; + reg = <0x00 0xfcff0000 0x00 0x10000 0x00>; + }; + + cpm_slcr_secure@0xfca20000 { + compatible = "xlnx.cpm_slcr_secure"; + reg = <0x00 0xfca20000 0x00 0x10000 0x00>; + }; + + fpd_slcr@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr"; + interrupts = <0x8c>; + reg = <0x00 0xec8c0000 0x00 0x10000 0x00>; + }; + + fpd_slcr_secure@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr-secure"; + interrupts = <0x8c>; + reg = <0x00 0xec8e0000 0x00 0x10000 0x00>; + }; + + watchdog@0xecc10000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xecc10000 0x00 0x10000 0x00>; + interrupts = <0xec 0xed 0xee 0xef>; + pclk = <0x5f5e100>; + reset-gpios = <0x52 0x1b>; + phandle = <0x154>; + }; + + apu_cluster@0xecc00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecc00000 0x00 0x10000 0x00>; + cpu0 = <0x53>; + cpu1 = <0x54>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x155>; + }; + + apu_cluster@0xecd00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecd00000 0x00 0x10000 0x00>; + cpu0 = <0x56>; + cpu1 = <0x57>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x156>; + }; + + apu_cluster@0xece00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xece00000 0x00 0x10000 0x00>; + cpu0 = <0x58>; + cpu1 = <0x59>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x157>; + }; + + apu_cluster@0xecf00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecf00000 0x00 0x10000 0x00>; + cpu0 = <0x5a>; + cpu1 = <0x5b>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x158>; + }; + + cmn600ae@0xa0000000 { + compatible = "arm,cmn600ae"; + reg = <0x00 0xa0000000 0x00 0x3000000 0x00>; + }; + + smmuv3@MM_FPD_SMMU { + compatible = "arm-smmuv3"; + reg-extended = <0x0b 0x00 0xec000000 0x00 0x200000 0x00 0x17 0x00 +0x00 0xffffffff 0xffffffff 0x00 0x5c 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5d 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x5e 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5f 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x60 0x00 0x00 0xffffffff 0xffffffff 0x00 0x61 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x62 0x00 0x00 0xffffffff 0xffffffff 0x00 0x63 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x64 0x00 0x00 0xffffffff 0xffffffff 0x00 0x65 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x66 0x00 0x00 0xffffffff 0xffffffff 0x00 0x67 0x00 0x00 +0xffffffff 0xffffffff 0x00>; + mr-0 = <0x0d>; + mr-1 = <0x0d>; + mr-2 = <0x0d>; + mr-3 = <0x0d>; + mr-4 = <0x0d>; + mr-5 = <0x0d>; + mr-6 = <0x0d>; + mr-7 = <0x0d>; + mr-8 = <0x0d>; + mr-9 = <0x0d>; + mr-10 = <0x0d>; + mr-11 = <0x0d>; + mr-12 = <0x0d>; + dma_mr = <0x0d>; + primary-bus = <0x68>; + phandle = <0x159>; + }; + + dummy_pcie@0x6_0000_0000 { + compatible = "PCI"; + phandle = <0x68>; + }; + + apu_pcil@0xecb10000 { + compatible = "xlnx.apu_pcil"; + reg = <0x00 0xecb10000 0x00 0x10000 0x00>; + core-mask = <0x3333>; + cluster-mask = <0x0f>; + gpios = <0x1b 0x52 0x1b 0x53 0x1b 0x54 0x1b 0x55 0x1b 0x56 0x1b 0x57 +0x1b 0x58 0x1b 0x59 0x1b 0x5a 0x1b 0x5b 0x1b 0x5c 0x1b 0x5d 0x1b 0x5e 0x1b 0x5f 0x1b 0x60 0x1b 0x61 +0x1b 0x62 0x1b 0x63 0x1b 0x64 0x1b 0x65 0x1b 0x66 0x1b 0x67 0x1b 0x68 0x1b 0x69>; + core-0 = <0x53>; + core-1 = <0x54>; + core-4 = <0x56>; + core-5 = <0x57>; + core-8 = <0x58>; + core-9 = <0x59>; + core-12 = <0x5a>; + core-13 = <0x5b>; + phandle = <0x15a>; + }; + + lpd_afi_fs@0xec860000 { + compatible = "xlnx.psxc_afi_fs"; + reg = <0x00 0xec860000 0x00 0x8000 0x00>; + phandle = <0x15b>; + }; + + mmi_gem_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x25e>; + phandle = <0x69>; + }; + + mmi_usb_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x20e>; + phandle = <0x6b>; + }; + + amba_mmi@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x6d>; + + mdio_10gbe@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "mdio"; + phandle = <0x6a>; + + phy@1 { + compatible = "phy-clause45-generic"; + device_type = "ethernet-phy"; + reg = <0x01>; + phandle = <0x15c>; + }; + }; + + ethernet@0xed920000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + reg = <0x00 0xed920000 0x00 0x10000 0x00>; + interrupts = <0xa4 0xa4 0xa4 0xa4>; + dma = <0x5d>; + memattr = <0x69>; + num-priority-queues = <0x04>; + mdio = <0x6a>; + has-usxgmii = <0x01>; + phandle = <0x15d>; + }; + + usb_drd@0xedec0000 { + compatible = "usb_dwc3"; + reg = <0x00 0xedec0000 0x00 0x10000 0x00>; + interrupts = <0xbf 0xc0>; + dma = <0x5d>; + memattr = <0x6b>; + intrs = <0x02>; + slots = <0x02>; + phandle = <0x15e>; + }; + + mmi_crs@0xedc00000 { + compatible = "xlnx.mmi_crx"; + reg = <0x00 0xedc00000 0x00 0x10000 0x00>; + phandle = <0x15f>; + }; + + mmi_pcsr@0xeb2f0000 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xeb2f0000 0x00 0x10000 0x01>; + map-size = <0x10000>; + custom = <0x01>; + pcsr-status = <0x7ffe>; + phandle = <0x160>; + }; + + mmi_gtyp@0xed900000 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xed900000 0x00 0x20000 0x01>; + map-size = <0xed900000>; + custom = <0x01>; + pcsr-status = <0x3a00d0>; + phandle = <0x161>; + }; + + mmi_slcr_sec@0 { + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xedc30000 0x00 0x10000 0x00>; + read-only; + phandle = <0x162>; + }; + + trng@0xede80000 { + doc-status = "complete"; + compatible = "xlnx,versal-trng"; + reg = <0x00 0xede80000 0x00 0x10000 0x00>; + interrupts = <0xc7>; + #gpio-cells = <0x01>; + phandle = <0x6c>; + }; + + udh_slcr@0xedea0000 { + compatible = "xlnx.mmi_udh_slcr"; + reg = <0x00 0xedea0000 0x00 0x8000 0x00>; + gpios = <0x6c 0x00>; + phandle = <0x163>; + }; + + udh_pll@0xede90000 { + compatible = "xlnx.mmi_udh_pll"; + reg = <0x00 0xede90000 0x00 0x10000 0x00>; + phandle = <0x164>; + }; + + mmi_gpu_a@0 { + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xed0a0098 0x00 0x10 0x00>; + read-only; + phandle = <0x165>; + }; + + loader_write_cpu0_0x1@0xEDC30440 { + compatible = "loader"; + addr = <0xedc30440>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x166>; + }; + + loader_write_cpu0_0x7F@0xEDC30444 { + compatible = "loader"; + addr = <0xedc30444>; + data = <0x7f>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x167>; + }; + + loader_write_cpu0_0x1@0xEDC3044c { + compatible = "loader"; + addr = <0xedc3044c>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x168>; + }; + + loader_write_cpu0_0x1@0xEDC30450 { + compatible = "loader"; + addr = <0xedc30450>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x169>; + }; + + loader_write_cpu0_0x1@0xEDC30460 { + compatible = "loader"; + addr = <0xedc30460>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16a>; + }; + + loader_write_cpu0_0x7f@0xEDC30464 { + compatible = "loader"; + addr = <0xedc30464>; + data = <0x7f>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16b>; + }; + + loader_write_cpu0_0x1@0xEDC3046c { + compatible = "loader"; + addr = <0xedc3046c>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16c>; + }; + + loader_write_cpu0_0x1@0xEDC30470 { + compatible = "loader"; + addr = <0xedc30470>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16d>; + }; + + loader_write_cpu0_0x3@0xED0A0098 { + compatible = "loader"; + addr = <0xed0a0098>; + data = <0x03>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16e>; + }; + }; + + downstream_amba_mmi { + compatible = "qemu:memory-region"; + alias = <0x6d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_pmc_internal@0 { + doc-ignore = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0c>; + + downstream_amba_pmc_ppu { + compatible = "qemu:memory-region"; + alias = <0x6e>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_iou { + compatible = "qemu:memory-region"; + alias = <0x16>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sec { + compatible = "qemu:memory-region"; + alias = <0x6f>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sys { + compatible = "qemu:memory-region"; + alias = <0x70>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_pl { + compatible = "qemu:memory-region"; + alias = <0x71>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_bat { + compatible = "qemu:memory-region"; + alias = <0x72>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x13>; + reg-extended = <0x0c 0x00 0xf12f0000 0x00 0x10000 0x00 0x0c 0x00 +0xf2000000 0x00 0x20000 0x02>; + protected-mr = <0x73>; + mr-0 = <0x0c>; + protected-base = <0xf2000000>; + phandle = <0x16f>; + }; + + xppu_pmc_npi@0xf1300000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0c 0x00 0xf1300000 0x00 0x10000 0x00 0x0c 0x00 +0xf6000000 0x00 0x1000000 0x02 0x0c 0x00 0xf7000000 0x00 0x1000000 0x02>; + mr = <0x71>; + interrupts = <0x13>; + phandle = <0x170>; + }; + + xppu_pmc@0xf1310000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0c 0x00 0xf1310000 0x00 0x10000 0x00 0x0d 0x00 +0xf1000000 0x00 0x1000000 0x02 0x0d 0x00 0xf0000000 0x00 0x1000000 0x02 0x0d 0x00 0xc0000000 0x00 +0x20000000 0x02>; + mr = <0x0c>; + interrupts = <0x13>; + phandle = <0x171>; + }; + }; + + amba_pmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x74>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0c>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc_cfu@0xf1340000 { + compatible = "xlnx,versal-xmpu"; + reg-extended = <0x74 0x00 0xf1340000 0x00 0x10000 0x00 0x71 0x00 +0xf12b0000 0x00 0x11000 0x02 0x71 0x00 0xf1f80000 0x00 0x40000 0x02>; + protected-mr = <0x75>; + mr-0 = <0x71>; + protected-base = <0xf12b0000>; + phandle = <0x172>; + }; + + pmx_err_mng@0xf1110000 { + compatible = "xlnx,pmxc-err-mng"; + reg = <0x00 0xf1130000 0x00 0x10000 0x01>; + gpios = <0x76 0x03 0x1b 0x2e 0x1b 0x2f 0x1b 0x30 0x1b 0x31>; + interrupts = <0xbca>; + phandle = <0x173>; + }; + + intpmxc_config@0xf1400000 { + compatible = "xlnx.pmxc_intpmx_config"; + reg = <0x00 0xf1400000 0x00 0x300000 0x00>; + phandle = <0x174>; + }; + }; + + amba_pmc_iou@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC IOU"; + doc-status = "partial"; + phandle = <0x16>; + + pmc_iou_slcr@0xf1060000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmx-iou-slcr"; + reg = <0x00 0xf1060000 0x00 0x1000 0x00>; + interrupts = <0xde>; + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x85>; + }; + + pmc_iou_slcr_secure@0xf1070000 { + compatible = "xlnx,versal-pmc-iou-slcr-secure"; + reg = <0x00 0xf1070000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + memattr-sd0 = <0x77>; + memattr-write-sd0 = <0x78>; + memattr-sd1 = <0x79>; + memattr-write-sd1 = <0x7a>; + memattr-write-qspi = <0x7b>; + memattr-write-ospi = <0x7c>; + phandle = <0x175>; + }; + + pmc_qspi_dma@QSPI_DMA { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd9>; + #stream-id-cells = <0x01>; + reg = <0x00 0xf1030800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x7d>; + memattr-write = <0x7b>; + is-dst = <0x01>; + reset-gpios = <0x7e 0x00>; + phandle = <0x7f>; + }; + + pmc_qspi@0xf1030000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,usmp-gqspi\0cdns,spi-r1p6"; + stream-connected-dma = <0x7f>; + dma = <0x74>; + interrupts = <0xd9>; + num-ss-bits = <0x02>; + reg-extended = <0x16 0x00 0xf1030000 0x00 0x1000 0x00 0x80 0x00 0x00 +0x00 0x20000000 0x00>; + speed-hz = <0x989680>; + xlnx,fb-clk = <0x01>; + xlnx,qspi-clk-freq-hz = <0xbebc200>; + xlnx,qspi-mode = <0x02>; + reset-gpios = <0x7e 0x00>; + phandle = <0x176>; + + qspi_flash_lcs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + drive-index = <0x00>; + phandle = <0x177>; + + qspi_flash_lcs_lb@0x00000000 { + label = "qspi_flash_lcs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_lcs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x02 0x01>; + drive-index = <0x01>; + phandle = <0x178>; + + qspi_flash_lcs_ub@0x00000000 { + label = "qspi_flash_lcs_ub"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_ucs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x01 0x00>; + drive-index = <0x02>; + phandle = <0x179>; + + qspi_flash_ucs_lb@0x00000000 { + label = "qspi_flash_ucs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_ucs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x03 0x01>; + drive-index = <0x03>; + phandle = <0x17a>; + + qspi_flash_ucs_ub@0x00000000 { + label = "qspi_flash_ucs_ub"; + reg = <0x00 0x2000000>; + }; + }; + }; + + ospi_dst_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd8>; + reg = <0x00 0xf1011800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x81>; + memattr-write = <0x7c>; + is-dst = <0x01>; + reset-gpios = <0x7e 0x01>; + phandle = <0x83>; + }; + + ospi_src_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd8>; + reg = <0x00 0xf1011000 0x00 0x800 0x00>; + dma = <0x82>; + memattr = <0x81>; + memattr-write = <0x7c>; + stream-connected-dma = <0x83>; + reset-gpios = <0x7e 0x01>; + phandle = <0x84>; + }; + + spi@0xf1010000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,versal-ospi"; + reg-extended = <0x16 0x00 0xf1010000 0x00 0x1000 0x00 0x82 0x00 0x00 +0x00 0x20000000 0x00>; + dma-src = <0x84>; + interrupts = <0xd8>; + reset-gpios = <0x7e 0x01>; + gpios = <0x85 0x03 0x00>; + phandle = <0x17b>; + + ospi_flash_lcs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu02gbba"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + drive-index = <0x04>; + phandle = <0x17c>; + + ospi_flash_lcs_lb@0x00000000 { + label = "ospi_flash_lcs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_lcs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu02gbba"; + spi-max-frequency = <0x2faf080>; + reg = <0x01 0x00>; + drive-index = <0x05>; + phandle = <0x17d>; + + ospi_flash_lcs_ub@0x00000000 { + label = "ospi_flash_lcs_ub"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_ucs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu01gbba\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x02 0x00>; + drive-index = <0x06>; + phandle = <0x17e>; + + ospi_flash_ucs_lb@0x00000000 { + label = "ospi_flash_ucs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_ucs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu01gbba\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x03 0x00>; + drive-index = <0x07>; + phandle = <0x17f>; + + ospi_flash_ucs_ub@0x00000000 { + label = "ospi_flash_ucs_ub"; + reg = <0x00 0x2000000>; + }; + }; + }; + + gpio_mr_mux@0xc0000000 { + doc-status = "complete"; + compatible = "gpio-mr-mux"; + reg = <0x00 0xc0000000 0x00 0x20000000 0x00>; + gpios = <0x85 0x02 0x00 0x85 0x03 0x00>; + mr-size = <0x20000000>; + mr0 = <0x80>; + mr1 = <0x82>; + mr2 = <0x80>; + mr3 = <0x82>; + phandle = <0x180>; + }; + + pmc_gpio@0xf1020000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0xca>; + reg = <0x00 0xf1020000 0x00 0x10000 0x00>; + reset-gpios = <0x7e 0x05>; + phandle = <0x181>; + }; + + mmc@0xf1040000 { + doc-status = "complete"; + compatible = "xilinx,zynqmp-sdhci\0generic-sdhci"; + drive-index = <0x00>; + reg = <0x00 0xf1040000 0x00 0x10000 0x00>; + interrupts = <0xda>; + dma = <0x17>; + memattr = <0x77>; + memattr-write = <0x78>; + gpios = <0x85 0x00 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x7e 0x08>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x182>; + }; + + mmc@0xf1050000 { + doc-status = "complete"; + compatible = "xlnx,versalnet-emmc"; + drive-index = <0x01>; + reg = <0x00 0xf1050200 0x00 0x100 0x00 0x00 0xf1050000 0x00 +0x100 0x00>; + interrupts = <0xdc>; + dma = <0x17>; + memattr = <0x79>; + memattr-write = <0x7a>; + gpios = <0x85 0x01 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x7e 0x03>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x183>; + }; + + pmc_tap@0xf11a0000 { + doc-status = "complete"; + doc-comments = "Just a stub."; + compatible = "xlnx,pmc-tap"; + interrupts-extended = <0x86 0x1e>; + interrupt-names = "sec-dbg-int"; + reg = <0x00 0xf11a0000 0x00 0x80000 0x00>; + idcode = <0x14ca8093>; + platform-ver = <0x01>; + phandle = <0x184>; + }; + + pmc_i2c_wrapper { + + pmc_i2c@0xf1000000 { + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0xcb>; + reg-extended = <0x16 0x00 0xf1000000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reset-gpios = <0x7e 0x04>; + phandle = <0x185>; + }; + }; + + wwdt@0xf03f0000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xf03f0000 0x00 0x10000 0x00>; + pclk = <0x5f5e100>; + phandle = <0x186>; + }; + + pmc_ufshc@0xf10b0000 { + compatible = "ufshc-sysbus"; + reg = <0x00 0xf10b0000 0x00 0x10000 0x00>; + interrupts = <0xea>; + ufs-target = <0x87>; + unipro-mphy = <0x88>; + dma = <0x74>; + phandle = <0x89>; + }; + + unipro@0 { + compatible = "unipro-mphy"; + ufshc = <0x89>; + #gpio-cells = <0x01>; + phandle = <0x88>; + }; + + ufs_dev@0 { + compatible = "ufs-dev"; + num-luns = <0x08>; + phandle = <0x87>; + }; + + ufs_reg@0xf1060000 { + compatible = "dwc.ufs_reg"; + reg = <0x00 0xf1061000 0x00 0x100 0x01>; + gpios = <0x88 0x00>; + phandle = <0x187>; + }; + }; + + amba_pmc_sec@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC Secure"; + doc-status = "in-progress"; + qemu-fdt-abort-on-error = "Unable to create PMC security models. +Cannot continue.\nTry installing libgcrypt."; + phandle = <0x6f>; + + trng@0xf1230000 { + doc-status = "complete"; + compatible = "xlnx,versal-trng"; + reg = <0x00 0xf1230000 0x00 0x1000 0x00>; + interrupts = <0xe9>; + }; + + pmc_dma0_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma0 = <0x8a>; + reg = <0x00 0xf11c0000 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8b>; + dma-width = <0x10>; + interrupts = <0xe0>; + reset-gpios = <0x7e 0x13>; + byte-align = <0x01>; + phandle = <0x188>; + }; + + pmc_dma0_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11c0800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8b>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xe0>; + reset-gpios = <0x7e 0x13>; + byte-align = <0x01>; + phandle = <0x8d>; + }; + + pmc_dma1_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma1 = <0x8a>; + reg = <0x00 0xf11d0000 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8c>; + dma-width = <0x10>; + interrupts = <0xe1>; + reset-gpios = <0x7e 0x14>; + byte-align = <0x01>; + phandle = <0x189>; + }; + + pmc_dma1_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11d0800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8c>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xe1>; + reset-gpios = <0x7e 0x14>; + byte-align = <0x01>; + phandle = <0x8e>; + }; + + pmc_stream_switch@0 { + doc-status = "complete"; + compatible = "versal,pmc-sss"; + reg-extended = <0x70 0x00 0xf1110500 0x00 0x04 0x01>; + stream-connected-dma0 = <0x8d>; + stream-connected-dma1 = <0x8e>; + stream-connected-aes = <0x8f>; + stream-connected-sha = <0x90>; + stream-connected-sbi = <0x91>; + stream-connected-sha1 = <0x92>; + phandle = <0x8a>; + }; + + pmc_sha@0xf1210000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha3"; + reg = <0x00 0xf1210000 0x00 0x100 0x00>; + interrupts = <0xe7>; + phandle = <0x90>; + }; + + pmc_aes@0xf11e0000 { + doc-status = "in-progress"; + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx-pmxc-aes"; + stream-connected-aes = <0x8a>; + reg = <0x00 0xf11e0000 0x00 0x100 0x00>; + interrupts = <0xe4>; + gpios = <0x93 0x00 0x93 0x01>; + gpio-names = "busy\0done"; + aes-core = <0x93>; + integrated-endianness-swap = <0x01>; + asu-aes = <0x94>; + phandle = <0x8f>; + + xlnx_aes@0 { + #gpio-cells = <0x01>; + compatible = "xlnx-aes"; + gpios = <0x8f 0x00>; + gpio-names = "reset"; + phandle = <0x93>; + }; + }; + + pmc_rsa@0xf1200000 { + doc-status = "complete"; + compatible = "xlnx,versal-ecdsa-rsa"; + reg = <0x00 0xf1200000 0x00 0x6c 0x00>; + interrupts = <0xe5>; + ram-nr-words = <0x100>; + phandle = <0x18a>; + }; + + xlnx_pmc_efuse_cache@0xf1250000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_cache"; + reg = <0x00 0xf1250000 0x00 0x10000 0x00>; + efuse = <0x95>; + phandle = <0x99>; + }; + + pmc_puf_ctrl@0 { + compatible = "xlnx,versal-puf-ctrl"; + zynqmp-aes-key-sink-puf = <0x8f>; + efuse = <0x95>; + reg = <0x00 0xf1150000 0x00 0x10000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x97>; + }; + + pmc_efuse@0xf1240000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_ctrl"; + #gpio-cells = <0x02>; + zynqmp-aes-key-sink-efuses = <0x8f>; + zynqmp-aes-key-sink-efuses-user0 = <0x8f>; + zynqmp-aes-key-sink-efuses-user1 = <0x8f>; + reg = <0x00 0xf1240000 0x00 0x10000 0x00>; + interrupts = <0xe6>; + efuse = <0x95>; + phandle = <0x18b>; + + xlnx_efuse@0 { + doc-ignore = <0x01>; + compatible = "xlnx,efuse"; + efuse-nr = <0x03>; + efuse-size = <0x2000>; + init-factory-extidcode = <0x01>; + phandle = <0x95>; + }; + }; + + pmc_bbram@0xf11f0000 { + doc-status = "partial"; + doc-limitations = "Missing AES key connections."; + compatible = "xlnx,bbram-ctrl"; + reg = <0x00 0xf11f0000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + zynqmp-aes-key-sink-bbram = <0x8f>; + crc-zpads = <0x00>; + phandle = <0x98>; + }; + + pmc_sbi@0xf1220000 { + doc-status = "complete"; + compatible = "pmc,slave-boot"; + reg = <0x00 0xf1220000 0x00 0x10000 0x00 0x00 0xf2100000 +0x00 0x10000 0x00>; + interrupts = <0xe3>; + stream-connected-sbi = <0x8a>; + reset-gpios = <0x7e 0x12>; + phandle = <0x91>; + }; + + pmc_sha1@0xF1800000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha2"; + reg = <0x00 0xf1800000 0x00 0x10000 0x00>; + phandle = <0x92>; + }; + }; + + amba_pmc_ppu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x6e>; + + pmc_gic_proxy@0 { + doc-status = "complete"; + #interrupt-cells = <0x03>; + interrupt-controller; + compatible = "xlnx,zynqmp-gicp"; + reg = <0x00 0xf1140000 0x00 0x100 0x00>; + interrupt-parent = <0x08>; + interrupts = <0x10>; + max-ints = <0x100>; + phandle = <0x07>; + }; + }; + + amba_pmc_sys@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC System"; + doc-status = "partial"; + phandle = <0x70>; + + pmc_clk_rst@0xf1260000 { + doc-status = "partial"; + compatible = "xlnx,pmx_crp"; + reg = <0x00 0xf1260000 0x00 0x80000 0x00>; + interrupts = <0xbca>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x7e>; + }; + + pmc_int@0xf1400000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmc-int"; + reg = <0x00 0xf1400000 0x00 0x300000 0x00>; + interrupts = <0xe2>; + phandle = <0x18c>; + }; + + pmc_reset_domain@0 { + compatible = "qemu,reset-device"; + gpios = <0x7e 0x02>; + }; + + pmc_global@0xf1110000 { + doc-status = "partial"; + #gpio-cells = <0x01>; + gpio-controller; + interrupts-extended = <0x08 0x10 0x08 0x1b 0x08 0x1b 0x08 0x1b 0x08 +0x1b 0x08 0x11 0x08 0x11 0x96 0x00 0x86 0x10 0x86 0x11 0x86 0x12 0x86 0x13 0x86 0x14 0x86 0x15 0x86 +0x16 0x86 0x17 0x86 0x18 0x86 0x19 0x86 0x1a 0x86 0x1b 0x96 0x00 0x86 0x1d>; + reg = <0x00 0xf1110000 0x00 0x50000 0x00>; + gpios = <0x97 0x00>; + bbram = <0x98>; + efuse = <0x99>; + compatible = "xlnx,pmxc_global"; + phandle = <0x76>; + }; + + pmc_stream_zero@ { + compatible = "xlnx,pmc-stream-zero"; + reg = <0x00 0xf1110518 0x00 0x04 0x01>; + stream-connected-pzm = <0x8a>; + phandle = <0x18d>; + }; + + pmc_analog@0xf1160000 { + compatible = "xlnx,pmxc_anlg"; + reg = <0x00 0xf1160000 0x00 0x40000 0x00>; + interrupts-extended = <0x07 0x00 0x13 0x00>; + tamper-sink = <0x76>; + phandle = <0x18e>; + }; + + pmc_sysmon@0xf1270000 { + compatible = "xlnx,pmc-sysmon"; + reg = <0x00 0xf1270000 0x00 0x30000 0x00>; + interrupts = <0x12 0x79>; + reset-gpios = <0x7e 0x15>; + efuse = <0x99>; + ams-sats = <0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0>; + tamper-sink = <0x76>; + phandle = <0x18f>; + }; + + pmc_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1280000 0x00 0x10000 0x01>; + phandle = <0x9a>; + }; + + pmc_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1290000 0x00 0x10000 0x01>; + phandle = <0x9b>; + }; + + versal_pmc_tamper@ { + compatible = "xlnx,pmc_tamper"; + reg-extended = <0x70 0x00 0xf1110530 0x00 0x38 0x01 0xa1 0x00 +0xf0041100 0x00 0x38 0x02>; + phandle = <0x190>; + }; + + lpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xeb550000 0x00 0x10000 0x01>; + phandle = <0x9c>; + }; + + fpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecc30000 0x00 0x10000 0x01>; + phandle = <0x9d>; + }; + + fpd_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecd30000 0x00 0x10000 0x01>; + phandle = <0x9e>; + }; + + fpd_ams_sat@2 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xece30000 0x00 0x10000 0x01>; + phandle = <0x9f>; + }; + + fpd_ams_sat@3 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecf30000 0x00 0x10000 0x01>; + phandle = <0xa0>; + }; + }; + + amba_pmc_pl@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC PL"; + doc-status = "partial"; + phandle = <0x71>; + + noc_npi_nir@0xf6000000 { + compatible = "xlnx.npi-nir"; + reg = <0x00 0xf6000000 0x00 0x10000 0x01>; + phandle = <0x191>; + }; + + npi_ddrmc_ub0@0xf62c0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf62c0000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x192>; + }; + + npi_ddrmc_main0@0xf6290000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6290000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0xcf>; + }; + + npi_ddrmc_noc0@0xf62a0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf62a0000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x193>; + }; + + npi_ddrmc_ub1@0xf63b0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf63b0000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x194>; + }; + + npi_ddrmc_main1@0xf6380000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6380000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x195>; + }; + + npi_ddrmc_noc1@0xf6390000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6390000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x196>; + }; + + npi_ddrmc_ub2@0xf6940000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6940000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x197>; + }; + + npi_ddrmc_main2@0xf6910000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6910000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x198>; + }; + + npi_ddrmc_noc2@0xf6920000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6920000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x199>; + }; + + npi_ddrmc_ub3@0xf6a20000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6a20000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x19a>; + }; + + npi_ddrmc_main3@0xf69f0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf69f0000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19b>; + }; + + npi_ddrmc_noc3@0xf6a00000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6a00000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19c>; + }; + + npi_ddrmc_xmpu0@0xf62a0000 { + compatible = "xlnx,versal-ddrmc-xmpu"; + reg-extended = <0x71 0x00 0xf62b2000 0x00 0x10000 0x01 0x0d 0x00 +0x00 0x00 0x80000000 0x00>; + protected-mr = <0xa2>; + mr-0 = <0x0d>; + protected-base = <0x00>; + phandle = <0x19d>; + }; + + npi_me@0xf6540000 { + compatible = "xlnx.aie2p_s_npi"; + reg = <0x00 0xf6540000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19e>; + }; + + noc_npi_devs@0 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xf6000000 0x00 0x2000000 0x00>; + phandle = <0x19f>; + }; + + cfu_fdro@0xf12c2000 { + compatible = "xlnx,versal-cfu-fdro"; + reg = <0x00 0xf12c2000 0x00 0x1000 0x00>; + phandle = <0xa4>; + }; + + cfu_sfr@0xf12c1000 { + compatible = "xlnx,versal-cfu-sfr"; + reg = <0x00 0xf12c1000 0x00 0x1000 0x00>; + cfu = <0xa3>; + phandle = <0x1a0>; + }; + + cframe0_reg@0xf12d0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d0000 0x00 0x1000 0x00 0x00 0xf12d1000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x853f>; + blktype1-frames = <0xdc8>; + blktype2-frames = <0x3200>; + blktype3-frames = <0x0b>; + blktype4-frames = <0x05>; + blktype5-frames = <0x01>; + blktype6-frames = <0x01>; + phandle = <0xa5>; + }; + + cframe1_reg@0xf12d2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d2000 0x00 0x1000 0x00 0x00 0xf12d3000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa6>; + }; + + cframe2_reg@0xf12d4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d4000 0x00 0x1000 0x00 0x00 0xf12d5000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa7>; + }; + + cframe3_reg@0xf12d6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d6000 0x00 0x1000 0x00 0x00 0xf12d7000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa8>; + }; + + cframe4_reg@0xf12d8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d8000 0x00 0x1000 0x00 0x00 0xf12d9000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xa9>; + }; + + cframe5_reg@0xf12da000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12da000 0x00 0x1000 0x00 0x00 0xf12db000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xaa>; + }; + + cframe6_reg@0xf12dc000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12dc000 0x00 0x1000 0x00 0x00 0xf12dd000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xab>; + }; + + cframe7_reg@0xf12de000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12de000 0x00 0x1000 0x00 0x00 0xf12df000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xac>; + }; + + cframe8_reg@0xf12e0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e0000 0x00 0x1000 0x00 0x00 0xf12e1000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xad>; + }; + + cframe9_reg@0xf12e2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e2000 0x00 0x1000 0x00 0x00 0xf12e3000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xae>; + }; + + cframe10_reg@0xf12e4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e4000 0x00 0x1000 0x00 0x00 0xf12e5000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xaf>; + }; + + cframe11_reg@0xf12e6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e6000 0x00 0x1000 0x00 0x00 0xf12e7000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb0>; + }; + + cframe12_reg@0xf12e8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e8000 0x00 0x1000 0x00 0x00 0xf12e9000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb1>; + }; + + cframe13_reg@0xf12ea000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ea000 0x00 0x1000 0x00 0x00 0xf12eb000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb2>; + }; + + cframe14_reg@0xf12ec000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ec000 0x00 0x1000 0x00 0x00 0xf12ed000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb3>; + }; + + cframe_bcast_reg@0xf12ee000 { + compatible = "xlnx.cframe-bcast-reg"; + reg = <0x00 0xf12ee000 0x00 0x1000 0x00 0x00 0xf12ef000 +0x00 0x1000 0x00>; + cframe0 = <0xa5>; + cframe1 = <0xa6>; + cframe2 = <0xa7>; + cframe3 = <0xa8>; + cframe4 = <0xa9>; + cframe5 = <0xaa>; + cframe6 = <0xab>; + cframe7 = <0xac>; + cframe8 = <0xad>; + cframe9 = <0xae>; + cframe10 = <0xaf>; + cframe11 = <0xb0>; + cframe12 = <0xb1>; + cframe13 = <0xb2>; + cframe14 = <0xb3>; + phandle = <0x1a1>; + }; + + gtyp_npi_slave_0@0xf65a0000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf65a0000 0x00 0x20000 0x00>; + }; + + gtyp_npi_slave_1@0xf66c0000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf66c0000 0x00 0x20000 0x00>; + }; + + gtyp_npi_slave_2@0xf6720000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf6720000 0x00 0x20000 0x00>; + }; + + dummy_cfu_mem@0xf12b0000 { + compatible = "qemu:memory-region"; + phandle = <0x75>; + + cfu@0x0 { + doc-status = "partial"; + doc-comments = "Stub"; + doc-limitations = "No way to extract CFRAME data."; + compatible = "xlnx,versal-cfu"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x10000 0x00 0x1000 +0x00 0x00 0xcd0000 0x00 0x40000 0x00>; + chardev = "pmc-cfu"; + dma = <0x74>; + phandle = <0xa3>; + }; + }; + }; + + amba_pmc_bat@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC BAT"; + doc-status = "partial"; + phandle = <0x72>; + + rtc@0xf12a0000 { + doc-status = "complete"; + doc-comments = "Versal PMC RTC"; + compatible = "xlnx,zynqmp-rtc"; + interrupts = <0xbca 0xc8 0xc9>; + reg = <0x00 0xf12a0000 0x00 0x10000 0x00>; + xlnx,version = "2.0.0"; + phandle = <0x1a2>; + }; + }; + + amba_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x14>; + }; + + amba_xram@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x15>; + + xram_ctrl_0 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8e0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_1 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8f0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_2 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb900000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_3 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb910000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + }; + + crf@0xec200000 { + compatible = "xlnx,versal-psx-crf"; + reg-extended = <0x0b 0x00 0xec200000 0x00 0x100000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x52>; + }; + + amba_asu_cpu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + #interrupt-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xb4>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_asu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x51>; + + asu_instr_ram@0xebe00000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + qemu,ram = <0x01>; + reg = <0x00 0xebe00000 0x00 0x40000 0x00>; + phandle = <0x1a3>; + }; + + io-module@0xebe80000 { + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xb4>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_0"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1a4>; + + asu_io_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xb5 0x0b>; + reg = <0x00 0xebe8000c 0x04 0x00 0xebe80030 0x10 0x00 +0xebe80080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x09>; + }; + + asu_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x09>; + interrupts = <0x0b>; + reg = <0x00 0xebe80020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1a5>; + }; + + asu_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xebe80010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0xb6>; + }; + + asu_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xebe80014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1a6>; + }; + + asu_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x03>; + reg = <0x00 0xebe80040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xb6 0x01 0xb7 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a7>; + }; + + asu_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x04>; + reg = <0x00 0xebe80050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xb7>; + }; + + asu_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x05>; + reg = <0x00 0xebe80060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xb6 0x02 0xb8 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a8>; + }; + + asu_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x06>; + reg = <0x00 0xebe80070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xb8>; + }; + }; + + asu_mdm_uart@0xebef0000 { + compatible = "xlnx,xps-uartlite"; + reg = <0x00 0xebef0000 0x00 0x10 0x01>; + chardev = "serial4"; + phandle = <0x1a9>; + }; + + asu_global@0xebf80000 { + compatible = "xlnx,asu_global"; + reg = <0x00 0xebf80000 0x00 0x20000 0x00>; + gpios = <0xb9 0x00>; + phandle = <0x1aa>; + }; + + asu_global_pmc@0xebf80000 { + compatible = "xlnx,asu_global_pmc"; + reg = <0x00 0xebf90000 0x00 0x20000 0x00>; + phandle = <0x1ab>; + }; + + asu_local@0xebe8e000 { + compatible = "xlnx,asu_local_reg"; + reg = <0x00 0xebe8e000 0x00 0x2000 0x00>; + phandle = <0x1ac>; + }; + + asu_sss@0xebe8e000 { + compatible = "asu-sss"; + reg = <0x00 0xebe8e000 0x00 0x08 0x01>; + stream-connected-dma0 = <0xba>; + stream-connected-sha2 = <0xbb>; + stream-connected-sha3 = <0xbc>; + stream-connected-dma1 = <0xbd>; + stream-connected-aes = <0xb9>; + phandle = <0xbe>; + }; + + asu_dma_src@0xebe8c000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8c000 0x00 0x800 0x00>; + interrupts = <0x13>; + stream-connected-dma0 = <0xbe>; + dma = <0xb4>; + memattr = <0x8b>; + dma-width = <0x10>; + byte-align = <0x01>; + phandle = <0x1ad>; + }; + + asu_dma_dst@0xebe8c000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8c800 0x00 0x800 0x00>; + interrupts = <0x13>; + dma = <0xb4>; + memattr = <0x8b>; + dma-width = <0x10>; + is-dst = <0x01>; + byte-align = <0x01>; + phandle = <0xba>; + }; + + asu_dma1_src@0xebe8d000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8d000 0x00 0x800 0x00>; + interrupts = <0x13>; + stream-connected-dma1 = <0xbe>; + dma = <0xb4>; + memattr = <0x8c>; + dma-width = <0x10>; + byte-align = <0x01>; + phandle = <0x1ae>; + }; + + asu_dma1_dst@0xebe8d000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8d800 0x00 0x800 0x00>; + interrupts = <0x14>; + dma = <0xb4>; + memattr = <0x8c>; + dma-width = <0x10>; + is-dst = <0x01>; + byte-align = <0x01>; + phandle = <0xbd>; + }; + + asu_xmpu@0xebf60000 { + compatible = "xlnx,versal-xmpu"; + reg-extended = <0x51 0x00 0xebf60000 0x00 0x10000 0x00 0x51 0x00 +0xebe40000 0x00 0x20000 0x02>; + protected-mr = <0xbf>; + mr-0 = <0x0d>; + protected-base = <0xebe40000>; + phandle = <0x1af>; + }; + + asu_aes@0xebe88000 { + doc-status = "complete"; + compatible = "xlnx,asu-aes"; + reg = <0x00 0xebe88000 0x00 0x2000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + interrupts = <0x12 0x1a>; + keyvault = <0x94>; + stream-connected-aes = <0xbe>; + phandle = <0xb9>; + }; + + asu_kv@0xebe8a000 { + compatible = "xlnx,asu-kv"; + reg = <0x00 0xebe8a000 0x00 0x2000 0x00>; + pmxc-aes = <0x8f>; + aes-engine = <0xb9>; + phandle = <0x94>; + }; + + asu_sha3@0xebf40000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha3"; + reg = <0x00 0xebf40000 0x00 0x10000 0x00>; + interrupts = <0x15>; + phandle = <0xbc>; + }; + + asu_sha2@0xebf30000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha2"; + reg = <0x00 0xebf30000 0x00 0x10000 0x00>; + phandle = <0xbb>; + }; + + pmc_rsa@0xebf50000 { + doc-status = "complete"; + compatible = "xlnx,asu-ecdsa-rsa"; + reg = <0x00 0xebf50000 0x00 0x10000 0x00>; + interrupts = <0x17>; + phandle = <0x1b0>; + }; + + trng@0xebf20000 { + doc-status = "complete"; + compatible = "xlnx-asu-trng"; + reg = <0x00 0xebf10000 0x00 0x20000 0x00>; + interrupts = <0x18>; + phandle = <0x1b1>; + }; + + asu_ecc@0xebf00000 { + doc-status = "complete"; + compatible = "xlnx,asu_ecc"; + reg = <0x00 0xebf00000 0x00 0x10000 0x00>; + interrupts = <0x16>; + phandle = <0x1b2>; + }; + }; + }; + + lmb_pmc_ppu0@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU0"; + doc-status = "complete"; + phandle = <0xa1>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x74>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + pmc_rom@0xf0000000 { + reg = <0x00 0xf0000000 0x00 0x40000 0x01>; + compatible = "qemu:memory-region"; + container = <0xa1>; + qemu,ram = <0x01>; + read-only; + phandle = <0x1b3>; + }; + + ppu0_ram@0xf0060000 { + reg = <0x00 0xf0060000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + container = <0xa1>; + qemu,ram = <0x01>; + phandle = <0x1b4>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xa1>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1b5>; + + pmc_ppu0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xc0 0x00>; + reg = <0x00 0xf008000c 0x04 0x00 0xf0080030 0x10 0x00 +0xf0080080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x86>; + }; + + pmc_ppu0_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0b>; + reg = <0x00 0xf0080020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b6>; + }; + + pmc_ppu0_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0c>; + reg = <0x00 0xf0080024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b7>; + }; + + pmc_ppu0_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0d>; + reg = <0x00 0xf0080028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b8>; + }; + + pmc_ppu0_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0e>; + reg = <0x00 0xf008002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b9>; + }; + + pmc_ppu0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0xc1>; + }; + + pmc_ppu0_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1ba>; + }; + + pmc_ppu0_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1bb>; + }; + + pmc_ppu0_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf008001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1bc>; + }; + + pmc_ppu0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x03>; + reg = <0x00 0xf0080040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xc1 0x01 0xc2 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1bd>; + }; + + pmc_ppu0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x04>; + reg = <0x00 0xf0080050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc2>; + }; + + pmc_ppu0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x05>; + reg = <0x00 0xf0080060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xc1 0x06 0xc3 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1be>; + }; + + pmc_ppu0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x06>; + reg = <0x00 0xf0080070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc3>; + }; + }; + }; + + lmb_pmc_ppu1@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU1"; + doc-status = "complete"; + phandle = <0xc4>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x74>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xc4>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1bf>; + + pmc_ppu1_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xc5 0x00>; + reg = <0x00 0xf030000c 0x04 0x00 0xf0300030 0x10 0x00 +0xf0300080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x08>; + }; + + pmc_ppu1_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0b>; + reg = <0x00 0xf0300020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c0>; + }; + + pmc_ppu1_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0c>; + reg = <0x00 0xf0300024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c1>; + }; + + pmc_ppu1_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0d>; + reg = <0x00 0xf0300028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c2>; + }; + + pmc_ppu1_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0e>; + reg = <0x00 0xf030002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c3>; + }; + + pmc_ppu1_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0xc6>; + }; + + pmc_ppu1_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c4>; + }; + + pmc_ppu1_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c5>; + }; + + pmc_ppu1_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf030001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c6>; + }; + + pmc_ppu1_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x03>; + reg = <0x00 0xf0300040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0xc6 0x01 0xc7 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1c7>; + }; + + pmc_ppu1_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x04>; + reg = <0x00 0xf0300050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc7>; + }; + + pmc_ppu1_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x05>; + reg = <0x00 0xf0300060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0xc6 0x06 0xc8 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + windows-frequency = <0x13d620>; + phandle = <0x1c8>; + }; + + pmc_ppu1_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x06>; + reg = <0x00 0xf0300070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc8>; + }; + }; + }; + + lmb_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x1c9>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x14>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + lmb_ddrmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB DDRMC0"; + doc-status = "partial"; + phandle = <0xc9>; + + ddrmc0_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1ca>; + }; + + ddrmc0_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1cb>; + }; + + ddrmc0_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1cc>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "simple-bus"; + container = <0xc9>; + priority = <0xffffffff>; + phandle = <0x1cd>; + + ddrmc0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xca 0x00>; + reg = <0x00 0x1b00c 0x04 0x00 0x1b030 0x10 0x00 0x1b080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0xcb>; + }; + + ddrmc0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0x1b010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0xcc>; + }; + + ddrmc0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x03>; + reg = <0x00 0x1b040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xcc 0x01 0xcd 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1ce>; + }; + + ddrmc0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x04>; + reg = <0x00 0x1b050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xcd>; + }; + + ddrmc0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x05>; + reg = <0x00 0x1b060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xcc 0x06 0xce 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1cf>; + }; + + ddrmc0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x06>; + reg = <0x00 0x1b070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xce>; + }; + }; + + ddrmc_uart0@0 { + compatible = "xlnx,io_uart"; + reg = <0x00 0x1b000 0x0c 0x1b04c 0x04>; + xlnx,use-uart-rx = <0x01>; + xlnx,use-uart-tx = <0x01>; + chardev = "ddrmc-uart0\0serial1"; + phandle = <0x1d0>; + }; + + alias_npi_ddrmc_main { + compatible = "qemu:memory-region"; + alias = <0xcf>; + reg = <0x00 0x00 0x00 0x8000 0x00>; + }; + }; + + lmb_ddrmc@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x1d1>; + + ddrmc1_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d2>; + }; + + ddrmc1_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d3>; + }; + + ddrmc1_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d4>; + }; + }; + + amba_rpu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xd0>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + timer_a { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x02>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_b { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x03>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_c { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x04>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_d { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x05>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_e { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x06>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + }; + + amba_r5@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe3>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x35>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xd1>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + amba_r5@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe6>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x37>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xd1>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + dummy1@0 { + doc-ignore = <0x01>; + interrupt-controller; + #interrupt-cells = <0x01>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x96>; + }; + + tbu0_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x17>; + }; + + tbu1_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5c>; + }; + + tbu2_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5d>; + }; + + tbu3_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5e>; + }; + + tbu4_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5f>; + }; + + tbu5_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x60>; + }; + + tbu6_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x61>; + }; + + memory@00000000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x102>; + }; + + memory@8_0000_0000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x103>; + }; + + memory@0x50000000000ULL { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x1d5>; + }; + + ocm_mem_bank_0@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x100000 0x00 0x80000 0x00>; + phandle = <0x1d6>; + }; + + ocm_mem_bank_1@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x180000 0x00 0x80000 0x00>; + phandle = <0x1d7>; + }; + + ocm_mem_bank_2@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x80000 0x00>; + phandle = <0x1d8>; + }; + + ocm_mem_bank_3@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x80000 0x00 0x80000 0x00>; + phandle = <0x1d9>; + }; + + xram_mem@0xbbe00000 { + compatible = "qemu:memory-region"; + phandle = <0x1da>; + }; + + ipi_msgbuf@0 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0a>; + qemu,ram = <0x01>; + reg = <0x00 0xeb3f0000 0x00 0x1000 0x00>; + phandle = <0x1db>; + }; + + pmc_ram@0xf2000000 { + compatible = "qemu:memory-region"; + phandle = <0x73>; + }; + + pmc_ram_bank_0@0x0 { + compatible = "qemu:memory-region"; + container = <0x73>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + phandle = <0x1dc>; + }; + + pmc_ppu1_ram@0xf0200000 { + compatible = "qemu:memory-region"; + container = <0x0d>; + qemu,ram = <0x01>; + reg = <0x00 0xf0200000 0x00 0x80000 0x00>; + phandle = <0x1dd>; + }; + + pmc_ppu1_ram@0xf0280000 { + compatible = "qemu:memory-region"; + container = <0x0d>; + qemu,ram = <0x01>; + reg = <0x00 0xf0280000 0x00 0x20000 0x00>; + phandle = <0x1de>; + }; + + ppu0_mdm_uart@0xf0110000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0xa1 0x00 0xf0110000 0x00 0x10 0x01>; + chardev = "serial0"; + }; + + ppu1_mdm_uart@0xf0310000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0xc4 0x00 0xf0310000 0x00 0x10 0x01>; + chardev = "serial1"; + }; + + lqspi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x80>; + }; + + lospi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x82>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + apu_cpu@0 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x00>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 0"; + #interrupt-cells = <0x01>; + memattr_s = <0xd3>; + memattr_ns = <0xd4>; + reset-gpios = <0x52 0x00>; + gpios = <0x1b 0x40>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x00>; + mp-affinity = <0x1000000>; + generic-timer-frequency = <0x298100>; + phandle = <0x53>; + }; + + apu_cpu@1 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x01>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 1"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd5>; + memattr_ns = <0xd6>; + reset-gpios = <0x52 0x01>; + gpios = <0x1b 0x41>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x01>; + mp-affinity = <0x1000100>; + generic-timer-frequency = <0x298100>; + phandle = <0x54>; + }; + + apu_cpu@2 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x02>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 2"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd7>; + memattr_ns = <0xd8>; + reset-gpios = <0x52 0x04>; + gpios = <0x1b 0x42>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x02>; + mp-affinity = <0x1010000>; + generic-timer-frequency = <0x298100>; + phandle = <0x56>; + }; + + apu_cpu@3 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x03>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 3"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd9>; + memattr_ns = <0xda>; + reset-gpios = <0x52 0x05>; + gpios = <0x1b 0x43>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x03>; + mp-affinity = <0x1010100>; + generic-timer-frequency = <0x298100>; + phandle = <0x57>; + }; + + apu_cpu@4 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x04>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 4"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdb>; + memattr_ns = <0xdc>; + reset-gpios = <0x52 0x08>; + gpios = <0x1b 0x44>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x04>; + mp-affinity = <0x1020000>; + generic-timer-frequency = <0x298100>; + phandle = <0x58>; + }; + + apu_cpu@5 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x05>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 5"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdd>; + memattr_ns = <0xde>; + reset-gpios = <0x52 0x09>; + gpios = <0x1b 0x45>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x05>; + mp-affinity = <0x1020100>; + generic-timer-frequency = <0x298100>; + phandle = <0x59>; + }; + + apu_cpu@6 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x06>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 6"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdf>; + memattr_ns = <0xe0>; + reset-gpios = <0x52 0x0c>; + gpios = <0x1b 0x46>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x06>; + mp-affinity = <0x1030000>; + generic-timer-frequency = <0x298100>; + phandle = <0x5a>; + }; + + apu_cpu@7 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x07>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 7"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xe1>; + memattr_ns = <0xe2>; + reset-gpios = <0x52 0x0d>; + gpios = <0x1b 0x47>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x07>; + mp-affinity = <0x1030100>; + generic-timer-frequency = <0x298100>; + phandle = <0x5b>; + }; + + rpu_a@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1df>; + + rpu_cpu_a@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x00>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe3>; + qemu,halt = <0x01>; + memattr_ns = <0xe4>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a0"; + gpios = <0x1a 0x23 0xe5 0x00 0x1b 0x48>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x08>; + phandle = <0x2a>; + }; + + rpu_cpu_a@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x01>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe6>; + qemu,halt = <0x01>; + memattr_ns = <0xe7>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a1"; + gpios = <0x1a 0x24 0xe8 0x00 0x1b 0x49>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x09>; + phandle = <0x2b>; + }; + }; + + rpu_b@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e0>; + + rpu_cpu_b@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x100>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe9>; + qemu,halt = <0x01>; + memattr_ns = <0xea>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b0"; + gpios = <0x1a 0x25 0xeb 0x00 0x1b 0x4a>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0a>; + phandle = <0x2c>; + }; + + rpu_cpu_b@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x101>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xec>; + qemu,halt = <0x01>; + memattr_ns = <0xed>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b1"; + gpios = <0x1a 0x26 0xee 0x00 0x1b 0x4b>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0b>; + phandle = <0x2d>; + }; + }; + + rpu_c@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e1>; + + rpu_cpu_c@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x200>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xef>; + qemu,halt = <0x01>; + memattr_ns = <0xf0>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #c0"; + gpios = <0x1a 0x27 0xf1 0x00 0x1b 0x4c>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0c>; + phandle = <0x2e>; + }; + + rpu_cpu_c@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x201>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf2>; + qemu,halt = <0x01>; + memattr_ns = <0xf3>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #c1"; + gpios = <0x1a 0x28 0xf4 0x00 0x1b 0x4d>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0d>; + phandle = <0x2f>; + }; + }; + + rpu_d@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e2>; + + rpu_cpu_d@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x300>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf5>; + qemu,halt = <0x01>; + memattr_ns = <0xf6>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #d0"; + gpios = <0x1a 0x29 0xf7 0x00 0x1b 0x4e>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0e>; + phandle = <0x30>; + }; + + rpu_cpu_d@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x301>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf8>; + qemu,halt = <0x01>; + memattr_ns = <0xf9>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #d1"; + gpios = <0x1a 0x2a 0xfa 0x00 0x1b 0x4f>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0f>; + phandle = <0x31>; + }; + }; + + rpu_e@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e3>; + + rpu_cpu_e@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x400>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xfb>; + qemu,halt = <0x01>; + memattr_ns = <0xfc>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #e0"; + gpios = <0x1a 0x2b 0xfd 0x00 0x1b 0x50>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x10>; + phandle = <0x32>; + }; + + rpu_cpu_e@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x401>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xfe>; + qemu,halt = <0x01>; + memattr_ns = <0xff>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #e1"; + gpios = <0x1a 0x2c 0x100 0x00 0x1b 0x51>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x11>; + phandle = <0x33>; + }; + }; + }; + + amba_apu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xd2>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x01>; + interrupts = <0x1000001 0x0d 0xffffff01 0x1000001 0x0e 0xffffff01 0x1000001 +0x0b 0xffffff01 0x1000001 0x0a 0xffffff01>; + clock-frequency = <0x5f5e100>; + phandle = <0x1e4>; + }; + }; + + amba_apu_gic@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + container = <0x0b>; + priority = <0xffffffff>; + phandle = <0x1e5>; + + interrupt-controller@0xe2000000 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0xe2000000 0x00 0x10000 0x00 0x00 0xe2060000 +0x00 0x400000 0x00>; + interrupt-controller; + interrupts-extended = <0x53 0x00 0x54 0x00 0x56 0x00 0x57 0x00 0x58 0x00 +0x59 0x00 0x5a 0x00 0x5b 0x00 0x53 0x01 0x54 0x01 0x56 0x01 0x57 0x01 0x58 0x01 0x59 0x01 0x5a +0x01 0x5b 0x01 0x53 0x02 0x54 0x02 0x56 0x02 0x57 0x02 0x58 0x02 0x59 0x02 0x5a 0x02 0x5b 0x02 +0x53 0x03 0x54 0x03 0x56 0x03 0x57 0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b 0x03 0x01 0x01 0x09 +0x104 0x01 0x01 0x09 0x204 0x01 0x01 0x09 0x404 0x01 0x01 0x09 0x804 0x01 0x01 0x09 0x1004 +0x01 0x01 0x09 0x2004 0x01 0x01 0x09 0x4004 0x01 0x01 0x09 0x8004>; + num-cpu = <0x08>; + num-irq = <0x220>; + has-security-extensions = <0x01>; + redist-region-count = <0x08>; + has-lpi = <0x01>; + sysmem = <0x0d>; + phandle = <0x01>; + }; + + git_its@0xe2040000 { + compatible = "arm-gicv3-its"; + reg = <0x00 0xe2040000 0x00 0x20000 0x00>; + parent-gicv3 = <0x01>; + }; + }; + + lpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x0a>; + reset-gpios = <0x7e 0x07 0x7e 0x0a>; + }; + + fpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x0b>; + reset-gpios = <0x7e 0x07 0x7e 0x0a 0x1a 0x1c 0x1a 0x1d>; + }; + + amba_alias@0 { + compatible = "qemu:memory-region"; + container = <0x101>; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x01>; + phandle = <0x1e6>; + }; + + qemu_sysmem@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:system-memory"; + phandle = <0x101>; + }; + + dummy_ppu0@0 { + #interrupt-cells = <0x01>; + phandle = <0xc0>; + }; + + dummy_ppu1@0 { + #interrupt-cells = <0x01>; + phandle = <0xc5>; + }; + + dummy_ddrmc0@0 { + #interrupt-cells = <0x01>; + phandle = <0xca>; + }; + + dummy_ddrmc1@0 { + #interrupt-cells = <0x01>; + phandle = <0x1e7>; + }; + + ddr@0x00000000 { + compatible = "qemu:memory-region"; + container = <0x102>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x80000000 0x00>; + phandle = <0xa2>; + }; + + ddr_2@0x800000000ULL { + compatible = "qemu:memory-region-spec"; + container = <0x103>; + qemu,ram = <0x01>; + reg = <0x08 0x00 0x08 0x00 0x00>; + phandle = <0x1e8>; + }; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "mdio"; + phandle = <0x1c>; + + phy@1 { + compatible = "dp83867"; + device_type = "ethernet-phy"; + reg = <0x01>; + phandle = <0x1e9>; + }; + + phy@2 { + compatible = "88e1118r"; + device_type = "ethernet-phy"; + reg = <0x02>; + phandle = <0x1ea>; + }; + }; + + cpu_dummy { + phandle = <0x55>; + }; + + tbu7_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x62>; + }; + + tbu8_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x63>; + }; + + tbu9_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x64>; + }; + + tbu10_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x65>; + }; + + tbu11_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x66>; + }; + + tbu12_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x67>; + }; + + mr_rpu_gic_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0xd1>; + + rpu_gic_a@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2a 0x00 0x2b 0x00 0x2a 0x01 0x2b 0x01 0x2a 0x02 +0x2b 0x02 0x2a 0x03 0x2b 0x03 0x02 0x01 0x09 0x104 0x02 0x01 0x09 0x204>; + first-cpu-idx = <0x08>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x02>; + }; + }; + + mr_rpu_gic_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x104>; + + rpu_gic_b@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2c 0x00 0x2d 0x00 0x2c 0x01 0x2d 0x01 0x2c 0x02 +0x2d 0x02 0x2c 0x03 0x2d 0x03 0x03 0x01 0x09 0x104 0x03 0x01 0x09 0x204>; + first-cpu-idx = <0x0a>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x03>; + }; + }; + + mr_rpu_gic_c@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x105>; + + rpu_gic_c@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2e 0x00 0x2f 0x00 0x2e 0x01 0x2f 0x01 0x2e 0x02 +0x2f 0x02 0x2e 0x03 0x2f 0x03 0x04 0x01 0x09 0x104 0x04 0x01 0x09 0x204>; + first-cpu-idx = <0x0c>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x04>; + }; + }; + + mr_rpu_gic_d@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x106>; + + rpu_gic_d@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x30 0x00 0x31 0x00 0x30 0x01 0x31 0x01 0x30 0x02 +0x31 0x02 0x30 0x03 0x31 0x03 0x05 0x01 0x09 0x104 0x05 0x01 0x09 0x204>; + first-cpu-idx = <0x0e>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x05>; + }; + }; + + mr_rpu_gic_e@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x107>; + + rpu_gic_e@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x32 0x00 0x33 0x00 0x32 0x01 0x33 0x01 0x32 0x02 +0x33 0x02 0x32 0x03 0x33 0x03 0x06 0x01 0x09 0x104 0x06 0x01 0x09 0x204>; + first-cpu-idx = <0x10>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x06>; + }; + }; + + tcm_core@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x35>; + + atcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1eb>; + }; + + btcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1ec>; + }; + + ctcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1ed>; + }; + }; + + tcm_core@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x37>; + + atcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1ee>; + }; + + btcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1ef>; + }; + + ctcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f0>; + }; + }; + + tcm_core@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x39>; + + atcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f1>; + }; + + btcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f2>; + }; + + ctcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f3>; + }; + }; + + tcm_core@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3b>; + + atcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f4>; + }; + + btcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f5>; + }; + + ctcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f6>; + }; + }; + + tcm_core@4 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3d>; + + atcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f7>; + }; + + btcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f8>; + }; + + ctcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f9>; + }; + }; + + tcm_core@5 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3f>; + + atcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1fa>; + }; + + btcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1fb>; + }; + + ctcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1fc>; + }; + }; + + tcm_core@6 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x41>; + + atcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1fd>; + }; + + btcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1fe>; + }; + + ctcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1ff>; + }; + }; + + tcm_core@7 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x43>; + + atcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x200>; + }; + + btcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x201>; + }; + + ctcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x202>; + }; + }; + + tcm_core@8 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x45>; + + atcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x203>; + }; + + btcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x204>; + }; + + ctcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x205>; + }; + }; + + tcm_core@9 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x47>; + + atcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x206>; + }; + + btcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x207>; + }; + + ctcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x208>; + }; + }; + + tcm_cluster_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x0f>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x35>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x37>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x10>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x39>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x3b>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_c@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x11>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x3d>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x3f>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_d@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x12>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x41>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x43>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_e@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x13>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x45>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x47>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + amba_r5@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe9>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x39>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0x104>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xec>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3b>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0x104>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@4 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xef>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3d>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic2 { + compatible = "qemu:memory-region"; + alias = <0x105>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@5 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf2>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3f>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic2 { + compatible = "qemu:memory-region"; + alias = <0x105>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@6 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf5>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x41>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic3 { + compatible = "qemu:memory-region"; + alias = <0x106>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@7 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf8>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x43>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic3 { + compatible = "qemu:memory-region"; + alias = <0x106>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@8 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xfb>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x45>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic4 { + compatible = "qemu:memory-region"; + alias = <0x107>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@9 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xfe>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x47>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic4 { + compatible = "qemu:memory-region"; + alias = <0x107>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + rpu2_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xea>; + }; + + rpu3_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xed>; + }; + + rpu4_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xf0>; + }; + + rpu5_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xf3>; + }; + + rpu6_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xf6>; + }; + + rpu7_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xf9>; + }; + + rpu8_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xfc>; + }; + + rpu9_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xff>; + }; + + usb1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x231>; + phandle = <0x48>; + }; + + apu2_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x262>; + phandle = <0xd7>; + }; + + apu2_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x262>; + phandle = <0xd8>; + }; + + apu3_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x263>; + phandle = <0xd9>; + }; + + apu3_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x263>; + phandle = <0xda>; + }; + + apu4_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x268>; + phandle = <0xdb>; + }; + + apu4_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x268>; + phandle = <0xdc>; + }; + + apu5_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x269>; + phandle = <0xdd>; + }; + + apu5_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x269>; + phandle = <0xde>; + }; + + apu6_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x26a>; + phandle = <0xdf>; + }; + + apu6_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x26a>; + phandle = <0xe0>; + }; + + apu7_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x26b>; + phandle = <0xe1>; + }; + + apu7_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x26b>; + phandle = <0xe2>; + }; + + apu8_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x270>; + phandle = <0x209>; + }; + + apu8_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x270>; + phandle = <0x20a>; + }; + + apu9_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x271>; + phandle = <0x20b>; + }; + + apu9_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x271>; + phandle = <0x20c>; + }; + + apu10_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x272>; + phandle = <0x20d>; + }; + + apu10_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x272>; + phandle = <0x20e>; + }; + + apu11_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x273>; + phandle = <0x20f>; + }; + + apu11_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x273>; + phandle = <0x210>; + }; + + apu12_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x278>; + phandle = <0x211>; + }; + + apu12_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x278>; + phandle = <0x212>; + }; + + apu13_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x279>; + phandle = <0x213>; + }; + + apu13_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x279>; + phandle = <0x214>; + }; + + apu14_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x27a>; + phandle = <0x215>; + }; + + apu14_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x27a>; + phandle = <0x216>; + }; + + apu15_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x27b>; + phandle = <0x217>; + }; + + apu15_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x27b>; + phandle = <0x218>; + }; + + apu16_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x280>; + phandle = <0x219>; + }; + + apu16_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x280>; + phandle = <0x21a>; + }; + + apu17_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x281>; + phandle = <0x21b>; + }; + + apu17_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x281>; + phandle = <0x21c>; + }; + + apu18_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x282>; + phandle = <0x21d>; + }; + + apu18_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x282>; + phandle = <0x21e>; + }; + + apu19_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x283>; + phandle = <0x21f>; + }; + + apu19_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x283>; + phandle = <0x220>; + }; + + apu20_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x288>; + phandle = <0x221>; + }; + + apu20_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x288>; + phandle = <0x222>; + }; + + apu21_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x289>; + phandle = <0x223>; + }; + + apu21_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x289>; + phandle = <0x224>; + }; + + apu22_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x28a>; + phandle = <0x225>; + }; + + apu22_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x28a>; + phandle = <0x226>; + }; + + apu23_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x28b>; + phandle = <0x227>; + }; + + apu23_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x28b>; + phandle = <0x228>; + }; + + apu24_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x290>; + phandle = <0x229>; + }; + + apu24_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x290>; + phandle = <0x22a>; + }; + + apu25_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x291>; + phandle = <0x22b>; + }; + + apu25_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x291>; + phandle = <0x22c>; + }; + + apu26_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x292>; + phandle = <0x22d>; + }; + + apu26_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x292>; + phandle = <0x22e>; + }; + + apu27_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x293>; + phandle = <0x22f>; + }; + + apu27_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x293>; + phandle = <0x230>; + }; + + apu28_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x298>; + phandle = <0x231>; + }; + + apu28_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x298>; + phandle = <0x232>; + }; + + apu29_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x299>; + phandle = <0x233>; + }; + + apu29_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x299>; + phandle = <0x234>; + }; + + apu30_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x29a>; + phandle = <0x235>; + }; + + apu30_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x29a>; + phandle = <0x236>; + }; + + apu31_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x29b>; + phandle = <0x237>; + }; + + apu31_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x29b>; + phandle = <0x238>; + }; + + asu_cpu_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x00>; + phandle = <0x239>; + }; + + lmb_amba_asu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x23a>; + + main_bus_for_asu { + compatible = "qemu:memory-region"; + alias = <0xb4>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + ocm_mem@0xbbe00000 { + compatible = "qemu:memory-region"; + phandle = <0x0e>; + }; + + asu_data_ram_wrapper@0xebe40000 { + compatible = "qemu:memory-region"; + phandle = <0xbf>; + + asu_data_ram@0 { + compatible = "qemu:memory-region"; + device_type = "memory"; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + }; + }; + + psm_gic_proxy@0 { + #interrupt-cells = <0x03>; + interrupt-controller; + phandle = <0x23b>; + }; + + asu_cpu@0 { + #interrupt-cells = <0x01>; + phandle = <0xb5>; + }; + + __symbols__ { + pmc_ppu0_memattr = "/pmc_ppu0_ma"; + pmc_ppu1_memattr = "/pmc_ppu1_ma"; + psm_memattr = "/psm_ma"; + ddrmc_ub0_memattr = "/ddrmc_ub0_ma"; + ddrmc_ub1_memattr = "/ddrmc_ub1_ma"; + pmc_dma0_memattr = "/pmc_dma0_ma"; + pmc_dma1_memattr = "/pmc_dma1_ma"; + pmc_qspi_dma_memattr_smid = "/pmc_qspi_dma_ma_smid"; + pmc_qspi_dma_w_memattr_smid = "/pmc_qspi_dma_w_ma_smid"; + apu0_s_memattr = "/apu0_s_ma"; + apu0_ns_memattr = "/apu0_ns_ma"; + apu1_s_memattr = "/apu1_s_ma"; + apu1_ns_memattr = "/apu1_ns_ma"; + rpu0_s_memattr = "/rpu0_s_ma"; + rpu1_s_memattr = "/rpu1_s_ma"; + gem0_memattr_smid = "/gem0_ma_smid"; + gem0_w_memattr_smid = "/gem0_w_ma_smid"; + gem1_memattr_smid = "/gem1_ma_smid"; + gem1_w_memattr_smid = "/gem1_w_ma_smid"; + ospi_dma_memattr_smid = "/ospi_dma_ma_smid"; + ospi_dma_w_memattr_smid = "/ospi_dma_w_ma_smid"; + sd0_memattr_smid = "/sd0_ma_smid"; + sd0_w_memattr_smid = "/sd0_w_ma_smid"; + sd1_memattr_smid = "/sd1_ma_smid"; + sd1_w_memattr_smid = "/sd1_w_ma_smid"; + usb0_memattr = "/usb0_ma"; + amba_root = "/amba_root@0"; + amba = "/amba_root@0/amba@0"; + xmpu_ocm = "/amba_root@0/amba@0/xmpu_ocm@0"; + xmpu_ocm2 = "/amba_root@0/amba@0/xmpu_ocm2@0"; + loader_write_0xF1110880 = "/amba_root@0/amba@0/loader_write_cpu0_0x1@0xF1110880"; + loader_write_0xFD1A0050 = "/amba_root@0/amba@0/loader_write_cpu0_0x5@0xFD1A0050"; + loader_write_0xF111010C = "/amba_root@0/amba@0/loader_write_cpu0_0xFF@0xF111010C"; + s_axi_tcm_a = "/amba_root@0/amba@0/s_axi_tcm_a@0"; + s_axi_tcm_b = "/amba_root@0/amba@0/s_axi_tcm_b@0"; + s_axi_tcm_c = "/amba_root@0/amba@0/s_axi_tcm_c@0"; + s_axi_tcm_d = "/amba_root@0/amba@0/s_axi_tcm_d@0"; + s_axi_tcm_e = "/amba_root@0/amba@0/s_axi_tcm_e@0"; + loader_write_0xF12B0100 = "/amba_root@0/amba@0/loader_write_cpu0_0x80C@0xF12B0100"; + loader_write_0xF1260320 = "/amba_root@0/amba@0/loader_write_cpu0_0x77@0xF1260320"; + xmpu_ocm1 = "/amba_root@0/amba@0/xmpu_ocm1@0"; + xmpu_ocm3 = "/amba_root@0/amba@0/xmpu_ocm3@0"; + amba_lpd = "/amba_root@0/amba_lpd@0"; + xppu_lpd = "/amba_root@0/amba_lpd@0/xppu_lpd@0xeb990000"; + gem0 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a60000"; + gem1 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a70000"; + serial0 = "/amba_root@0/amba_lpd@0/serial@0xf1920000"; + serial1 = "/amba_root@0/amba_lpd@0/serial@0xf1930000"; + canfdbus0 = "/amba_root@0/amba_lpd@0/canfdbus@0"; + can0 = "/amba_root@0/amba_lpd@0/can@0xf19e0000"; + can1 = "/amba_root@0/amba_lpd@0/can@0xf19f0000"; + crl = "/amba_root@0/amba_lpd@0/crl@0xeb5e0000"; + lpd_iou_slcr = "/amba_root@0/amba_lpd@0/slcr@0xf1a20000"; + ipi = "/amba_root@0/amba_lpd@0/ipi@0xeb300000"; + spi0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000"; + spi0_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000/spi0_flash0@0"; + spi1 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000"; + spi1_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000/spi1_flash0@0"; + dwc3_0 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI"; + ttc0 = "/amba_root@0/amba_lpd@0/timer@0xf1e60000"; + ttc1 = "/amba_root@0/amba_lpd@0/timer@0xf1e70000"; + ttc2 = "/amba_root@0/amba_lpd@0/timer@0xf1e80000"; + ttc3 = "/amba_root@0/amba_lpd@0/timer@0xf1e90000"; + adma0_mattr = "/amba_root@0/amba_lpd@0/adma0mattr"; + adma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd00000"; + adma1_mattr = "/amba_root@0/amba_lpd@0/adma1mattr"; + adma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd10000"; + adma2_mattr = "/amba_root@0/amba_lpd@0/adma2mattr"; + adma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd20000"; + adma3_mattr = "/amba_root@0/amba_lpd@0/adma3mattr"; + adma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd30000"; + adma4_mattr = "/amba_root@0/amba_lpd@0/adma4mattr"; + adma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd40000"; + adma5_mattr = "/amba_root@0/amba_lpd@0/adma5mattr"; + adma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd50000"; + adma6_mattr = "/amba_root@0/amba_lpd@0/adma6mattr"; + adma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd60000"; + adma7_mattr = "/amba_root@0/amba_lpd@0/adma7mattr"; + adma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd70000"; + ps_i2c0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1940000"; + ps_i2c1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1950000"; + ps_i2c2 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1960000"; + ps_i2c3 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1970000"; + ps_i2c4 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1980000"; + ps_i2c5 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1990000"; + ps_i2c6 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19a0000"; + ps_i2c7 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19b0000"; + ocm_ctrl0 = "/amba_root@0/amba_lpd@0/ocm_ctrl@OCM"; + lpd_slcr = "/amba_root@0/amba_lpd@0/lpd_slcr@0xeb410000"; + lpd_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_slcr_secure@0xeb510000"; + lpd_iou_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_iou_slcr_secure@0xf1a40000"; + lpd_wwdt0 = "/amba_root@0/amba_lpd@0/wwdt@0xeb000000"; + lpd_gpio = "/amba_root@0/amba_lpd@0/lpd_gpio@0xf1a50000"; + rpu_ctrl = "/amba_root@0/amba_lpd@0/rpu_ctrl@0"; + rpu_ctrl_a = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb580000"; + rpu_ctrl_a0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a0@0xeb588000"; + rpu_ctrl_a1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a1@0xeb58c000"; + rpu_ctrl_b = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb590000"; + rpu_ctrl_b0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b0@0xeb598000"; + rpu_ctrl_b1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b1@0xeb59c000"; + rpu_ctrl_c = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5a0000"; + rpu_ctrl_c0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c0@0xeb5a8000"; + rpu_ctrl_c1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c1@0xeb5ac000"; + rpu_ctrl_d = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5b0000"; + rpu_ctrl_d0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d0@0xeb5b8000"; + rpu_ctrl_d1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d1@0xeb5bc000"; + rpu_ctrl_e = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5c0000"; + rpu_ctrl_e0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e0@0xeb5c8000"; + rpu_ctrl_e1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e1@0xeb5cc000"; + dwc3_1 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI1"; + psx_i3c0 = "/amba_root@0/amba_lpd@0/i3c0@0xf1940000"; + psx_i3c1 = "/amba_root@0/amba_lpd@0/i3c1@0xf1950000"; + ocm_ctrl1 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb960000"; + ocm_ctrl2 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb9d0000"; + ocm_ctrl3 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeaa00000"; + can2 = "/amba_root@0/amba_lpd@0/can@0xf1a00000"; + can3 = "/amba_root@0/amba_lpd@0/can@0xf1a10000"; + ttc4 = "/amba_root@0/amba_lpd@0/timer@0xf1ea0000"; + ttc5 = "/amba_root@0/amba_lpd@0/timer@0xf1eb0000"; + ttc6 = "/amba_root@0/amba_lpd@0/timer@0xf1ec0000"; + ttc7 = "/amba_root@0/amba_lpd@0/timer@0xf1ed0000"; + sdma0_mattr = "/amba_root@0/amba_lpd@0/sdma0mattr"; + sdma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd80000"; + sdma1_mattr = "/amba_root@0/amba_lpd@0/sdma1mattr"; + sdma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd90000"; + sdma2_mattr = "/amba_root@0/amba_lpd@0/sdma2mattr"; + sdma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebda0000"; + sdma3_mattr = "/amba_root@0/amba_lpd@0/sdma3mattr"; + sdma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdb0000"; + sdma4_mattr = "/amba_root@0/amba_lpd@0/sdma4mattr"; + sdma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdc0000"; + sdma5_mattr = "/amba_root@0/amba_lpd@0/sdma5mattr"; + sdma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdd0000"; + sdma6_mattr = "/amba_root@0/amba_lpd@0/sdma6mattr"; + sdma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebde0000"; + sdma7_mattr = "/amba_root@0/amba_lpd@0/sdma7mattr"; + sdma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdf0000"; + lpd_wwdt1 = "/amba_root@0/amba_lpd@0/wwdt@0xeb010000"; + lpd_afi_fs = "/amba_root@0/amba_lpd@0/lpd_afi_fs@0xeb560000"; + amba_fpd = "/amba_root@0/amba_fpd@0"; + wwdt0 = "/amba_root@0/amba_fpd@0/watchdog@0xecc10000"; + apu_cluster0 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecc00000"; + apu_cluster1 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecd00000"; + apu_cluster2 = "/amba_root@0/amba_fpd@0/apu_cluster@0xece00000"; + apu_cluster3 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecf00000"; + smmu = "/amba_root@0/amba_fpd@0/smmuv3@MM_FPD_SMMU"; + pcie = "/amba_root@0/amba_fpd@0/dummy_pcie@0x6_0000_0000"; + apu_pcil = "/amba_root@0/amba_fpd@0/apu_pcil@0xecb10000"; + fpd_afi_fs = "/amba_root@0/amba_fpd@0/lpd_afi_fs@0xec860000"; + mmi_gem_memattr = "/amba_root@0/amba_fpd@0/mmi_gem_ma"; + mmi_usb_memattr = "/amba_root@0/amba_fpd@0/mmi_usb_ma"; + amba_mmi = "/amba_root@0/amba_fpd@0/amba_mmi@0"; + mdio_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0"; + phy_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0/phy@1"; + mmi_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/ethernet@0xed920000"; + mmi_usb_drd = "/amba_root@0/amba_fpd@0/amba_mmi@0/usb_drd@0xedec0000"; + mmi_crx = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_crs@0xedc00000"; + mmi_pcsr = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_pcsr@0xeb2f0000"; + mmi_gtyp = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gtyp@0xed900000"; + mmi_slcr_secure = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_slcr_sec@0"; + mmi_trng = "/amba_root@0/amba_fpd@0/amba_mmi@0/trng@0xede80000"; + mmi_udh_slcr = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_slcr@0xedea0000"; + mmi_udh_pll = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_pll@0xede90000"; + mmi_gpu_a = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gpu_a@0"; + loader_write_0xEDC30440 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30440"; + loader_write_0xEDC30444 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x7F@0xEDC30444"; + loader_write_0xEDC3044c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC3044c"; + loader_write_0xEDC30450 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30450"; + loader_write_0xEDC30460 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30460"; + loader_write_0xEDC30464 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x7f@0xEDC30464"; + loader_write_0xEDC3046c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC3046c"; + loader_write_0xEDC30470 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30470"; + loader_write_0xED0A0098 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x3@0xED0A0098"; + amba_pmc_internal = "/amba_root@0/amba_pmc_internal@0"; + xmpu_pmc = "/amba_root@0/amba_pmc_internal@0/xmpu_pmc@0"; + xppu_pmc_npi = "/amba_root@0/amba_pmc_internal@0/xppu_pmc_npi@0xf1300000"; + xppu_pmc = "/amba_root@0/amba_pmc_internal@0/xppu_pmc@0xf1310000"; + amba_pmc = "/amba_root@0/amba_pmc@0"; + xmpu_pmc_cfu = "/amba_root@0/amba_pmc@0/xmpu_pmc_cfu@0xf1340000"; + pmx_err_mng = "/amba_root@0/amba_pmc@0/pmx_err_mng@0xf1110000"; + intpmxc_config = "/amba_root@0/amba_pmc@0/intpmxc_config@0xf1400000"; + amba_pmc_iou = "/amba_root@0/amba_pmc_iou@0"; + pmc_iou_slcr = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr@0xf1060000"; + pmc_iou_slcr_secure = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr_secure@0xf1070000"; + pmc_qspi_dma_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi_dma@QSPI_DMA"; + pmc_qspi_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000"; + qspi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_lcs_lb@0"; + qspi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_lcs_ub@0"; + qspi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_ucs_lb@0"; + qspi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_ucs_ub@0"; + ospi_dma_dst = "/amba_root@0/amba_pmc_iou@0/ospi_dst_dma@0"; + ospi_dma_src = "/amba_root@0/amba_pmc_iou@0/ospi_src_dma@0"; + ospi = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000"; + ospi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_lcs_lb@0"; + ospi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_lcs_ub@0"; + ospi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_ucs_lb@0"; + ospi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_ucs_ub@0"; + gpio_mr_mux = "/amba_root@0/amba_pmc_iou@0/gpio_mr_mux@0xc0000000"; + pmc_gpio = "/amba_root@0/amba_pmc_iou@0/pmc_gpio@0xf1020000"; + sdhci0 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1040000"; + sdhci1 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1050000"; + pmc_tap = "/amba_root@0/amba_pmc_iou@0/pmc_tap@0xf11a0000"; + pmc_i2c = "/amba_root@0/amba_pmc_iou@0/pmc_i2c_wrapper/pmc_i2c@0xf1000000"; + pmx_wwdt = "/amba_root@0/amba_pmc_iou@0/wwdt@0xf03f0000"; + pmc_ufshc = "/amba_root@0/amba_pmc_iou@0/pmc_ufshc@0xf10b0000"; + unipro = "/amba_root@0/amba_pmc_iou@0/unipro@0"; + ufs_dev = "/amba_root@0/amba_pmc_iou@0/ufs_dev@0"; + ufs_reg = "/amba_root@0/amba_pmc_iou@0/ufs_reg@0xf1060000"; + amba_pmc_sec = "/amba_root@0/amba_pmc_sec@0"; + pmc_dma0_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_src@0"; + pmc_dma0_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_dst@0"; + pmc_dma1_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_src@0"; + pmc_dma1_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_dst@0"; + pmc_stream_switch = "/amba_root@0/amba_pmc_sec@0/pmc_stream_switch@0"; + pmc_sha3 = "/amba_root@0/amba_pmc_sec@0/pmc_sha@0xf1210000"; + pmc_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000"; + xlnx_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000/xlnx_aes@0"; + pmc_rsa = "/amba_root@0/amba_pmc_sec@0/pmc_rsa@0xf1200000"; + xlnx_pmc_efuse_cache = "/amba_root@0/amba_pmc_sec@0/ +xlnx_pmc_efuse_cache@0xf1250000"; + pmc_puf_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_puf_ctrl@0"; + pmc_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000"; + xlnx_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000/xlnx_efuse@0"; + pmc_bbram_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_bbram@0xf11f0000"; + pmc_sbi = "/amba_root@0/amba_pmc_sec@0/pmc_sbi@0xf1220000"; + pmc_sha3_1 = "/amba_root@0/amba_pmc_sec@0/pmc_sha1@0xF1800000"; + amba_pmc_ppu = "/amba_root@0/amba_pmc_ppu@0"; + pmc_gic_proxy = "/amba_root@0/amba_pmc_ppu@0/pmc_gic_proxy@0"; + amba_pmc_sys = "/amba_root@0/amba_pmc_sys@0"; + pmc_clk_rst = "/amba_root@0/amba_pmc_sys@0/pmc_clk_rst@0xf1260000"; + pmc_int = "/amba_root@0/amba_pmc_sys@0/pmc_int@0xf1400000"; + pmc_global = "/amba_root@0/amba_pmc_sys@0/pmc_global@0xf1110000"; + pmc_stream_zero = "/amba_root@0/amba_pmc_sys@0/pmc_stream_zero@"; + pmx_analog = "/amba_root@0/amba_pmc_sys@0/pmc_analog@0xf1160000"; + pmc_sysmon = "/amba_root@0/amba_pmc_sys@0/pmc_sysmon@0xf1270000"; + pmc_ams_sat0 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@0"; + pmc_ams_sat1 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@1"; + pmc_global_tamper = "/amba_root@0/amba_pmc_sys@0/versal_pmc_tamper@"; + lpd_sysmon_sat = "/amba_root@0/amba_pmc_sys@0/lpd_ams_sat@0"; + fpd_sysmon_sat0 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@0"; + fpd_sysmon_sat1 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@1"; + fpd_sysmon_sat2 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@2"; + fpd_sysmon_sat3 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@3"; + amba_pmc_pl = "/amba_root@0/amba_pmc_pl@0"; + noc_npi_nir = "/amba_root@0/amba_pmc_pl@0/noc_npi_nir@0xf6000000"; + npi_ddrmc_ub0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub0@0xf62c0000"; + npi_ddrmc_main0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main0@0xf6290000"; + npi_ddrmc_noc0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc0@0xf62a0000"; + npi_ddrmc_ub1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub1@0xf63b0000"; + npi_ddrmc_main1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main1@0xf6380000"; + npi_ddrmc_noc1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc1@0xf6390000"; + npi_ddrmc_ub2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub2@0xf6940000"; + npi_ddrmc_main2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main2@0xf6910000"; + npi_ddrmc_noc2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc2@0xf6920000"; + npi_ddrmc_ub3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub3@0xf6a20000"; + npi_ddrmc_main3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main3@0xf69f0000"; + npi_ddrmc_noc3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc3@0xf6a00000"; + npi_ddrmc_xmpu0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_xmpu0@0xf62a0000"; + npi_me = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; + npi_me0 = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; + noc_npi_devs = "/amba_root@0/amba_pmc_pl@0/noc_npi_devs@0"; + cfu_fdro = "/amba_root@0/amba_pmc_pl@0/cfu_fdro@0xf12c2000"; + cfu_sfr = "/amba_root@0/amba_pmc_pl@0/cfu_sfr@0xf12c1000"; + cframe0_reg = "/amba_root@0/amba_pmc_pl@0/cframe0_reg@0xf12d0000"; + cframe1_reg = "/amba_root@0/amba_pmc_pl@0/cframe1_reg@0xf12d2000"; + cframe2_reg = "/amba_root@0/amba_pmc_pl@0/cframe2_reg@0xf12d4000"; + cframe3_reg = "/amba_root@0/amba_pmc_pl@0/cframe3_reg@0xf12d6000"; + cframe4_reg = "/amba_root@0/amba_pmc_pl@0/cframe4_reg@0xf12d8000"; + cframe5_reg = "/amba_root@0/amba_pmc_pl@0/cframe5_reg@0xf12da000"; + cframe6_reg = "/amba_root@0/amba_pmc_pl@0/cframe6_reg@0xf12dc000"; + cframe7_reg = "/amba_root@0/amba_pmc_pl@0/cframe7_reg@0xf12de000"; + cframe8_reg = "/amba_root@0/amba_pmc_pl@0/cframe8_reg@0xf12e0000"; + cframe9_reg = "/amba_root@0/amba_pmc_pl@0/cframe9_reg@0xf12e2000"; + cframe10_reg = "/amba_root@0/amba_pmc_pl@0/cframe10_reg@0xf12e4000"; + cframe11_reg = "/amba_root@0/amba_pmc_pl@0/cframe11_reg@0xf12e6000"; + cframe12_reg = "/amba_root@0/amba_pmc_pl@0/cframe12_reg@0xf12e8000"; + cframe13_reg = "/amba_root@0/amba_pmc_pl@0/cframe13_reg@0xf12ea000"; + cframe14_reg = "/amba_root@0/amba_pmc_pl@0/cframe14_reg@0xf12ec000"; + cframe_bcast_reg = "/amba_root@0/amba_pmc_pl@0/cframe_bcast_reg@0xf12ee000"; + dummy_cfu_mem = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000"; + cfu = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000/cfu@0x0"; + amba_pmc_bat = "/amba_root@0/amba_pmc_bat@0"; + rtc = "/amba_root@0/amba_pmc_bat@0/rtc@0xf12a0000"; + amba_psm = "/amba_root@0/amba_psm@0"; + amba_xram = "/amba_root@0/amba_xram@0"; + crf = "/amba_root@0/crf@0xec200000"; + amba_asu_cpu = "/amba_root@0/amba_asu_cpu@0"; + amba_asu = "/amba_root@0/amba_asu@0"; + asu_iram = "/amba_root@0/amba_asu@0/asu_instr_ram@0xebe00000"; + asu_io_module = "/amba_root@0/amba_asu@0/io-module@0xebe80000"; + asu_io_intc = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_io_intc@0C"; + asu_io_gpi1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpi@20"; + asu_io_gpo1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@10"; + asu_io_gpo2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@14"; + asu_io_pit1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@40"; + asu_io_pit2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@50"; + asu_io_pit3 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@60"; + asu_io_pit4 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@70"; + asu_mdm_uart = "/amba_root@0/amba_asu@0/asu_mdm_uart@0xebef0000"; + asu_global = "/amba_root@0/amba_asu@0/asu_global@0xebf80000"; + asu_global_pmc = "/amba_root@0/amba_asu@0/asu_global_pmc@0xebf80000"; + asu_local = "/amba_root@0/amba_asu@0/asu_local@0xebe8e000"; + asu_sss = "/amba_root@0/amba_asu@0/asu_sss@0xebe8e000"; + asu_dma_src = "/amba_root@0/amba_asu@0/asu_dma_src@0xebe8c000"; + asu_dma_dst = "/amba_root@0/amba_asu@0/asu_dma_dst@0xebe8c000"; + asu_dma1_src = "/amba_root@0/amba_asu@0/asu_dma1_src@0xebe8d000"; + asu_dma1_dst = "/amba_root@0/amba_asu@0/asu_dma1_dst@0xebe8d000"; + asu_xmpu = "/amba_root@0/amba_asu@0/asu_xmpu@0xebf60000"; + asu_aes = "/amba_root@0/amba_asu@0/asu_aes@0xebe88000"; + asu_kv = "/amba_root@0/amba_asu@0/asu_kv@0xebe8a000"; + asu_sha3 = "/amba_root@0/amba_asu@0/asu_sha3@0xebf40000"; + asu_sha2 = "/amba_root@0/amba_asu@0/asu_sha2@0xebf30000"; + asu_rsa = "/amba_root@0/amba_asu@0/pmc_rsa@0xebf50000"; + asu_trng = "/amba_root@0/amba_asu@0/trng@0xebf20000"; + asu_ecc = "/amba_root@0/amba_asu@0/asu_ecc@0xebf00000"; + lmb_pmc_ppu0 = "/lmb_pmc_ppu0@0"; + pmc_rom = "/lmb_pmc_ppu0@0/pmc_rom@0xf0000000"; + pmc_ppu0_ram = "/lmb_pmc_ppu0@0/ppu0_ram@0xf0060000"; + pmc_ppu0_io_module = "/lmb_pmc_ppu0@0/io-module@00"; + pmc_ppu0_io_intc = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_intc@0C"; + pmc_ppu0_io_gpi1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@20"; + pmc_ppu0_io_gpi2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@24"; + pmc_ppu0_io_gpi3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@28"; + pmc_ppu0_io_gpi4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@2c"; + pmc_ppu0_io_gpo1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@10"; + pmc_ppu0_io_gpo2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@14"; + pmc_ppu0_io_gpo3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@18"; + pmc_ppu0_io_gpo4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@1c"; + pmc_ppu0_io_pit1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@40"; + pmc_ppu0_io_pit2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@50"; + pmc_ppu0_io_pit3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@60"; + pmc_ppu0_io_pit4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@70"; + lmb_pmc_ppu1 = "/lmb_pmc_ppu1@0"; + pmc_ppu1_io_module = "/lmb_pmc_ppu1@0/io-module@00"; + pmc_ppu1_io_intc = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_intc@0C"; + pmc_ppu1_io_gpi1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@20"; + pmc_ppu1_io_gpi2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@24"; + pmc_ppu1_io_gpi3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@28"; + pmc_ppu1_io_gpi4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@2c"; + pmc_ppu1_io_gpo1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@10"; + pmc_ppu1_io_gpo2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@14"; + pmc_ppu1_io_gpo3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@18"; + pmc_ppu1_io_gpo4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@1c"; + pmc_ppu1_io_pit1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@40"; + pmc_ppu1_io_pit2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@50"; + pmc_ppu1_io_pit3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@60"; + pmc_ppu1_io_pit4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@70"; + lmb_psm = "/lmb_psm@0"; + lmb_ddrmc0 = "/lmb_ddrmc@0"; + ddrmc0_ram_data = "/lmb_ddrmc@0/ddrmc0_ram_data@0x1c000"; + ddrmc0_ram_instr = "/lmb_ddrmc@0/ddrmc0_ram_instr@0x20000"; + ddrmc0_ram_exchange = "/lmb_ddrmc@0/ddrmc0_ram_exchange@0x08000"; + ddrmc_0_io_module = "/lmb_ddrmc@0/io-module@00"; + ddrmc0_io_intc = "/lmb_ddrmc@0/io-module@00/ddrmc0_intc@0C"; + ddrmc0_io_gpo1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_gpo@10"; + ddrmc0_io_pit1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@40"; + ddrmc0_io_pit2 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@50"; + ddrmc0_io_pit3 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@60"; + ddrmc0_io_pit4 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@70"; + ddrmc_uart0 = "/lmb_ddrmc@0/ddrmc_uart0@0"; + lmb_ddrmc1 = "/lmb_ddrmc@1"; + ddrmc1_ram_data = "/lmb_ddrmc@1/ddrmc1_ram_data@0x1c000"; + ddrmc1_ram_instr = "/lmb_ddrmc@1/ddrmc1_ram_instr@0x20000"; + ddrmc1_ram_exchange = "/lmb_ddrmc@1/ddrmc1_ram_exchange@0x08000"; + amba_rpu = "/amba_rpu@0"; + amba_r5_0 = "/amba_r5@0"; + amba_r5_1 = "/amba_r5@1"; + dummy1 = "/dummy1@0"; + smmu_tbu0 = "/tbu0_slave@0"; + smmu_tbu1 = "/tbu1_slave@0"; + smmu_tbu2 = "/tbu2_slave@0"; + smmu_tbu3 = "/tbu3_slave@0"; + smmu_tbu4 = "/tbu4_slave@0"; + smmu_tbu5 = "/tbu5_slave@0"; + smmu_tbu6 = "/tbu6_slave@0"; + ddr_mem = "/memory@00000000"; + ddr_2_mem = "/memory@8_0000_0000"; + ddr_3_mem = "/memory@0x50000000000ULL"; + ocm_mem_bank_0 = "/ocm_mem_bank_0@"; + ocm_mem_bank_1 = "/ocm_mem_bank_1@"; + ocm_mem_bank_2 = "/ocm_mem_bank_2@"; + ocm_mem_bank_3 = "/ocm_mem_bank_3@"; + xram_mem = "/xram_mem@0xbbe00000"; + ipi_msgbuf = "/ipi_msgbuf@0"; + pmc_ram = "/pmc_ram@0xf2000000"; + pmc_ram_bank_0 = "/pmc_ram_bank_0@0x0"; + pmc_ppu1_insn_ram = "/pmc_ppu1_ram@0xf0200000"; + pmc_ppu1_data_ram = "/pmc_ppu1_ram@0xf0280000"; + lqspi_mr = "/lqspi_mr@0"; + lospi_mr = "/lospi_mr@0"; + cpu0 = "/cpus/apu_cpu@0"; + cpu1 = "/cpus/apu_cpu@1"; + cpu2 = "/cpus/apu_cpu@2"; + cpu3 = "/cpus/apu_cpu@3"; + cpu4 = "/cpus/apu_cpu@4"; + cpu5 = "/cpus/apu_cpu@5"; + cpu6 = "/cpus/apu_cpu@6"; + cpu7 = "/cpus/apu_cpu@7"; + rpu_a = "/cpus/rpu_a@0"; + rpu_cpu0 = "/cpus/rpu_a@0/rpu_cpu_a@0"; + rpu_cpu1 = "/cpus/rpu_a@0/rpu_cpu_a@1"; + rpu_b = "/cpus/rpu_b@0"; + rpu_cpu2 = "/cpus/rpu_b@0/rpu_cpu_b@0"; + rpu_cpu3 = "/cpus/rpu_b@0/rpu_cpu_b@1"; + rpu_c = "/cpus/rpu_c@0"; + rpu_cpu4 = "/cpus/rpu_c@0/rpu_cpu_c@0"; + rpu_cpu5 = "/cpus/rpu_c@0/rpu_cpu_c@1"; + rpu_d = "/cpus/rpu_d@0"; + rpu_cpu6 = "/cpus/rpu_d@0/rpu_cpu_d@0"; + rpu_cpu7 = "/cpus/rpu_d@0/rpu_cpu_d@1"; + rpu_e = "/cpus/rpu_e@0"; + rpu_cpu8 = "/cpus/rpu_e@0/rpu_cpu_e@0"; + rpu_cpu9 = "/cpus/rpu_e@0/rpu_cpu_e@1"; + amba_apu = "/amba_apu@0"; + timer = "/amba_apu@0/timer"; + amba_apu_gic = "/amba_apu_gic@0"; + gic = "/amba_apu_gic@0/interrupt-controller@0xe2000000"; + amba_alias = "/amba_alias@0"; + qemu_sysmem = "/qemu_sysmem@0"; + psm0 = "/dummy_ppu0@0"; + pmc_ppu0 = "/dummy_ppu0@0"; + pmc_ppu1 = "/dummy_ppu1@0"; + ddrmc_ub0 = "/dummy_ddrmc0@0"; + ddrmc_ub1 = "/dummy_ddrmc1@0"; + ddr = "/ddr@0x00000000"; + ddr_2 = "/ddr_2@0x800000000ULL"; + mdio0 = "/mdio"; + phy0 = "/mdio/phy@1"; + phy1 = "/mdio/phy@2"; + cpunone = "/cpu_dummy"; + smmu_tbu7 = "/tbu7_slave@0"; + smmu_tbu8 = "/tbu8_slave@0"; + smmu_tbu9 = "/tbu9_slave@0"; + smmu_tbu10 = "/tbu10_slave@0"; + smmu_tbu11 = "/tbu11_slave@0"; + smmu_tbu12 = "/tbu12_slave@0"; + mr_rpu_gic_a = "/mr_rpu_gic_a@0"; + rpu_gic_a = "/mr_rpu_gic_a@0/rpu_gic_a@0x0"; + mr_rpu_gic_b = "/mr_rpu_gic_b@0"; + rpu_gic_b = "/mr_rpu_gic_b@0/rpu_gic_b@0x0"; + mr_rpu_gic_c = "/mr_rpu_gic_c@0"; + rpu_gic_c = "/mr_rpu_gic_c@0/rpu_gic_c@0x0"; + mr_rpu_gic_d = "/mr_rpu_gic_d@0"; + rpu_gic_d = "/mr_rpu_gic_d@0/rpu_gic_d@0x0"; + mr_rpu_gic_e = "/mr_rpu_gic_e@0"; + rpu_gic_e = "/mr_rpu_gic_e@0/rpu_gic_e@0x0"; + tcm_core0 = "/tcm_core@0"; + atcm_rpu_core0 = "/tcm_core@0/atcm_rpu_core0@0x00000"; + btcm_rpu_core0 = "/tcm_core@0/btcm_rpu_core0@0x00000"; + ctcm_rpu_core0 = "/tcm_core@0/ctcm_rpu_core0@0x00000"; + tcm_core1 = "/tcm_core@1"; + atcm_rpu_core1 = "/tcm_core@1/atcm_rpu_core1@0x00000"; + btcm_rpu_core1 = "/tcm_core@1/btcm_rpu_core1@0x00000"; + ctcm_rpu_core1 = "/tcm_core@1/ctcm_rpu_core1@0x00000"; + tcm_core2 = "/tcm_core@2"; + atcm_rpu_core2 = "/tcm_core@2/atcm_rpu_core2@0x00000"; + btcm_rpu_core2 = "/tcm_core@2/btcm_rpu_core2@0x00000"; + ctcm_rpu_core2 = "/tcm_core@2/ctcm_rpu_core2@0x00000"; + tcm_core3 = "/tcm_core@3"; + atcm_rpu_core3 = "/tcm_core@3/atcm_rpu_core3@0x00000"; + btcm_rpu_core3 = "/tcm_core@3/btcm_rpu_core3@0x00000"; + ctcm_rpu_core3 = "/tcm_core@3/ctcm_rpu_core3@0x00000"; + tcm_core4 = "/tcm_core@4"; + atcm_rpu_core4 = "/tcm_core@4/atcm_rpu_core4@0x00000"; + btcm_rpu_core4 = "/tcm_core@4/btcm_rpu_core4@0x00000"; + ctcm_rpu_core4 = "/tcm_core@4/ctcm_rpu_core4@0x00000"; + tcm_core5 = "/tcm_core@5"; + atcm_rpu_core5 = "/tcm_core@5/atcm_rpu_core5@0x00000"; + btcm_rpu_core5 = "/tcm_core@5/btcm_rpu_core5@0x00000"; + ctcm_rpu_core5 = "/tcm_core@5/ctcm_rpu_core5@0x00000"; + tcm_core6 = "/tcm_core@6"; + atcm_rpu_core6 = "/tcm_core@6/atcm_rpu_core6@0x00000"; + btcm_rpu_core6 = "/tcm_core@6/btcm_rpu_core6@0x00000"; + ctcm_rpu_core6 = "/tcm_core@6/ctcm_rpu_core6@0x00000"; + tcm_core7 = "/tcm_core@7"; + atcm_rpu_core7 = "/tcm_core@7/atcm_rpu_core7@0x00000"; + btcm_rpu_core7 = "/tcm_core@7/btcm_rpu_core7@0x00000"; + ctcm_rpu_core7 = "/tcm_core@7/ctcm_rpu_core7@0x00000"; + tcm_core8 = "/tcm_core@8"; + atcm_rpu_core8 = "/tcm_core@8/atcm_rpu_core8@0x00000"; + btcm_rpu_core8 = "/tcm_core@8/btcm_rpu_core8@0x00000"; + ctcm_rpu_core8 = "/tcm_core@8/ctcm_rpu_core8@0x00000"; + tcm_core9 = "/tcm_core@9"; + atcm_rpu_core9 = "/tcm_core@9/atcm_rpu_core9@0x00000"; + btcm_rpu_core9 = "/tcm_core@9/btcm_rpu_core9@0x00000"; + ctcm_rpu_core9 = "/tcm_core@9/ctcm_rpu_core9@0x00000"; + tcm_cluster_a = "/tcm_cluster_a@0"; + tcm_cluster_b = "/tcm_cluster_b@0"; + tcm_cluster_c = "/tcm_cluster_c@0"; + tcm_cluster_d = "/tcm_cluster_d@0"; + tcm_cluster_e = "/tcm_cluster_e@0"; + amba_r5_2 = "/amba_r5@2"; + amba_r5_3 = "/amba_r5@3"; + amba_r5_4 = "/amba_r5@4"; + amba_r5_5 = "/amba_r5@5"; + amba_r5_6 = "/amba_r5@6"; + amba_r5_7 = "/amba_r5@7"; + amba_r5_8 = "/amba_r5@8"; + amba_r5_9 = "/amba_r5@9"; + rpu2_s_memattr = "/rpu2_s_ma"; + rpu3_s_memattr = "/rpu3_s_ma"; + rpu4_s_memattr = "/rpu4_s_ma"; + rpu5_s_memattr = "/rpu5_s_ma"; + rpu6_s_memattr = "/rpu6_s_ma"; + rpu7_s_memattr = "/rpu7_s_ma"; + rpu8_s_memattr = "/rpu8_s_ma"; + rpu9_s_memattr = "/rpu9_s_ma"; + usb1_memattr = "/usb1_ma"; + apu2_s_memattr = "/apu2_s_ma"; + apu2_ns_memattr = "/apu2_ns_ma"; + apu3_s_memattr = "/apu3_s_ma"; + apu3_ns_memattr = "/apu3_ns_ma"; + apu4_s_memattr = "/apu4_s_ma"; + apu4_ns_memattr = "/apu4_ns_ma"; + apu5_s_memattr = "/apu5_s_ma"; + apu5_ns_memattr = "/apu5_ns_ma"; + apu6_s_memattr = "/apu6_s_ma"; + apu6_ns_memattr = "/apu6_ns_ma"; + apu7_s_memattr = "/apu7_s_ma"; + apu7_ns_memattr = "/apu7_ns_ma"; + apu8_s_memattr = "/apu8_s_ma"; + apu8_ns_memattr = "/apu8_ns_ma"; + apu9_s_memattr = "/apu9_s_ma"; + apu9_ns_memattr = "/apu9_ns_ma"; + apu10_s_memattr = "/apu10_s_ma"; + apu10_ns_memattr = "/apu10_ns_ma"; + apu11_s_memattr = "/apu11_s_ma"; + apu11_ns_memattr = "/apu11_ns_ma"; + apu12_s_memattr = "/apu12_s_ma"; + apu12_ns_memattr = "/apu12_ns_ma"; + apu13_s_memattr = "/apu13_s_ma"; + apu13_ns_memattr = "/apu13_ns_ma"; + apu14_s_memattr = "/apu14_s_ma"; + apu14_ns_memattr = "/apu14_ns_ma"; + apu15_s_memattr = "/apu15_s_ma"; + apu15_ns_memattr = "/apu15_ns_ma"; + apu16_s_memattr = "/apu16_s_ma"; + apu16_ns_memattr = "/apu16_ns_ma"; + apu17_s_memattr = "/apu17_s_ma"; + apu17_ns_memattr = "/apu17_ns_ma"; + apu18_s_memattr = "/apu18_s_ma"; + apu18_ns_memattr = "/apu18_ns_ma"; + apu19_s_memattr = "/apu19_s_ma"; + apu19_ns_memattr = "/apu19_ns_ma"; + apu20_s_memattr = "/apu20_s_ma"; + apu20_ns_memattr = "/apu20_ns_ma"; + apu21_s_memattr = "/apu21_s_ma"; + apu21_ns_memattr = "/apu21_ns_ma"; + apu22_s_memattr = "/apu22_s_ma"; + apu22_ns_memattr = "/apu22_ns_ma"; + apu23_s_memattr = "/apu23_s_ma"; + apu23_ns_memattr = "/apu23_ns_ma"; + apu24_s_memattr = "/apu24_s_ma"; + apu24_ns_memattr = "/apu24_ns_ma"; + apu25_s_memattr = "/apu25_s_ma"; + apu25_ns_memattr = "/apu25_ns_ma"; + apu26_s_memattr = "/apu26_s_ma"; + apu26_ns_memattr = "/apu26_ns_ma"; + apu27_s_memattr = "/apu27_s_ma"; + apu27_ns_memattr = "/apu27_ns_ma"; + apu28_s_memattr = "/apu28_s_ma"; + apu28_ns_memattr = "/apu28_ns_ma"; + apu29_s_memattr = "/apu29_s_ma"; + apu29_ns_memattr = "/apu29_ns_ma"; + apu30_s_memattr = "/apu30_s_ma"; + apu30_ns_memattr = "/apu30_ns_ma"; + apu31_s_memattr = "/apu31_s_ma"; + apu31_ns_memattr = "/apu31_ns_ma"; + asu_cpu_memattr = "/asu_cpu_ma"; + lmb_amba_asu = "/lmb_amba_asu@0"; + ocm_mem = "/ocm_mem@0xbbe00000"; + asu_dram = "/asu_data_ram_wrapper@0xebe40000"; + psm_gic_proxy = "/psm_gic_proxy@0"; + asu_cpu = "/asu_cpu@0"; + }; +}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.dts b/boards/amd/versal2_rpu/versal2_rpu.dts new file mode 100644 index 000000000000..36e8c2ed7e9e --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu.dts @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ocm = &ocm; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@30000 { + compatible = "mmio-sram"; + reg = <0x30000 0x7ffd0000>; + }; +}; + +&ocm { + status = "okay"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.yaml b/boards/amd/versal2_rpu/versal2_rpu.yaml new file mode 100644 index 000000000000..91753bea822c --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu.yaml @@ -0,0 +1,13 @@ +identifier: versal2_rpu +name: AMD Development board for Versal Gen 2 RPU +arch: arm +toolchain: + - zephyr +supported: + - scsi + - ufs +testing: + ignore_tags: + - net + - bluetooth +vendor: amd diff --git a/boards/amd/versal2_rpu/versal2_rpu_defconfig b/boards/amd/versal2_rpu/versal2_rpu_defconfig new file mode 100644 index 000000000000..ed6209ff2afb --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu_defconfig @@ -0,0 +1,13 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# Enable cache and arch timer +CONFIG_CACHE_MANAGEMENT=y +CONFIG_ARM_ARCH_TIMER=y diff --git a/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu b/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu new file mode 100644 index 000000000000..192725829dba --- /dev/null +++ b/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu @@ -0,0 +1,8 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_VERSALNET_RPU + select SOC_AMD_VERSALNET_RPU diff --git a/boards/amd/versalnet_rpu/board.cmake b/boards/amd/versalnet_rpu/board.cmake new file mode 100644 index 000000000000..a624cc396d3c --- /dev/null +++ b/boards/amd/versalnet_rpu/board.cmake @@ -0,0 +1,7 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) diff --git a/boards/amd/versalnet_rpu/board.yml b/boards/amd/versalnet_rpu/board.yml new file mode 100644 index 000000000000..6135a69a6ab1 --- /dev/null +++ b/boards/amd/versalnet_rpu/board.yml @@ -0,0 +1,6 @@ +board: + name: versalnet_rpu + full_name: Versal NET RPU development board + vendor: amd + socs: + - name: amd_versalnet_rpu diff --git a/boards/amd/versalnet_rpu/doc/index.rst b/boards/amd/versalnet_rpu/doc/index.rst new file mode 100644 index 000000000000..35d3ea5f22df --- /dev/null +++ b/boards/amd/versalnet_rpu/doc/index.rst @@ -0,0 +1,75 @@ +.. zephyr:board:: versalnet_rpu + +Overview +******** +This configuration provides support for the RPU(R52), real-time processing unit on Xilinx +Versal Net SOC, it can operate as following: + +* Two independent R52 cores with their own TCMs (tightly coupled memories) +* Or as a single dual lock step unit with the TCM. + +This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices: + +* ARM GIC v3 Interrupt Controller +* Global Timer Counter +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The ocm0 memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Only the first core of the R52 subsystem is supported. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versalnet_rpu + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! + + +References +********** + +1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520) +2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en) diff --git a/boards/amd/versalnet_rpu/support/xsdb.cfg b/boards/amd/versalnet_rpu/support/xsdb.cfg new file mode 100644 index 000000000000..087ed4c85c11 --- /dev/null +++ b/boards/amd/versalnet_rpu/support/xsdb.cfg @@ -0,0 +1,44 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc load_image args { + set elf_file [lindex $args 0] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + after 100 + targets -set -nocase -filter {name =~ "Versal*"} + after 100 + rst -system + after 100 + + if { [info exists ::env(PDI_FILE_PATH)] } { + device program $::env(PDI_FILE_PATH) + } else { + puts "Error: env variable PDI_FILE_PATH is not set" + exit + } + + after 100 + targets -set -nocase -filter {name =~ "DPC"} + after 100 + # Configure timestamp generator to run global timer gracefully + # Ideally these registers should be set from bootloader (cdo) + mwr -force 0xeb5b0000 0x1 + mwr -force 0xeb5b0020 100000000 + after 100 + + targets -set -nocase -filter {name =~ "*Cortex-R52 #0.0"} + rst -proc + after 100 + dow -force $elf_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.dts b/boards/amd/versalnet_rpu/versalnet_rpu.dts new file mode 100644 index 000000000000..f9ff17225673 --- /dev/null +++ b/boards/amd/versalnet_rpu/versalnet_rpu.dts @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,ocm = &ocm; + }; + + sdhci_ref_clk: sdhci-ref-clk { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0x00000 DT_SIZE_M(2048)>; + }; +}; + +&ocm { + status = "okay"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&sdhci0 { + status = "okay"; + power-delay-ms = <10>; + clocks = <&sdhci_ref_clk>; +}; + +&sdhci1 { + status = "okay"; + clocks = <&sdhci_ref_clk>; +}; diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.yaml b/boards/amd/versalnet_rpu/versalnet_rpu.yaml new file mode 100644 index 000000000000..21f19ea6cced --- /dev/null +++ b/boards/amd/versalnet_rpu/versalnet_rpu.yaml @@ -0,0 +1,12 @@ +identifier: versalnet_rpu +name: AMD Development board for Versal NET RPU +arch: arm +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +vendor: amd +supported: + - sdhc diff --git a/boards/amd/versalnet_rpu/versalnet_rpu_defconfig b/boards/amd/versalnet_rpu/versalnet_rpu_defconfig new file mode 100644 index 000000000000..4aec6a299f37 --- /dev/null +++ b/boards/amd/versalnet_rpu/versalnet_rpu_defconfig @@ -0,0 +1,9 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst index 3e290dd2f284..42767445c55c 100644 --- a/boards/andestech/adp_xc7k_ae350/doc/index.rst +++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst @@ -1,7 +1,4 @@ -.. _adp_xc7k_ae350: - -Andes ADP-XC7K AE350 -#################### +.. zephyr:board:: adp_xc7k Overview ******** @@ -52,40 +49,7 @@ The ADP-XC7K AE350 platform provides following hardware components: Supported Features ================== -The ``adp_xc7k/ae350`` board configuration supports the following hardware features: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| PLIC | on-chip | interrupt_controller | -+----------------+------------+----------------------+ -| RISC-V Machine | on-chip | timer | -| Timer | | | -+----------------+------------+----------------------+ -| GPIO | on-chip | gpio | -+----------------+------------+----------------------+ -| UART | on-chip | serial | -+----------------+------------+----------------------+ -| COUNTER | on-chip | counter | -+----------------+------------+----------------------+ -| SPI | on-chip | spi | -+----------------+------------+----------------------+ -| I2C | on-chip | i2c | -+----------------+------------+----------------------+ -| EEPROM | on-chip | eeprom | -+----------------+------------+----------------------+ -| FLASH | on-chip | flash | -+----------------+------------+----------------------+ -| HWINFO | on-chip | syscon | -+----------------+------------+----------------------+ -| MAILBOX | on-chip | mbox | -+----------------+------------+----------------------+ -| DMA | on-chip | dma | -+----------------+------------+----------------------+ -| WATCHDOG | on-chip | wdt | -+----------------+------------+----------------------+ - -Other hardware features are not supported yet. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -206,6 +170,8 @@ settings are 115200 8N1. Programming and debugging ************************* +.. zephyr:board-supported-runners:: + For debugging zephyr applications or burning them into a flash, you will need to connect Andes ICE from host computer to ADP-XC7K board and execute the Andes ICE management software, ICEman, on this host computer. diff --git a/boards/antmicro/index.rst b/boards/antmicro/index.rst index 34beaee93d25..d7393218659c 100644 --- a/boards/antmicro/index.rst +++ b/boards/antmicro/index.rst @@ -1,7 +1,7 @@ .. _boards-antmicro: Antmicro -### +######## .. toctree:: :maxdepth: 1 diff --git a/boards/antmicro/myra_sip_baseboard/doc/index.rst b/boards/antmicro/myra_sip_baseboard/doc/index.rst index ee33397e453d..0eb273c52455 100644 --- a/boards/antmicro/myra_sip_baseboard/doc/index.rst +++ b/boards/antmicro/myra_sip_baseboard/doc/index.rst @@ -116,48 +116,7 @@ Other board's peripherals: Supported Features ------------------ -The Zephyr ``myra_sip_baseboard`` board target supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; serial | -| | | port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac controller | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| NVS | on-chip | nvs | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| FDCAN1 | on-chip | can controller | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. +.. zephyr:board-supported-hw:: Connections and IOs ------------------- @@ -213,6 +172,8 @@ settings are 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``myra_sip_baseboard`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). Flashing diff --git a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts index e2d011fddf01..fc815cd352b8 100644 --- a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts +++ b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts @@ -55,6 +55,7 @@ volt-sensor0 = &vref; volt-sensor1 = &vbat; rtc = &rtc; + eeprom-0 = &mb85rs1mt; }; }; diff --git a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml index 5979e67fd174..77fe8017c5d8 100644 --- a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml +++ b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml @@ -19,6 +19,7 @@ supported: - can - rtc - sensors + - eeprom testing: timeout_multiplier: 3 renode: diff --git a/boards/arduino/due/arduino_due-pinctrl.dtsi b/boards/arduino/due/arduino_due-pinctrl.dtsi index 08f369eed7dc..410df4f7eea4 100644 --- a/boards/arduino/due/arduino_due-pinctrl.dtsi +++ b/boards/arduino/due/arduino_due-pinctrl.dtsi @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { twi0_default: twi0_default { @@ -53,10 +53,25 @@ }; }; + spi0_default: spi0_default { + group1 { + pinmux = , + , + ; + }; + }; + pwm0_default: pwm0_default { group1 { pinmux = , ; }; }; + + adc0_default: adc0_default { + group1 { + pinmux = , + ; + }; + }; }; diff --git a/boards/arduino/due/arduino_due.dts b/boards/arduino/due/arduino_due.dts index bbfc92b110c7..0e9c4693abe4 100644 --- a/boards/arduino/due/arduino_due.dts +++ b/boards/arduino/due/arduino_due.dts @@ -4,6 +4,7 @@ #include #include "arduino_due-pinctrl.dtsi" +#include "arduino_r3_connector.dtsi" / { model = "Arduino Due with an Atmel SAM3X8E SoC"; @@ -57,6 +58,13 @@ pinctrl-names = "default"; }; +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&pioa 28 GPIO_ACTIVE_LOW>; +}; + &uart { status = "okay"; current-speed = <115200>; diff --git a/boards/arduino/due/arduino_due.yaml b/boards/arduino/due/arduino_due.yaml index b8beeac60c92..12f9ba82ad43 100644 --- a/boards/arduino/due/arduino_due.yaml +++ b/boards/arduino/due/arduino_due.yaml @@ -8,6 +8,7 @@ toolchain: flash: 512 ram: 96 supported: + - adc - arduino_i2c - gpio - watchdog diff --git a/boards/arduino/due/arduino_r3_connector.dtsi b/boards/arduino/due/arduino_r3_connector.dtsi new file mode 100644 index 000000000000..16fcfa2674fc --- /dev/null +++ b/boards/arduino/due/arduino_r3_connector.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright 2025 Arduino SA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = < 0 0 &pioa 16 0>, /* A0 */ + < 1 0 &pioa 24 0>, /* A1 */ + < 2 0 &pioa 23 0>, /* A2 */ + < 3 0 &pioa 22 0>, /* A3 */ + < 4 0 &pioa 6 0>, /* A4 */ + < 5 0 &pioa 4 0>, /* A5 */ + < 6 0 &pioa 8 0>, /* D0 */ + < 7 0 &pioa 9 0>, /* D1 */ + < 8 0 &piob 25 0>, /* D2 */ + < 9 0 &pioc 28 0>, /* D3 */ + <10 0 &pioa 29 0>, /* D4 */ + <11 0 &pioc 25 0>, /* D5 */ + <12 0 &pioc 24 0>, /* D6 */ + <13 0 &pioc 23 0>, /* D7 */ + <14 0 &pioc 22 0>, /* D8 */ + <15 0 &pioc 21 0>, /* D9 */ + <16 0 &pioa 28 0>, /* D10 */ + <17 0 &piod 7 0>, /* D11 */ + <18 0 &piod 8 0>, /* D12 */ + <19 0 &piob 27 0>, /* D13 */ + <20 0 &pioa 17 0>, /* D20 */ + <21 0 &pioa 18 0>; /* D21 */ + }; +}; diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst index e1eda346744c..9bce2aa68e3b 100644 --- a/boards/arduino/due/doc/index.rst +++ b/boards/arduino/due/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_due: - -Arduino Due -########### +.. zephyr:board:: arduino_due Overview ******** @@ -23,41 +20,17 @@ the processor. .. note:: This configuration is not supported by Arduino. -.. image:: img/arduino_due.jpg - :align: center - :alt: Arduino Due - Hardware ******** + Supported Features ================== -The arduino_due board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not currently supported by the Zephyr kernel. +.. zephyr:board-supported-hw:: + See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete list of Arduino Due board hardware features. -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arduino/due/arduino_due_defconfig`. - .. note:: For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13). @@ -131,6 +104,8 @@ default, is utilizing this controller. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts index 5d6e0dd7d883..7505ba0f2df7 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts @@ -252,3 +252,9 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; }; + +/* alias used by display shields */ +zephyr_mipi_dsi: &mipi_dsi {}; + +/* alias used by LCD display shields */ +zephyr_lcd_controller: <dc {}; diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst index 696844a71fab..508f6363151c 100644 --- a/boards/arduino/giga_r1/doc/index.rst +++ b/boards/arduino/giga_r1/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_giga_r1_board: - -Arduino GIGA R1 WiFi -#################### +.. zephyr:board:: arduino_giga_r1 Overview ******** @@ -22,10 +19,6 @@ The board features: - Audio jack - ATECC608A secure element -.. image:: img/arduino_giga_r1.jpg - :align: center - :alt: Arduino GIGA R1 WiFi - More information about the board, including the datasheet, pinout and schematics, can be found at the `Arduino GIGA website`_. @@ -38,39 +31,7 @@ More information about STM32H747XIH6 can be found here: Supported Features ================== -The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the -following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| QSPI | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| RADIO | Murata 1DX | WiFi and Bluetooth module | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr port. +.. zephyr:board-supported-hw:: Fetch Binary Blobs ****************** @@ -102,6 +63,8 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``arduino_giga_r1`` board should be built per core target, using either ``arduino_giga_r1/stm32h747xx/m7`` or ``arduino_giga_r1/stm32h747xx/m4`` as the target. diff --git a/boards/arduino/mkrzero/arduino_mkr_connector.dtsi b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi index 0f16581d8b8b..0fba02ef759e 100644 --- a/boards/arduino/mkrzero/arduino_mkr_connector.dtsi +++ b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi @@ -3,34 +3,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_mkr_header: connector { compatible = "arduino-mkr-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &porta 22 0>, /* D0 */ - <1 0 &porta 23 0>, /* D1 */ - <2 0 &porta 10 0>, /* D2 */ - <3 0 &porta 11 0>, /* D3 */ - <4 0 &portb 10 0>, /* D4 */ - <5 0 &portb 11 0>, /* D5 */ - <6 0 &porta 20 0>, /* D6 */ - <7 0 &porta 21 0>, /* D7 */ - <8 0 &porta 16 0>, /* D8 / SPI-COPI */ - <9 0 &porta 17 0>, /* D9 / SPI-SCK */ - <10 0 &porta 19 0>, /* D10 / SPI-CIPO */ - <11 0 &porta 8 0>, /* D11 / I2C-SDA */ - <12 0 &porta 9 0>, /* D12 / I2C-SCL */ - <13 0 &portb 23 0>, /* D13 / UART-RX */ - <14 0 &portb 22 0>, /* D14 / UART-TX */ - <15 0 &porta 2 0>, /* D15 / A0 */ - <16 0 &portb 2 0>, /* D16 / A1 */ - <17 0 &portb 3 0>, /* D17 / A2 */ - <18 0 &porta 4 0>, /* D18 / A3 */ - <19 0 &porta 5 0>, /* D19 / A4 */ - <20 0 &porta 6 0>, /* D20 / A5 */ - <21 0 &porta 7 0>; /* D21 / A6 */ + gpio-map = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 / SPI-COPI */ + , /* D9 / SPI-SCK */ + , /* D10 / SPI-CIPO */ + , /* D11 / I2C-SDA */ + , /* D12 / I2C-SCL */ + , /* D13 / UART-RX */ + , /* D14 / UART-TX */ + , /* D15 / A0 */ + , /* D16 / A1 */ + , /* D17 / A2 */ + , /* D18 / A3 */ + , /* D19 / A4 */ + , /* D20 / A5 */ + ; /* D21 / A6 */ }; }; diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst index b6f92d969302..3e5281521317 100644 --- a/boards/arduino/mkrzero/doc/index.rst +++ b/boards/arduino/mkrzero/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_mkrzero: - -Arduino MKR Zero -#################### +.. zephyr:board:: arduino_mkrzero Overview ******** @@ -9,10 +6,6 @@ Overview The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU. This board come with microSD card holder that allows you to play with music files with no extra hardware. -.. image:: img/arduino_mkrzero.jpg - :align: center - :alt: Arduino MKR Zero - Hardware ******** @@ -27,46 +20,7 @@ Hardware Supported Features ================== -The arduino_mkrzero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arduino/mkrzero/arduino_mkrzero_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -124,6 +78,8 @@ Arduino MKR Zero, the DAC is available on pin A0. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Arduino MKR Zero ships the BOSSA compatible bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts index 598d206bd314..03963cfe0094 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts @@ -7,7 +7,7 @@ #include #include "arduino_nano_33_ble-common.dtsi" #include "arduino_nano_33_ble-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 BLE"; diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts index e5b18d2b120d..1593360220df 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts @@ -7,7 +7,7 @@ #include #include "arduino_nano_33_ble-common.dtsi" #include "arduino_nano_33_ble-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 BLE Sense"; diff --git a/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi new file mode 100644 index 000000000000..bec8b3b87751 --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 Huawei Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_nano_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 / UART-TX */ + , /* D1 / UART-RX */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 / SPI-MOSI */ + , /* D12 / SPI-MISO */ + , /* D13 / SPI-SCK */ + , /* D14 / A0 */ + , /* D15 / A1 */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 / I2C-SDA */ + , /* D19 / A5 / I2C-SCL */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_nano_i2c: &i2c0 {}; +arduino_nano_spi: &spi2 {}; +arduino_nano_serial: &uart0 {}; diff --git a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi deleted file mode 100644 index af20cc6c755a..000000000000 --- a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2022 Huawei Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - arduino_nano_header: connector { - compatible = "arduino-nano-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 3 0>, /* D0 / UART-TX */ - <1 0 &gpio1 10 0>, /* D1 / UART-RX */ - <2 0 &gpio1 11 0>, /* D2 */ - <3 0 &gpio1 12 0>, /* D3 */ - <4 0 &gpio1 15 0>, /* D4 */ - <5 0 &gpio1 13 0>, /* D5 */ - <6 0 &gpio1 14 0>, /* D6 */ - <7 0 &gpio0 23 0>, /* D7 */ - <8 0 &gpio0 21 0>, /* D8 */ - <9 0 &gpio0 27 0>, /* D9 */ - <10 0 &gpio1 2 0>, /* D10 */ - <11 0 &gpio1 1 0>, /* D11 / SPI-MOSI */ - <12 0 &gpio1 8 0>, /* D12 / SPI-MISO */ - <13 0 &gpio0 13 0>, /* D13 / SPI-SCK */ - <14 0 &gpio0 4 0>, /* D14 / A0 */ - <15 0 &gpio0 5 0>, /* D15 / A1 */ - <16 0 &gpio0 30 0>, /* D16 / A2 */ - <17 0 &gpio0 29 0>, /* D17 / A3 */ - <18 0 &gpio0 31 0>, /* D18 / A4 / I2C-SDA */ - <19 0 &gpio0 2 0>, /* D19 / A5 / I2C-SCL */ - <20 0 &gpio0 28 0>, /* D20 / A6 */ - <21 0 &gpio0 3 0>; /* D21 / A7 */ - }; -}; - -arduino_nano_i2c: &i2c0 {}; -arduino_nano_spi: &spi2 {}; -arduino_nano_serial: &uart0 {}; diff --git a/boards/arduino/nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst index 2b5ede0ea114..753209f349de 100644 --- a/boards/arduino/nano_33_ble/doc/index.rst +++ b/boards/arduino/nano_33_ble/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_nano_33_ble: - -Arduino Nano 33 BLE (Sense) -################################# +.. zephyr:board:: arduino_nano_33_ble Overview ******** @@ -11,58 +8,13 @@ nRF52840 ARM Cortex-M4F CPU. Arduino sells 2 variants of the board, the plain `BLE`_ type and the `BLE Sense`_ type. The "Sense" variant is distinguished by the inclusion of more sensors, but otherwise both variants are the same. -.. image:: img/arduino_nano_33_ble_sense.jpg - :align: center - :alt: Arduino Nano 33 BLE (Sense variant) - -The Sense variant of the board - Hardware ******** Supported Features ================== -The package is configured to support the following hardware: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C0 | on-chip | i2c | -+-----------+------------+----------------------+ -| I2C1 | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Notably, this includes the PDM (microphone) interface. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -77,6 +29,8 @@ as ``pull-up-gpios``. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + This board requires the Arduino variant of bossac. You will not be able to flash with the bossac included with the zephyr-sdk, or using shumatech's mainline build. diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts index 7a8e3b7e745a..f3af145110bb 100644 --- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts @@ -8,7 +8,7 @@ #include #include #include "arduino_nano_33_iot-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 IOT"; diff --git a/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi new file mode 100644 index 000000000000..697e56844036 --- /dev/null +++ b/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 Joylab AG + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_nano_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 / UART-RX */ + , /* D1 / UART-TX */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 / SPI-MOSI */ + , /* D12 / SPI-MISO */ + , /* D13 / SPI-SCK */ + , /* D14 / A0 */ + , /* D15 / A1 */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 / I2C-SDA */ + , /* D19 / A5 / I2C-SCL */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_nano_i2c: &sercom4 {}; +arduino_nano_spi: &sercom1 {}; +arduino_nano_serial: &sercom5 {}; diff --git a/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi deleted file mode 100644 index 9c69abdcacbd..000000000000 --- a/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2022 Joylab AG - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - arduino_nano_header: connector { - compatible = "arduino-nano-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &portb 23 0>, /* D0 / UART-RX */ - <1 0 &portb 22 0>, /* D1 / UART-TX */ - <2 0 &portb 10 0>, /* D2 */ - <3 0 &portb 11 0>, /* D3 */ - <4 0 &porta 7 0>, /* D4 */ - <5 0 &porta 5 0>, /* D5 */ - <6 0 &porta 4 0>, /* D6 */ - <7 0 &porta 6 0>, /* D7 */ - <8 0 &porta 18 0>, /* D8 */ - <9 0 &porta 20 0>, /* D9 */ - <10 0 &porta 21 0>, /* D10 */ - <11 0 &porta 16 0>, /* D11 / SPI-MOSI */ - <12 0 &porta 19 0>, /* D12 / SPI-MISO */ - <13 0 &porta 17 0>, /* D13 / SPI-SCK */ - <14 0 &porta 2 0>, /* D14 / A0 */ - <15 0 &portb 2 0>, /* D15 / A1 */ - <16 0 &porta 11 0>, /* D16 / A2 */ - <17 0 &porta 10 0>, /* D17 / A3 */ - <18 0 &portb 8 0>, /* D18 / A4 / I2C-SDA */ - <19 0 &portb 9 0>, /* D19 / A5 / I2C-SCL */ - <20 0 &porta 9 0>, /* D20 / A6 */ - <21 0 &portb 3 0>; /* D21 / A7 */ - }; -}; - -arduino_nano_i2c: &sercom4 {}; -arduino_nano_spi: &sercom1 {}; -arduino_nano_serial: &sercom5 {}; diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst index 419c02a5ceac..14c76bc9e25e 100644 --- a/boards/arduino/nano_33_iot/doc/index.rst +++ b/boards/arduino/nano_33_iot/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_nano_33_iot: - -Arduino Nano 33 IOT -################### +.. zephyr:board:: arduino_nano_33_iot Overview ******** @@ -9,10 +6,6 @@ Overview The Arduino Nano 33 IOT is a small form factor development board with USB, Wifi, Bluetooth, a 6 axis IMU, and secure element. -.. image:: img/nano_33_iot.jpg - :align: center - :alt: Arduino Nano 33 IOT - Hardware ******** @@ -28,43 +21,7 @@ Hardware Supported Features ================== -The arduino_nano_33_iot board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -109,6 +66,8 @@ serial port that echos characters back to the host PC. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The bootloader can be entered by quickly tapping the reset button twice. diff --git a/boards/arduino/nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst index 1bf984f23f4f..826fb2f42013 100644 --- a/boards/arduino/nicla_sense_me/doc/index.rst +++ b/boards/arduino/nicla_sense_me/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_nicla_sense_me: - -Arduino Nicla Sense ME -###################### +.. zephyr:board:: arduino_nicla_sense_me Overview ******** @@ -10,12 +7,6 @@ nrf52832 ARM Cortex-M4F CPU. The board houses 4 low power industrial grade senso that can measure rotation, acceleration, pressure, humidity, temperature, air quality and CO2 levels. -.. figure:: arduino_nicla_sense_me.jpg - :align: center - :alt: Arduino Nicla Sense ME - - Arduino Nicla Sense ME (Credit: Arduino) - Hardware ******** @@ -39,35 +30,7 @@ Hardware Supported Features ================== -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M/S) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth Low Energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -85,6 +48,8 @@ For more details please refer to the `datasheet`_, `full pinout`_ and the `schem Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``arduino_nicla_sense_me`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index 0028128f8e23..e9f39b173aef 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -225,7 +225,7 @@ zephyr_udc0: &usbotg_hs { port { gc2145_ep_out: endpoint { - remote-endpoint = <&dcmi_ep_in>; + remote-endpoint-label = "dcmi_ep_in"; }; }; @@ -240,19 +240,13 @@ zephyr_udc0: &usbotg_hs { pinctrl-names = "default"; status = "okay"; - sensor = <&gc2145>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - capture-rate = <1>; - dmas = <&dma1 0 38 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | - STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | - STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; - port { dcmi_ep_in: endpoint { - remote-endpoint = <&gc2145_ep_out>; + remote-endpoint-label = "gc2145_ep_out"; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; }; }; }; diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst index 73b2d7cd7337..f9cc62c6ee17 100644 --- a/boards/arduino/nicla_vision/doc/index.rst +++ b/boards/arduino/nicla_vision/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_nicla_vision_board: - -Arduino Nicla Vision -#################### +.. zephyr:board:: arduino_nicla_vision Overview ******** @@ -38,53 +35,7 @@ More information about STM32H747GAII6 can be found here: Supported Features ================== -The current Zephyr ``arduino_nicla_vision/stm32h747xx/m7`` board configuration supports the -following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DCMI | on-chip | Parallel Camera interface | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| RADIO | Murata 1DX | WiFi and Bluetooth module | -+-----------+------------+-------------------------------------+ - -And the ``arduino_nicla_vision/stm32h747xx/m4`` has the following -support from Zephyr: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr port. +.. zephyr:board-supported-hw:: Fetch Binary Blobs ****************** @@ -116,6 +67,8 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``arduino_nicla_vision`` board should be built per core target, using either ``arduino_nicla_vision/stm32h747xx/m7`` or ``arduino_nicla_vision/stm32h747xx/m4`` as the target. diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts index d1b63e91e52c..c3e45f6184ee 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts @@ -107,6 +107,8 @@ zephyr_udc0: &usbotg_fs { ð_txd0_pg13 >; pinctrl-names = "default"; + phy-connection-type = "rmii"; + phy-handle = <ð_phy>; status = "okay"; }; @@ -115,9 +117,39 @@ zephyr_udc0: &usbotg_fs { pinctrl-names = "default"; status = "okay"; - ethernet-phy@0 { + eth_phy: ethernet-phy@0 { compatible = "ethernet-phy"; reg = <0x00>; + }; +}; + +&quadspi { + pinctrl-0 = < &quadspi_bk1_io0_pd11 + &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 + &quadspi_bk1_io3_pd13 + &quadspi_bk1_ncs_pg6 + &quadspi_clk_pb2 >; + pinctrl-names = "default"; + status = "okay"; + + at25sf128a: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ + qspi-max-frequency = ; status = "okay"; + spi-bus-width = <2>; + st,read-id-dummy-cycles = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = < 1 >; + #size-cells = < 1 >; + + storage_partition: partition@0 { + label = "storage"; + reg=< 0x0 DT_SIZE_K(15872) >; + }; + }; }; }; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml index 6169f1b33649..d2d60fe33fc1 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml @@ -10,6 +10,7 @@ flash: 768 supported: - gpio - netif:eth + - qspi testing: ignore_tags: - mpu diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst index 8c6aa7884871..4b131659355d 100644 --- a/boards/arduino/opta/doc/index.rst +++ b/boards/arduino/opta/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_opta_m4_board: - -Arduino OPTA -############ +.. zephyr:board:: arduino_opta Overview ******** @@ -31,10 +28,6 @@ Additionally, the device features: - 8 x analog inputs - 4 x isolated relay outputs -.. image:: img/arduino_opta.jpeg - :align: center - :alt: ARDUINO-OPTA - More information about the board can be found at the `ARDUINO-OPTA website`_. More information about STM32H747XIH6 can be found here: @@ -45,55 +38,7 @@ More information about STM32H747XIH6 can be found here: Supported Features ================== -The ``arduino_opta/stm32h747xx/m7`` board target -supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| USB | on-board | usb-fs | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-board | eth | -+-----------+------------+-------------------------------------+ -| RS485 | on-board | uart | -+-----------+------------+-------------------------------------+ - -The ``arduino_opta/stm32h747xx/m4`` board target -supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig files: -:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` and -:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -153,6 +98,8 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``arduino_opta`` use the regular Zephyr build commands. See :ref:`build_an_application` for more information about application builds. diff --git a/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml index 580288b2382a..8036df3c65e4 100644 --- a/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml +++ b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml @@ -2,9 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 description: | - This allows to define a group of relays (like in the original Opta) - or other kinds of power switches controlled by a GPIO. Each power - switch is defined in a child node of the gpio-power-switches node. + Group of relays (like in the original Opta) or other kinds of power switches controlled by a GPIO. + + Each power switch is defined in a child node of the gpio-power-switches node. compatible: "gpio-power-switches" diff --git a/boards/arduino/portenta_h7/Kconfig.defconfig b/boards/arduino/portenta_h7/Kconfig.defconfig index b2a4abd35e73..3a59127ffa71 100644 --- a/boards/arduino/portenta_h7/Kconfig.defconfig +++ b/boards/arduino/portenta_h7/Kconfig.defconfig @@ -5,6 +5,9 @@ if BOARD_ARDUINO_PORTENTA_H7 if NETWORKING +config REGULATOR + default y + config NET_L2_ETHERNET default y diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi index 7a61e830e526..d7489b77d261 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi +++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi @@ -209,17 +209,33 @@ }; }; +&rng { + status = "okay"; +}; + &mac { pinctrl-0 = < ð_ref_clk_pa1 - ð_mdio_pa2 ð_crs_dv_pa7 - ð_mdc_pc1 ð_rxd0_pc4 ð_rxd1_pc5 ð_tx_en_pg11 ð_txd1_pg12 ð_txd0_pg13 >; pinctrl-names = "default"; + phy-connection-type = "rmii"; + phy-handle = <ð_phy>; + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; + pinctrl-names = "default"; + + eth_phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0x00>; + }; }; zephyr_udc0: &usbotg_hs { diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts index 3a3745c5a7d5..001d8509059e 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts @@ -86,6 +86,54 @@ &i2c1 { status = "okay"; + + pf1550: pmic@8 { + status = "okay"; + reg = <0x8>; + compatible = "nxp,pf1550"; + + pmic_regulators: regulators { + status = "okay"; + compatible = "nxp,pf1550-regulator"; + pf1550_sw1: BUCK1 { + regulator-init-microvolt = <3000000>; + regulator-boot-on; + }; + pf1550_sw2: BUCK2 { + regulator-init-microvolt = <3300000>; + regulator-boot-on; + }; + pf1550_sw3: BUCK3 { + regulator-init-microvolt = <3300000>; + regulator-init-microamp = <2000000>; + regulator-boot-on; + }; + pf1550_ldo1: LDO1 { + regulator-init-microvolt = <1000000>; + regulator-boot-on; + }; + pf1550_ldo2: LDO2 { + regulator-init-microvolt = <1800000>; + regulator-boot-on; + }; + pf1550_ldo3: LDO3 { + regulator-init-microvolt = <1200000>; + regulator-boot-on; + }; + }; + + pmic_charger: charger { + status = "okay"; + compatible = "nxp,pf1550-charger"; + constant-charge-current-max-microamp = <100000>; + constant-charge-voltage-max-microvolt = <4200000>; + pf1550,int-gpios = <&gpiok 0 0>; + pf1550,led-behaviour = "manual-off"; + pf1550,system-voltage-min-threshold-microvolt = <3500000>; + pf1550,thermistor-monitoring-mode = "thermistor"; + pf1550,vbus-current-limit-microamp = <1500000>; + }; + }; }; /* Only one should be enabled */ diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml deleted file mode 100644 index e4179c6e5b9c..000000000000 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: arduino_portenta_h7/stm32h747xx/m7 -name: Arduino Portenta H7 (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -ram: 512 -flash: 1024 -supported: - - gpio -vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml new file mode 100644 index 000000000000..7dc36b141900 --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml @@ -0,0 +1,18 @@ +identifier: arduino_portenta_h7@1.0.0/stm32h747xx/m7 +name: Arduino Portenta H7 (M7) rev. 1.0.0 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 1024 +supported: + - gpio + - netif:eth + - i2c + - spi + - qspi + - memc + - usb_device +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml new file mode 100644 index 000000000000..456ae5871e3b --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml @@ -0,0 +1,19 @@ +identifier: arduino_portenta_h7@4.10.0/stm32h747xx/m7 +name: Arduino Portenta H7 (M7) rev. 4.10.0 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 1024 +supported: + - gpio + - netif:eth + - i2c + - spi + - qspi + - memc + - usb_cdc + - usb_device +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig index acc978d70c98..a67b6f27c001 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 # Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y +CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO=y # Enable GPIO CONFIG_GPIO=y diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst index 2d1d167065e7..85d3212a616b 100644 --- a/boards/arduino/portenta_h7/doc/index.rst +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_portenta_h7_board: - -Arduino Portenta H7 -################### +.. zephyr:board:: arduino_portenta_h7 Overview ******** @@ -19,12 +16,6 @@ Additionally, the board features: - USB OTG FS - 3 color user LEDs -.. image:: img/arduino_portenta_h7.jpeg - :width: 500px - :align: center - :height: 325px - :alt: ARDUINO_PORTENTA_H7 - More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_. More information about STM32H747XIH6 can be found here: @@ -35,40 +26,7 @@ More information about STM32H747XIH6 can be found here: Supported Features ================== -The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| EXTFLASH | on-chip | qspi | -+-----------+------------+-------------------------------------+ -| SDRAM | on-chip | sdram | -+-----------+------------+-------------------------------------+ -| USB | on-board | usb-hs | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-board | eth | -+-----------+------------+-------------------------------------+ -| RADIO | Murata 1DX | WiFi and Bluetooth module | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. +.. zephyr:board-supported-hw:: The high precision low speed external (LSE) clock is only fully supported on boards with hardware revision 4.10 or greater. By default the internal source @@ -108,7 +66,9 @@ two cores. This is done in 3 ways: to avoid potential concurrent access issues. Building and Flashing -************************* +********************* + +.. zephyr:board-supported-runners:: Applications for the ``arduino_portenta_h7`` board should be built per core target, using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target. diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4 b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4 new file mode 100644 index 000000000000..67a9f951d67f --- /dev/null +++ b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_UNO_R4 + select SOC_R7FA4M1AB3CFM diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima deleted file mode 100644 index 2fae481238c0..000000000000 --- a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_UNO_R4_MINIMA - select SOC_R7FA4M1AB3CFM diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi deleted file mode 100644 index 840ead804a42..000000000000 --- a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_UNO_R4_WIFI - select SOC_R7FA4M1AB3CFM diff --git a/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi new file mode 100644 index 000000000000..b54c4d8cfbb6 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci2_default: sci2_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = , + , + , + ; + renesas,analog-enable; + }; + }; + + pwm7_default: pwm7_default { + group1 { + /* GTIOC7A GTIOC7B */ + psels = , + ; + }; + }; +}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4.dts b/boards/arduino/uno_r4/arduino_uno_r4.dts new file mode 100644 index 000000000000..09ce3664f1d9 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4.dts @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2023 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "arduino_uno_r4-pinctrl.dtsi" +#include +#include + +/ { + model = "Arduino Uno R4 Board"; + compatible = "renesas,ra4m1", "renesas,ra"; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,entropy = &trng; + zephyr,code-partition = &code_partition; + }; +}; + +&sci2 { + status = "okay"; + pinctrl-0 = <&sci2_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + + uart2: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq0 { + interrupts = <27 12>; + status = "okay"; +}; + +&port_irq1 { + interrupts = <28 12>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&iic1 { + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <10 1>, <11 1>, <12 1>, <13 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "bootloader"; + reg = <0x00000000 0x4000>; + read-only; + }; + + code_partition: partition@4000 { + label = "code"; + reg = <0x4000 0x3C000>; + read-only; + }; + }; +}; + +&hoco { + status = "okay"; + clock-frequency = <48000000>; +}; + +&pclkblock { + clocks = <&hoco>; +}; + +&iclk { + div = <1>; +}; + +&pclka { + div = <1>; +}; + +&pclkb { + div = <2>; +}; + +&pclkc { + div = <1>; +}; + +&pclkd { + div = <1>; +}; + +&fclk { + div = <2>; +}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi deleted file mode 100644 index f9fff37eaabf..000000000000 --- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include - -/ { - model = "Arduino Uno R4 Board"; - compatible = "renesas,r7fa4m1ab3cfm"; - - chosen { - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; - }; -}; - -&sci2 { - status = "okay"; - pinctrl-0 = <&sci2_default>; - pinctrl-names = "default"; - uart2: uart { - current-speed = <115200>; - status = "okay"; - }; -}; - -&ioport1 { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "bootloader"; - reg = <0x00000000 0x4000>; - read-only; - }; - - code_partition: partition@4000 { - label = "code"; - reg = <0x4000 0x3C000>; - read-only; - }; - }; -}; - -&fcu { - status = "okay"; -}; - -&hoco { - status = "okay"; - clock-frequency = <48000000>; -}; - -&pclkblock { - clocks = <&hoco>; -}; - -&iclk { - div = <1>; -}; - -&pclka { - div = <1>; -}; - -&pclkb { - div = <2>; -}; - -&pclkc { - div = <1>; -}; - -&pclkd { - div = <1>; -}; - -&fclk { - div = <2>; -}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_defconfig new file mode 100644 index 000000000000..17e552742746 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi index 863d9e6030af..63940405a7d8 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi @@ -4,18 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - &pinctrl { - sci2_default: sci2_default { + spi1_default: spi1_default { group1 { - /* tx */ - psels = ; - drive-strength = "medium"; - }; - group2 { - /* rx */ - psels = ; + /* MOSI MISO RSPCK SSL */ + psels = , + , + , + ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4/arduino_uno_r4_minima.dts deleted file mode 100644 index d80ca6d4f1fc..000000000000 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "arduino_uno_r4_common.dtsi" -#include "arduino_uno_r4_minima-pinctrl.dtsi" - -/ { - model = "Arduino Uno R4 Minima"; - - leds { - compatible = "gpio-leds"; - led: led { - gpios = <&ioport1 11 GPIO_ACTIVE_HIGH>; - }; - }; - - aliases { - led0 = &led; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &ioport0 14 0>, /* A0 */ - <1 0 &ioport0 0 0>, /* A1 */ - <2 0 &ioport0 1 0>, /* A2 */ - <3 0 &ioport0 2 0>, /* A3 */ - <4 0 &ioport1 1 0>, /* A4 */ - <5 0 &ioport1 0 0>, /* A5 */ - <6 0 &ioport3 1 0>, /* D0 */ - <7 0 &ioport3 2 0>, /* D1 */ - <8 0 &ioport1 5 0>, /* D2 */ - <9 0 &ioport1 4 0>, /* D3 */ - <10 0 &ioport1 3 0>, /* D4 */ - <11 0 &ioport1 2 0>, /* D5 */ - <12 0 &ioport1 6 0>, /* D6 */ - <13 0 &ioport1 7 0>, /* D7 */ - <14 0 &ioport3 4 0>, /* D8 */ - <15 0 &ioport3 3 0>, /* D9 */ - <16 0 &ioport1 12 0>, /* D10 */ - <17 0 &ioport1 9 0>, /* D11 */ - <18 0 &ioport1 10 0>, /* D12 */ - <19 0 &ioport1 11 0>, /* D13 */ - <20 0 &ioport1 1 0>, /* D14 */ - <21 0 &ioport1 0 0>; /* D15 */ - }; -}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay new file mode 100644 index 000000000000..504b15973723 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2023 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "arduino_uno_r4_minima-pinctrl.dtsi" + +#include +#include +#include + +/ { + model = "Arduino Uno R4 Minima"; + + leds { + compatible = "gpio-leds"; + led: led { + gpios = <&arduino_header ARDUINO_HEADER_R3_D13 GPIO_ACTIVE_HIGH>; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led: pwm_led { + pwms = <&arduino_pwm ARDUINO_HEADER_R3_D13 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led; + pwm-led0 = &pwm_led; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = , /* P009 = CH09 */ + , /* P000 = CH00 */ + , /* P001 = CH01 */ + , /* P002 = CH02 */ + , /* P101 = CH21 */ + ; /* P100 = CH22 */ + }; + + arduino_pwm: connector-pwm { + compatible = "arduino-header-pwm"; + #pwm-cells = <3>; + pwm-map = , /* P105 = GPT1_A */ + , /* P104 = GPT1_B */ + , /* P103 = GPT2 A */ + , /* P102 = GPT2_B */ + , /* P106 = GPT0_B */ + , /* P107 = GPT0_A */ + , /* P304 = GPT7_A */ + , /* P303 = GPT7_B */ + , /* P112 = GPT3_B */ + ; /* P111 = GPT3_A */ + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +arduino_i2c: &iic1 {}; +arduino_spi: &spi1 {}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml b/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml index b106de02aa7a..7e60cd09528f 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml @@ -1,4 +1,4 @@ -identifier: arduino_uno_r4_minima +identifier: arduino_uno_r4@minima name: Arduino Uno R4 Minima type: mcu arch: arm @@ -7,5 +7,8 @@ toolchain: - gnuarmemb ram: 32 supported: + - adc - gpio + - pwm + - spi - uart diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig deleted file mode 100644 index 3c655ea376e8..000000000000 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 - -CONFIG_BUILD_OUTPUT_HEX=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -CONFIG_CLOCK_CONTROL=y - -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi index 9add47e47236..47f94cc3a0eb 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi @@ -4,18 +4,23 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - &pinctrl { - sci2_default: sci2_default { + iic0_default: iic0_default { group1 { - /* tx */ - psels = ; + /* SCL0 SDA0 */ + psels = , + ; drive-strength = "medium"; }; - group2 { - /* rx */ - psels = ; + }; + + spi0_default: spi0_default { + group1 { + /* MOSI MISO RSPCK SSL */ + psels = , + , + , + ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts b/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts deleted file mode 100644 index a3a2019990eb..000000000000 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2024 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "arduino_uno_r4_common.dtsi" -#include "arduino_uno_r4_wifi-pinctrl.dtsi" - -/ { - model = "Arduino Uno R4 WiFi"; - - leds { - compatible = "gpio-leds"; - led: led { - gpios = <&ioport1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - aliases { - led0 = &led; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &ioport0 14 0>, /* A0 */ - <1 0 &ioport0 0 0>, /* A1 */ - <2 0 &ioport0 1 0>, /* A2 */ - <3 0 &ioport0 2 0>, /* A3 */ - <4 0 &ioport1 1 0>, /* A4 */ - <5 0 &ioport1 0 0>, /* A5 */ - <6 0 &ioport3 1 0>, /* D0 */ - <7 0 &ioport3 2 0>, /* D1 */ - <8 0 &ioport1 4 0>, /* D2 */ - <9 0 &ioport1 5 0>, /* D3 */ - <10 0 &ioport1 6 0>, /* D4 */ - <11 0 &ioport1 7 0>, /* D5 */ - <12 0 &ioport1 11 0>, /* D6 */ - <13 0 &ioport1 12 0>, /* D7 */ - <14 0 &ioport3 4 0>, /* D8 */ - <15 0 &ioport3 3 0>, /* D9 */ - <16 0 &ioport1 3 0>, /* D10 */ - <17 0 &ioport4 11 0>, /* D11 */ - <18 0 &ioport4 10 0>, /* D12 */ - <19 0 &ioport1 2 0>, /* D13 */ - <20 0 &ioport1 1 0>, /* D14 */ - <21 0 &ioport1 0 0>; /* D15 */ - }; -}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay new file mode 100644 index 000000000000..f411487d080d --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "arduino_uno_r4_wifi-pinctrl.dtsi" + +#include +#include +#include + +/ { + model = "Arduino Uno R4 WiFi"; + + leds { + compatible = "gpio-leds"; + led: led { + gpios = <&arduino_header ARDUINO_HEADER_R3_D13 GPIO_ACTIVE_HIGH>; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led: pwm_led { + pwms = <&arduino_pwm ARDUINO_HEADER_R3_D13 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led; + pwm-led0 = &pwm_led; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = , /* P009 = CH09 */ + , /* P000 = CH00 */ + , /* P001 = CH01 */ + , /* P002 = CH02 */ + , /* P101 = CH21 */ + ; /* P100 = CH22 */ + }; + + arduino_pwm: connector-pwm { + compatible = "arduino-header-pwm"; + #pwm-cells = <3>; + pwm-map = , /* P104 = GPT1_B */ + , /* P105 = GPT1_A */ + , /* P106 = GPT0 B */ + , /* P107 = GPT0_A */ + , /* P111 = GPT3_A */ + , /* P112 = GPT3_B */ + , /* P304 = GPT7_A */ + , /* P303 = GPT7_B */ + , /* P103 = GPT2_A */ + , /* P411 = GPT6_A */ + , /* P410 = GPT6_B */ + ; /* P102 = GPT2_B */ + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; + }; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <14 1>, <15 1>, <16 1>, <17 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +qwiic_i2c: &iic0 {}; +arduino_i2c: &iic1 {}; +arduino_spi: &spi0 {}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml index 30d3dfb89bc4..e2e101e93abc 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml @@ -1,4 +1,4 @@ -identifier: arduino_uno_r4_wifi +identifier: arduino_uno_r4@wifi name: Arduino Uno R4 WiFi type: mcu arch: arm @@ -7,5 +7,8 @@ toolchain: - gnuarmemb ram: 32 supported: + - adc - gpio + - pwm + - spi - uart diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig deleted file mode 100644 index 48137e86d7ac..000000000000 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2024 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 - -CONFIG_BUILD_OUTPUT_HEX=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -CONFIG_CLOCK_CONTROL=y - -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/board.yml b/boards/arduino/uno_r4/board.yml index 9c168c300c22..ee0f51c47d4f 100644 --- a/boards/arduino/uno_r4/board.yml +++ b/boards/arduino/uno_r4/board.yml @@ -1,11 +1,12 @@ -boards: - - name: arduino_uno_r4_minima - full_name: Arduino UNO R4 Minima - vendor: arduino - socs: - - name: r7fa4m1ab3cfm - - name: arduino_uno_r4_wifi - full_name: Arduino UNO R4 WiFi - vendor: arduino - socs: - - name: r7fa4m1ab3cfm +board: + name: arduino_uno_r4 + full_name: Arduino UNO R4 Minima/WiFi + vendor: arduino + revision: + format: custom + default: "minima" + revisions: + - name: "minima" + - name: "wifi" + socs: + - name: r7fa4m1ab3cfm diff --git a/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp b/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp new file mode 100644 index 000000000000..c42a9e389e42 Binary files /dev/null and b/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp differ diff --git a/boards/arduino/uno_r4/doc/index.rst b/boards/arduino/uno_r4/doc/index.rst index 1b2b28385bae..71dcd0d94e48 100644 --- a/boards/arduino/uno_r4/doc/index.rst +++ b/boards/arduino/uno_r4/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_uno_r4: - -Arduino UNO R4 -############## +.. zephyr:board:: arduino_uno_r4 Overview ******** @@ -23,20 +20,13 @@ Hardware Supported Features ================== -The Arduino UNO R4 Minima/Wifi board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| UART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ +.. zephyr:board-supported-hw:: Programming and debugging ************************* +.. zephyr:board-supported-runners:: + Debug adapter ============= @@ -60,12 +50,12 @@ Here is an example for building and flashing the :zephyr:code-sample:`blinky` ap .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: arduino_uno_r4_minima + :board: arduino_uno_r4@minima :goals: build flash .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: arduino_uno_r4_wifi + :board: arduino_uno_r4@wifi :goals: build flash Debugging @@ -77,13 +67,13 @@ Also, see the instructions specific to the debug server that you use. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: arduino_uno_r4_minima + :board: arduino_uno_r4@minima :maybe-skip-config: :goals: debug .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: arduino_uno_r4_wifi + :board: arduino_uno_r4@wifi :maybe-skip-config: :goals: debug diff --git a/boards/arduino/uno_r4/revision.cmake b/boards/arduino/uno_r4/revision.cmake new file mode 100644 index 000000000000..f148e05dd0ab --- /dev/null +++ b/boards/arduino/uno_r4/revision.cmake @@ -0,0 +1,8 @@ +set(BOARD_REVISIONS "minima" "wifi") +if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "minima") +else() + if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for arduino_uno_r4. Accepted revisions: ${BOARD_REVISIONS}") + endif() +endif() diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst index 9e665aa75cd8..150c864b3f95 100644 --- a/boards/arduino/zero/doc/index.rst +++ b/boards/arduino/zero/doc/index.rst @@ -1,7 +1,4 @@ -.. _arduino_zero: - -Arduino/Genuino Zero -#################### +.. zephyr:board:: arduino_zero Overview ******** @@ -10,10 +7,6 @@ The Arduino Zero is a maker-friendly development board with Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. image:: img/arduino_zero.jpg - :align: center - :alt: Arduino Zero - Hardware ******** @@ -28,37 +21,7 @@ Hardware Supported Features ================== -The arduino_zero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| DAC | on-chip | Digital to analogue converter | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arduino/zero/arduino_zero_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -111,6 +74,8 @@ Arduino Zero, the DAC is available on pin A0. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The Arduino Zero comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMD21 chip and is supported by OpenOCD. diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst index 8fcc4d07b0ec..080d316e6b78 100644 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst +++ b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst @@ -82,7 +82,7 @@ Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchro .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: fvp_baser_aemv8r_aarch32 + :board: fvp_baser_aemv8r/fvp_aemv8r_aarch32 :goals: build This will build an image with the synchronization sample app. diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst index 724ee182cc9a..0f9a28d0a810 100644 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst +++ b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst @@ -91,7 +91,7 @@ Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchro .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: fvp_baser_aemv8r + :board: fvp_baser_aemv8r/fvp_aemv8r_aarch64 :goals: build This will build an image with the synchronization sample app. diff --git a/boards/arm/mps2/CMakeLists.txt b/boards/arm/mps2/CMakeLists.txt index 2f6cea861c66..7a2209df8f89 100644 --- a/boards/arm/mps2/CMakeLists.txt +++ b/boards/arm/mps2/CMakeLists.txt @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -zephyr_library() -zephyr_library_sources(pinmux.c) - if(CONFIG_BOARD_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP) # Building a firmware image for CPU1: this requires a binary # for CPU0, which will boot the device and wake up CPU1. diff --git a/boards/arm/mps2/board.cmake b/boards/arm/mps2/board.cmake index b52e1958cf4e..98e34a997487 100644 --- a/boards/arm/mps2/board.cmake +++ b/boards/arm/mps2/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates if(CONFIG_BOARD_MPS2_AN385) set(SUPPORTED_EMU_PLATFORMS qemu armfvp) @@ -48,6 +48,8 @@ elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG # TF-M (Secure) & Zephyr (Non Secure) image (when running # in-tree tests). set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") + + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) elseif(CONFIG_OPENAMP) set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf") elseif(CONFIG_BOARD_MPS2_AN521_CPU1) diff --git a/boards/arm/mps2/mps2-pinctrl.dtsi b/boards/arm/mps2/mps2-pinctrl.dtsi new file mode 100644 index 000000000000..da259040e975 --- /dev/null +++ b/boards/arm/mps2/mps2-pinctrl.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /omit-if-no-ref/ uart3_default: uart3_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ uart4_default: uart4_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi0_default: spi0_default { + group1 { + pinmux = , , + ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi1_default: spi1_default { + group1 { + pinmux = , , + ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon0_default: sbcon0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon1_default: sbcon1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; +}; diff --git a/boards/arm/mps2/mps2_an383.yaml b/boards/arm/mps2/mps2_an383.yaml index c7e2ae8ba3fb..249225737754 100644 --- a/boards/arm/mps2/mps2_an383.yaml +++ b/boards/arm/mps2/mps2_an383.yaml @@ -8,7 +8,6 @@ simulation: toolchain: - zephyr - gnuarmemb - - xtools supported: - counter - netif:serial-net diff --git a/boards/arm/mps2/mps2_an386.yaml b/boards/arm/mps2/mps2_an386.yaml index c241948ce498..f71e166e683d 100644 --- a/boards/arm/mps2/mps2_an386.yaml +++ b/boards/arm/mps2/mps2_an386.yaml @@ -8,7 +8,6 @@ simulation: toolchain: - zephyr - gnuarmemb - - xtools supported: - counter - gpio diff --git a/boards/arm/mps2/mps2_an500.yaml b/boards/arm/mps2/mps2_an500.yaml index 243fc64083df..cc4c713d799f 100644 --- a/boards/arm/mps2/mps2_an500.yaml +++ b/boards/arm/mps2/mps2_an500.yaml @@ -8,7 +8,6 @@ simulation: toolchain: - zephyr - gnuarmemb - - xtools supported: - counter - gpio diff --git a/boards/arm/mps2/mps2_an521-common.dtsi b/boards/arm/mps2/mps2_an521-common.dtsi index 5b1959ff5fe3..b96f1144982a 100644 --- a/boards/arm/mps2/mps2_an521-common.dtsi +++ b/boards/arm/mps2/mps2_an521-common.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Linaro Limited + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -112,6 +113,8 @@ uart3: uart@203000 { interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; }; uart4: uart@204000 { @@ -121,6 +124,8 @@ uart4: uart@204000 { interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; }; i2c_touch: i2c@207000 { @@ -145,6 +150,8 @@ i2c_shield0: i2c@20c000 { #address-cells = <1>; #size-cells = <0>; reg = <0x20c000 0x1000>; + pinctrl-0 = <&sbcon0_default>; + pinctrl-names = "default"; }; i2c_shield1: i2c@20d000 { @@ -153,10 +160,12 @@ i2c_shield1: i2c@20d000 { #address-cells = <1>; #size-cells = <0>; reg = <0x20d000 0x1000>; + pinctrl-0 = <&sbcon1_default>; + pinctrl-names = "default"; }; gpio_led0: mps2_fpgaio@302000 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302000 0x4>; gpio-controller; @@ -165,16 +174,17 @@ gpio_led0: mps2_fpgaio@302000 { }; gpio_button: mps2_fpgaio@302008 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps2_fpgaio@30204c { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x30204c 0x4>; gpio-controller; @@ -189,3 +199,8 @@ eth0: eth@2000000 { reg = <0x2000000 0x100000>; interrupts = <48 3>; }; + +pinctrl: pinctrl { + compatible = "arm,mps2-pinctrl"; + status = "okay"; +}; diff --git a/boards/arm/mps2/mps2_an521_cpu0.dts b/boards/arm/mps2/mps2_an521_cpu0.dts index 2bb956645caf..532384377da5 100644 --- a/boards/arm/mps2/mps2_an521_cpu0.dts +++ b/boards/arm/mps2/mps2_an521_cpu0.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2019 Linaro Limited + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -128,3 +129,5 @@ &uart1 { status = "okay"; }; + +#include "mps2-pinctrl.dtsi" diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml index 2e73e6b113ab..e511285c190f 100644 --- a/boards/arm/mps2/mps2_an521_cpu0.yaml +++ b/boards/arm/mps2/mps2_an521_cpu0.yaml @@ -15,7 +15,6 @@ supported: testing: default: true ignore_tags: - - drivers - bluetooth - net - timer diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.dts b/boards/arm/mps2/mps2_an521_cpu0_ns.dts index e2b24cd9ba57..d67718fcc59a 100644 --- a/boards/arm/mps2/mps2_an521_cpu0_ns.dts +++ b/boards/arm/mps2/mps2_an521_cpu0_ns.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2019 Linaro Limited + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -142,3 +143,4 @@ &nvic { arm,num-irq-priority-bits = <3>; }; +#include "mps2-pinctrl.dtsi" diff --git a/boards/arm/mps2/mps2_an521_cpu1.dts b/boards/arm/mps2/mps2_an521_cpu1.dts index 311694ca3999..24b39b50978b 100644 --- a/boards/arm/mps2/mps2_an521_cpu1.dts +++ b/boards/arm/mps2/mps2_an521_cpu1.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2019 Linaro Limited + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -144,3 +145,5 @@ &nvic { arm,num-irq-priority-bits = <3>; }; + +#include "mps2-pinctrl.dtsi" diff --git a/boards/arm/mps2/mps2_base.dtsi b/boards/arm/mps2/mps2_base.dtsi index 4d8106aa9126..021373fac43a 100644 --- a/boards/arm/mps2/mps2_base.dtsi +++ b/boards/arm/mps2/mps2_base.dtsi @@ -1,4 +1,4 @@ -/* Copyright 2024 Arm Limited and/or its affiliates */ +/* Copyright 2024-2025 Arm Limited and/or its affiliates */ /* SPDX-License-Identifier: Apache-2.0 */ / { @@ -145,6 +145,8 @@ interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; }; wdog0: wdog@40008000 { @@ -160,6 +162,8 @@ interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; }; gpio0: gpio@40010000 { @@ -225,6 +229,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40029000 0x1000>; + pinctrl-0 = <&sbcon0_default>; + pinctrl-names = "default"; }; i2c_shield1: i2c@4002a000 { @@ -233,10 +239,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x4002a000 0x1000>; + pinctrl-0 = <&sbcon1_default>; + pinctrl-names = "default"; }; gpio_led0: mps2_fpgaio@40028000 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x40028000 0x4>; gpio-controller; #gpio-cells = <1>; @@ -244,23 +252,31 @@ }; gpio_button: mps2_fpgaio@40028008 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x40028008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps2_fpgaio@4002804c { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x4002804c 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <10>; }; }; + + pinctrl: pinctrl { + compatible = "arm,mps2-pinctrl"; + status = "okay"; + }; }; &nvic { arm,num-irq-priority-bits = <3>; }; + +#include "mps2-pinctrl.dtsi" diff --git a/boards/arm/mps2/pinmux.c b/boards/arm/mps2/pinmux.c deleted file mode 100644 index 6cf939830728..000000000000 --- a/boards/arm/mps2/pinmux.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -/** - * @brief Pinmux driver for ARM MPS2 AN385 Board - * - * The ARM MPS2 AN385 Board has 4 GPIO controllers. These controllers - * are responsible for pin muxing, input/output, pull-up, etc. - * - * All GPIO controller pins are exposed via the following sequence of pin - * numbers: - * Pins 0 - 15 are for GPIO0 - * Pins 16 - 31 are for GPIO1 - * Pins 32 - 47 are for GPIO2 - * Pins 48 - 51 are for GPIO3 - * - * For the GPIO controllers configuration ARM MPS2 AN385 Board follows the - * Arduino compliant pin out. - */ - -#define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0))) -#define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1))) -#define CMSDK_AHB_GPIO2_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2))) -#define CMSDK_AHB_GPIO3_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3))) - -/* - * This is the mapping from the ARM MPS2 AN385 Board pins to GPIO - * controllers. - * - * D0 : EXT_0 - * D1 : EXT_4 - * D2 : EXT_2 - * D3 : EXT_3 - * D4 : EXT_1 - * D5 : EXT_6 - * D6 : EXT_7 - * D7 : EXT_8 - * D8 : EXT_9 - * D9 : EXT_10 - * D10 : EXT_12 - * D11 : EXT_13 - * D12 : EXT_14 - * D13 : EXT_11 - * D14 : EXT_15 - * D15 : EXT_5 - * D16 : EXT_16 - * D17 : EXT_17 - * D18 : EXT_18 - * D19 : EXT_19 - * D20 : EXT_20 - * D21 : EXT_21 - * D22 : EXT_22 - * D23 : EXT_23 - * D24 : EXT_24 - * D25 : EXT_25 - * D26 : EXT_26 - * D27 : EXT_30 - * D28 : EXT_28 - * D29 : EXT_29 - * D30 : EXT_27 - * D31 : EXT_32 - * D32 : EXT_33 - * D33 : EXT_34 - * D34 : EXT_35 - * D35 : EXT_36 - * D36 : EXT_38 - * D37 : EXT_39 - * D38 : EXT_40 - * D39 : EXT_44 - * D40 : EXT_41 - * D41 : EXT_31 - * D42 : EXT_37 - * D43 : EXT_42 - * D44 : EXT_43 - * D45 : EXT_45 - * D46 : EXT_46 - * D47 : EXT_47 - * D48 : EXT_48 - * D49 : EXT_49 - * D50 : EXT_50 - * D51 : EXT_51 - * - * UART_3_RX : D0 - * UART_3_TX : D1 - * SPI_3_CS : D10 - * SPI_3_MOSI : D11 - * SPI_3_MISO : D12 - * SPI_3_SCLK : D13 - * I2C_3_SDA : D14 - * I2C_3_SCL : D15 - * UART_4_RX : D26 - * UART_4_TX : D30 - * SPI_4_CS : D36 - * SPI_4_MOSI : D37 - * SPI_4_MISO : D38 - * SPI_4_SCK : D39 - * I2C_4_SDA : D40 - * I2C_4_SCL : D41 - * - */ -static void arm_mps2_pinmux_defaults(void) -{ - uint32_t gpio_0 = 0U; - uint32_t gpio_1 = 0U; - uint32_t gpio_2 = 0U; - - /* Set GPIO Alternate Functions */ - - gpio_0 = (1<<0) /* Shield 0 UART 3 RXD */ - | (1<<4) /* Shield 0 UART 3 TXD */ - | (1<<5) /* Shield 0 I2C SCL SBCON2 */ - | (1<<15) /* Shield 0 I2C SDA SBCON2 */ - | (1<<11) /* Shield 0 SPI 3 SCK */ - | (1<<12) /* Shield 0 SPI 3 SS */ - | (1<<13) /* Shield 0 SPI 3 MOSI */ - | (1<<14); /* Shield 0 SPI 3 MISO */ - - CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; - - gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */ - | (1<<14) /* Shield 1 UART 4 TXD */ - | (1<<15) /* Shield 1 I2C SCL SBCON3 */ - | (1<<0) /* ADC SPI 2 SS */ - | (1<<1) /* ADC SPI 2 MISO */ - | (1<<2) /* ADC SPI 2 MOSI */ - | (1<<3) /* ADC SPI 2 SCK */ - | (1<<5) /* USER BUTTON 0 */ - | (1<<6); /* USER BUTTON 1 */ - - CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; - - gpio_2 = (1<<9) /* Shield 1 I2C SDA SBCON3 */ - | (1<<6) /* Shield 1 SPI 4 SS */ - | (1<<7) /* Shield 1 SPI 4 MOSI */ - | (1<<8) /* Shield 1 SPI 4 MISO */ - | (1<<12); /* Shield 1 SPI 4 SCK */ - - CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2; -} - -static int arm_mps2_pinmux_init(void) -{ - - arm_mps2_pinmux_defaults(); - - return 0; -} - -SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/mps3/Kconfig.defconfig b/boards/arm/mps3/Kconfig.defconfig index 4ce6cf0c910b..014b80f307fb 100644 --- a/boards/arm/mps3/Kconfig.defconfig +++ b/boards/arm/mps3/Kconfig.defconfig @@ -1,5 +1,5 @@ # Copyright (c) 2018-2021 Linaro Limited -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP @@ -19,4 +19,14 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL +if ROMSTART_RELOCATION_ROM && (BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP) + +config ROMSTART_REGION_ADDRESS + default $(dt_nodelabel_reg_addr_hex,itcm) + +config ROMSTART_REGION_SIZE + default $(dt_nodelabel_reg_size_hex,itcm,0,k) + +endif + endif diff --git a/boards/arm/mps3/board.cmake b/boards/arm/mps3/board.cmake index ca090a832fc8..e6204c4c2eab 100644 --- a/boards/arm/mps3/board.cmake +++ b/boards/arm/mps3/board.cmake @@ -1,5 +1,5 @@ # Copyright (c) 2021 Linaro -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 # The FVP variant must be used to enable Ethos-U55 NPU support, but QEMU also @@ -37,6 +37,10 @@ elseif(CONFIG_BOARD_MPS3_CORSTONE310_FVP OR CONFIG_BOARD_MPS3_CORSTONE310_FVP_NS set(ARMFVP_FLAGS # default is '0x11000000' but should match cpu.INITSVTOR which is 0. -C mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0 + # default is 0x8, this change is needed since we split flash into itcm + # and sram and it reduces the number of available mpu regions causing a + # few MPU tests to fail. + -C cpu0.MPU_S=16 ) endif() endif() @@ -48,6 +52,8 @@ if (CONFIG_BUILD_WITH_TFM) # TF-M (Secure) & Zephyr (Non Secure) image (when running # in-tree tests). set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") + + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) endif() # FVP Parameters diff --git a/boards/arm/mps3/mps3-pinctrl.dtsi b/boards/arm/mps3/mps3-pinctrl.dtsi new file mode 100644 index 000000000000..17b143ae6442 --- /dev/null +++ b/boards/arm/mps3/mps3-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /omit-if-no-ref/ uart3_default: uart3_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ uart4_default: uart4_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi3_default: spi3_default { + group1 { + pinmux = , , + ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon2_default: sbcon2_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon3_default: sbcon3_default { + group1 { + pinmux = , ; + input-enable; + }; + }; +}; diff --git a/boards/arm/mps3/mps3_common.dtsi b/boards/arm/mps3/mps3_common.dtsi index 798af2633103..3348101bc723 100644 --- a/boards/arm/mps3/mps3_common.dtsi +++ b/boards/arm/mps3/mps3_common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,3 +104,4 @@ &nvic { arm,num-irq-priority-bits = <3>; }; +#include "mps3-pinctrl.dtsi" diff --git a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi index 6fd5c7acd402..d46f6c602cf1 100644 --- a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi +++ b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2021 Linaro Limited - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -85,6 +85,8 @@ spi_shield0: spi@9203000 { clocks = <&sysclk>; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&spi3_default>; + pinctrl-names = "default"; }; spi_shield1: spi@9204000 { @@ -95,6 +97,8 @@ spi_shield1: spi@9204000 { clocks = <&sysclk>; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&spi4_default>; + pinctrl-names = "default"; }; i2c_shield0: i2c@9205000 { @@ -103,6 +107,8 @@ i2c_shield0: i2c@9205000 { #address-cells = <1>; #size-cells = <0>; reg = <0x9205000 0x1000>; + pinctrl-0 = <&sbcon2_default>; + pinctrl-names = "default"; }; i2c_shield1: i2c@9206000 { @@ -111,6 +117,8 @@ i2c_shield1: i2c@9206000 { #address-cells = <1>; #size-cells = <0>; reg = <0x9206000 0x1000>; + pinctrl-0 = <&sbcon3_default>; + pinctrl-names = "default"; }; i2c_ddr4_eeprom: i2c@9208000 { @@ -122,7 +130,7 @@ i2c_ddr4_eeprom: i2c@9208000 { }; gpio_led0: mps3_fpgaio@9302000 { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x9302000 0x4>; gpio-controller; @@ -131,16 +139,17 @@ gpio_led0: mps3_fpgaio@9302000 { }; gpio_button: mps3_fpgaio@9302008 { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x9302008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps3_fpgaio@930204c { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x930204c 0x4>; gpio-controller; @@ -182,6 +191,8 @@ uart3: uart@9306000 { interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; }; uart4: uart@9307000 { @@ -191,6 +202,8 @@ uart4: uart@9307000 { interrupt-names = "tx", "rx"; clocks = <&sysclk>; current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; }; uart5: uart@9308000 { @@ -202,3 +215,8 @@ uart5: uart@9308000 { clocks = <&sysclk>; current-speed = <115200>; }; + +pinctrl: pinctrl { + compatible = "arm,mps3-pinctrl"; + status = "okay"; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an547.dts b/boards/arm/mps3/mps3_corstone300_an547.dts index ae71ddf72825..55188180f0cf 100644 --- a/boards/arm/mps3/mps3_corstone300_an547.dts +++ b/boards/arm/mps3/mps3_corstone300_an547.dts @@ -1,6 +1,6 @@ /* * Copyright (c) 2018-2021 Linaro Limited - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an547"; @@ -95,3 +94,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_an547.yaml b/boards/arm/mps3/mps3_corstone300_an547.yaml index 27d74d8c571b..b63d2b1211ce 100644 --- a/boards/arm/mps3/mps3_corstone300_an547.yaml +++ b/boards/arm/mps3/mps3_corstone300_an547.yaml @@ -1,6 +1,6 @@ # # Copyright (c) 2019-2021 Linaro Limited -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # # SPDX-License-Identifier: Apache-2.0 # @@ -20,6 +20,7 @@ toolchain: supported: - gpio testing: + default: true ignore_tags: - drivers - bluetooth diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns.dts b/boards/arm/mps3/mps3_corstone300_an547_ns.dts index 5a4e0031946c..9540682e37b2 100644 --- a/boards/arm/mps3/mps3_corstone300_an547_ns.dts +++ b/boards/arm/mps3/mps3_corstone300_an547_ns.dts @@ -1,6 +1,6 @@ /* * Copyright (c) 2018-2021 Linaro Limited - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an547"; @@ -100,3 +99,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_an552.dts b/boards/arm/mps3/mps3_corstone300_an552.dts index 7c7ec8d02a5c..51aabcda2fa4 100644 --- a/boards/arm/mps3/mps3_corstone300_an552.dts +++ b/boards/arm/mps3/mps3_corstone300_an552.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an552"; @@ -94,3 +93,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns.dts b/boards/arm/mps3/mps3_corstone300_an552_ns.dts index 17e9d259bca9..7b8bab99ff6d 100644 --- a/boards/arm/mps3/mps3_corstone300_an552_ns.dts +++ b/boards/arm/mps3/mps3_corstone300_an552_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an552"; @@ -99,3 +98,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_fvp.dts b/boards/arm/mps3/mps3_corstone300_fvp.dts index eff11378c616..886b8d776291 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp.dts +++ b/boards/arm/mps3/mps3_corstone300_fvp.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-fvp"; @@ -94,3 +93,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_fvp.yaml b/boards/arm/mps3/mps3_corstone300_fvp.yaml index 07c8c8a131e1..520e69fc2712 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp.yaml +++ b/boards/arm/mps3/mps3_corstone300_fvp.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone300/fvp @@ -16,8 +16,9 @@ toolchain: supported: - gpio testing: + default: true + timeout_multiplier: 4 ignore_tags: - - drivers - bluetooth - net - timer diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.dts b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts index 8a9704cae3a8..d2be764eb502 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp_ns.dts +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-fvp"; @@ -99,3 +98,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml index 52de52a2a1b1..f0561b716c3f 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone300/fvp/ns @@ -12,5 +12,6 @@ toolchain: - zephyr testing: default: true + timeout_multiplier: 4 only_tags: - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone310_an555.dts b/boards/arm/mps3/mps3_corstone310_an555.dts index f16aff58eae8..47c2a9626a81 100644 --- a/boards/arm/mps3/mps3_corstone310_an555.dts +++ b/boards/arm/mps3/mps3_corstone310_an555.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an555"; @@ -20,8 +19,8 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &dtcm; - zephyr,flash = &itcm; + zephyr,sram = &sram; + zephyr,flash = &isram; }; cpus { @@ -94,3 +93,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone310_an555_defconfig b/boards/arm/mps3/mps3_corstone310_an555_defconfig index f5607f3da4c2..cfea436df56a 100644 --- a/boards/arm/mps3/mps3_corstone310_an555_defconfig +++ b/boards/arm/mps3/mps3_corstone310_an555_defconfig @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 CONFIG_RUNTIME_NMI=y @@ -15,3 +15,5 @@ CONFIG_SERIAL=y # Build a Secure firmware image CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns.dts b/boards/arm/mps3/mps3_corstone310_an555_ns.dts index 786ca6d9eb16..4a910777e113 100644 --- a/boards/arm/mps3/mps3_corstone310_an555_ns.dts +++ b/boards/arm/mps3/mps3_corstone310_an555_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-an555"; @@ -99,3 +98,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone310_fvp.dts b/boards/arm/mps3/mps3_corstone310_fvp.dts index 6ad45b5f9735..585a7297d72c 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp.dts +++ b/boards/arm/mps3/mps3_corstone310_fvp.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-fvp"; @@ -20,8 +19,8 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &dtcm; - zephyr,flash = &itcm; + zephyr,sram = &sram; + zephyr,flash = &isram; }; cpus { @@ -94,3 +93,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone310_fvp.yaml b/boards/arm/mps3/mps3_corstone310_fvp.yaml index be08cf95aca2..3a9cc5e70a76 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp.yaml +++ b/boards/arm/mps3/mps3_corstone310_fvp.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone310/fvp @@ -16,6 +16,8 @@ toolchain: supported: - gpio testing: + default: true + timeout_multiplier: 4 ignore_tags: - drivers - bluetooth diff --git a/boards/arm/mps3/mps3_corstone310_fvp_defconfig b/boards/arm/mps3/mps3_corstone310_fvp_defconfig index f5607f3da4c2..cfea436df56a 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp_defconfig +++ b/boards/arm/mps3/mps3_corstone310_fvp_defconfig @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 CONFIG_RUNTIME_NMI=y @@ -15,3 +15,5 @@ CONFIG_SERIAL=y # Build a Secure firmware image CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.dts b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts index acc9b5fb737e..9cd73ee3959f 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp_ns.dts +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 Arm Limited and/or its affiliates + * Copyright 2024-2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include -#include "mps3_common.dtsi" / { compatible = "arm,mps3-fvp"; @@ -99,3 +98,4 @@ }; }; }; +#include "mps3_common.dtsi" diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml index 307329bcf902..bfbc54dc16b8 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone310/fvp/ns @@ -12,5 +12,6 @@ toolchain: - zephyr testing: default: true + timeout_multiplier: 4 only_tags: - trusted-firmware-m diff --git a/boards/arm/v2m_beetle/CMakeLists.txt b/boards/arm/v2m_beetle/CMakeLists.txt deleted file mode 100644 index 9bc25bae4c64..000000000000 --- a/boards/arm/v2m_beetle/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(pinmux.c) diff --git a/boards/arm/v2m_beetle/pinmux.c b/boards/arm/v2m_beetle/pinmux.c deleted file mode 100644 index 856239761b80..000000000000 --- a/boards/arm/v2m_beetle/pinmux.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -/** - * @brief Pinmux driver for ARM V2M Beetle Board - * - * The ARM V2M Beetle Board has 4 GPIO controllers. These controllers - * are responsible for pin muxing, input/output, pull-up, etc. - * - * The GPIO controllers 2 and 3 are reserved and therefore not exposed by - * this driver. - * - * All GPIO controller exposed pins are exposed via the following sequence of - * pin numbers: - * Pins 0 - 15 are for GPIO0 - * Pins 16 - 31 are for GPIO1 - * - * For the exposed GPIO controllers ARM V2M Beetle Board follows the Arduino - * compliant pin out. - */ - -#define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0))) -#define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1))) - -/* - * This is the mapping from the ARM V2M Beetle Board pins to GPIO - * controllers. - * - * D0 : P0_0 - * D1 : P0_1 - * D2 : P0_2 - * D3 : P0_3 - * D4 : P0_4 - * D5 : P0_5 - * D6 : P0_6 - * D7 : P0_7 - * D8 : P0_8 - * D9 : P0_9 - * D10 : P0_10 - * D11 : P0_11 - * D12 : P0_12 - * D13 : P0_13 - * D14 : P0_14 - * D15 : P0_15 - * D16 : P1_0 - * D17 : P1_1 - * D18 : P1_2 - * D19 : P1_3 - * D20 : P1_4 - * D21 : P1_5 - * D22 : P1_6 - * D23 : P1_7 - * D24 : P1_8 - * D25 : P1_9 - * D26 : P1_10 - * D27 : P1_11 - * D28 : P1_12 - * D29 : P1_13 - * D30 : P1_14 - * D31 : P1_15 - * - * UART_0_RX : D0 - * UART_0_TX : D1 - * SPI_0_CS : D10 - * SPI_0_MOSI : D11 - * SPI_0_MISO : D12 - * SPI_0_SCLK : D13 - * I2C_0_SCL : D14 - * I2C_0_SDA : D15 - * UART_1_RX : D16 - * UART_1_TX : D17 - * SPI_1_CS : D18 - * SPI_1_MOSI : D19 - * SPI_1_MISO : D20 - * SPI_1_SCK : D21 - * I2C_1_SDA : D22 - * I2C_1_SCL : D23 - * - */ -static void arm_v2m_beetle_pinmux_defaults(void) -{ - uint32_t gpio_0 = 0U; - uint32_t gpio_1 = 0U; - - /* Set GPIO Alternate Functions */ - - gpio_0 = (1<<0); /* Shield 0 UART 0 RXD */ - gpio_0 |= (1<<1); /* Shield 0 UART 0 TXD */ - gpio_0 |= (1<<14); /* Shield 0 I2C SDA SBCON2 */ - gpio_0 |= (1<<15); /* Shield 0 I2C SCL SBCON2 */ - gpio_0 |= (1<<10); /* Shield 0 SPI_3 nCS */ - gpio_0 |= (1<<11); /* Shield 0 SPI_3 MOSI */ - gpio_0 |= (1<<12); /* Shield 0 SPI_3 MISO */ - gpio_0 |= (1<<13); /* Shield 0 SPI_3 SCK */ - - CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; - - gpio_1 = (1<<0); /* UART 1 RXD */ - gpio_1 |= (1<<1); /* UART 1 TXD */ - gpio_1 |= (1<<6); /* Shield 1 I2C SDA */ - gpio_1 |= (1<<7); /* Shield 1 I2C SCL */ - gpio_1 |= (1<<2); /* ADC SPI_1 nCS */ - gpio_1 |= (1<<3); /* ADC SPI_1 MOSI */ - gpio_1 |= (1<<4); /* ADC SPI_1 MISO */ - gpio_1 |= (1<<5); /* ADC SPI_1 SCK */ - - gpio_1 |= (1<<8); /* QSPI CS 2 */ - gpio_1 |= (1<<9); /* QSPI CS 1 */ - gpio_1 |= (1<<10); /* QSPI IO 0 */ - gpio_1 |= (1<<11); /* QSPI IO 1 */ - gpio_1 |= (1<<12); /* QSPI IO 2 */ - gpio_1 |= (1<<13); /* QSPI IO 3 */ - gpio_1 |= (1<<14); /* QSPI SCK */ - - CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; - - /* Set the ARD_PWR_EN GPIO1[15] as an output */ - CMSDK_AHB_GPIO1_DEV->outenableset |= (0x1 << 15); - /* Set on 3v3 (for ARDUINO HDR compliance) */ - CMSDK_AHB_GPIO1_DEV->data |= (0x1 << 15); -} - -static int arm_v2m_beetle_pinmux_init(void) -{ - - arm_v2m_beetle_pinmux_defaults(); - - return 0; -} - -SYS_INIT(arm_v2m_beetle_pinmux_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi b/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi new file mode 100644 index 000000000000..3bd342daac9a --- /dev/null +++ b/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /omit-if-no-ref/ uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ uart1_default: uart1_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi1_default: spi1_default { + group1 { + pinmux = , , ; + + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon0_default: sbcon0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon1_default: sbcon1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; +}; diff --git a/boards/arm/v2m_beetle/v2m_beetle.dts b/boards/arm/v2m_beetle/v2m_beetle.dts index abb2687701c6..8e8dc71872af 100644 --- a/boards/arm/v2m_beetle/v2m_beetle.dts +++ b/boards/arm/v2m_beetle/v2m_beetle.dts @@ -74,6 +74,8 @@ interrupts = <0 3>; clocks = <&sysclk &syscon>; current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; }; uart1: uart@40005000 { @@ -82,6 +84,8 @@ interrupts = <2 3>; clocks = <&sysclk &syscon>; current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; }; wdog0: wdog@40008000 { @@ -131,9 +135,15 @@ reg = <0x4001f000 0x1000>; #clock-cells = <0>; }; + + pinctrl: pinctrl { + compatible = "arm,mps3-pinctrl"; + status = "okay"; + }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; +#include "v2m_beetle-pinctrl.dtsi" diff --git a/boards/aspeed/ast1030_evb/doc/index.rst b/boards/aspeed/ast1030_evb/doc/index.rst index 1c23d7d2644f..1faa0185e27f 100644 --- a/boards/aspeed/ast1030_evb/doc/index.rst +++ b/boards/aspeed/ast1030_evb/doc/index.rst @@ -26,22 +26,7 @@ Hardware Supported Features ================== -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in -:zephyr_file:`boards/aspeed/ast1030_evb/ast1030_evb_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -63,6 +48,8 @@ UART5 is configured for serial logs. The default serial setup is 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + This board comes with a JTAG port which facilitates debugging using a single physical connection. Flashing diff --git a/boards/atmarktechno/degu_evk/board.cmake b/boards/atmarktechno/degu_evk/board.cmake index 33b72c2e9693..028127e8ef02 100644 --- a/boards/atmarktechno/degu_evk/board.cmake +++ b/boards/atmarktechno/degu_evk/board.cmake @@ -2,5 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst index 1069727aa6c8..fe51eaf3f904 100644 --- a/boards/atmel/sam/sam4e_xpro/doc/index.rst +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -27,45 +27,7 @@ Hardware Supported Features ================== -The sam4e_xpro board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| AFEC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | hwinfo | -+-----------+------------+-------------------------------------+ -| HSMCI | on-chip | sdhc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -89,6 +51,8 @@ chip. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_. By default a factory new SAM4E chip will boot SAM-BA boot loader located in the ROM, not the flashed image. This is determined by the value of GPNVM1 diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst index f958a5405154..899498f61a53 100644 --- a/boards/atmel/sam/sam4l_ek/doc/index.rst +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -49,38 +49,7 @@ Hardware Supported Features ================== -The sam4l_ek board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique 120 bit serial number | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| TWIM | on-chip | i2c master port-interrupt | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb device | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -104,6 +73,8 @@ between all others headers and RS-485 port. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM4L-EK board have a Segger Embedded Debugger Unit `J-Link OB `_. This provides a debug interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst index 792c407da8cd..6f39a88367ad 100644 --- a/boards/atmel/sam/sam4s_xplained/doc/index.rst +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -23,45 +23,7 @@ Hardware Supported Features ================== -The sam4s_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SMC | on-chip | memc (PSRAM) | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -86,6 +48,8 @@ The section flashing uses the UART from the Segger USB debug connection. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM4S Xplained board comes with Segger `J-Link OB `_. This provides a debug interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst index 6c8164391768..659f793049d5 100644 --- a/boards/atmel/sam/sam_e70_xplained/doc/index.rst +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -27,53 +27,7 @@ Hardware Supported Features ================== -The sam_e70_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| AFEC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN FD | on-chip | can | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| XDMAC | on-chip | dma | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -96,6 +50,8 @@ chip. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. Support for Atmel SAM E microcontroller series was added in OpenOCD release 0.10.0, which was added in Zephyr SDK 0.9.2. diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi index d6190e050f97..8875e53e511f 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi @@ -17,6 +17,7 @@ led0 = &green_led; sw0 = &sw0_user_button; watchdog0 = &wdt; + sdhc0 = &hsmci; }; chosen { @@ -238,3 +239,17 @@ zephyr_udc0: &usbhs { pinctrl-names = "default"; }; }; + +&hsmci { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsmci_default>; + cd-gpios = <&pioc 16 GPIO_ACTIVE_LOW>; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi index 443bb39651f0..bf09abaf1d0e 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi @@ -182,4 +182,15 @@ ; }; }; + + hsmci_default: hsmci_default { + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml index 3cec4f751823..6f958557d7b6 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml @@ -18,6 +18,7 @@ supported: - i2s - pwm - netif:eth + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml index 7a70dbc58440..2007e30e92ed 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml @@ -18,6 +18,7 @@ supported: - i2s - pwm - netif:eth + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst index cb7ecbfda439..d58c6ded861e 100644 --- a/boards/atmel/sam/sam_v71_xult/doc/index.rst +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -33,53 +33,7 @@ Hardware Supported Features ================== -The sam_v71_xplained_ultra board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| AFEC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN FD | on-chip | can | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| XDMAC | on-chip | dma | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -102,6 +56,8 @@ for the console and is available as a Virtual COM Port via EDBG USB chip. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_. By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader located in the ROM, not the flashed image. This is determined by the value diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi index d5500da2bfc9..b156ff7a91fd 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi @@ -21,6 +21,7 @@ sw0 = &sw0_user_button; sw1 = &sw1_user_button; watchdog0 = &wdt; + sdhc0 = &hsmci; }; chosen { @@ -341,6 +342,20 @@ zephyr_udc0: &usbhs { status = "okay"; }; +&hsmci { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsmci_default>; + cd-gpios = <&piod 18 GPIO_ACTIVE_LOW>; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + ext1_spi: &spi0 { }; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi index fa7d49227439..fdd5ff1e8ad4 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi @@ -153,4 +153,15 @@ ; }; }; + + hsmci_default: hsmci_default { + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml index c1873f6aaaea..1e3a867ebbad 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml @@ -22,6 +22,7 @@ supported: - pwm - netif:eth - rtc + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml index b0a226550c96..68d06bd6699f 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml @@ -22,6 +22,7 @@ supported: - pwm - netif:eth - rtc + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam0/samc21n_xpro/doc/index.rst b/boards/atmel/sam0/samc21n_xpro/doc/index.rst index 678e3afa4530..094f75631ea0 100644 --- a/boards/atmel/sam0/samc21n_xpro/doc/index.rst +++ b/boards/atmel/sam0/samc21n_xpro/doc/index.rst @@ -25,53 +25,7 @@ Hardware Supported Features ================== -The samc21n_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - CAN - - on-chip - - CAN ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -129,6 +83,8 @@ driven by TCC2 instead of by GPIO. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMC21 chip and is supported by OpenOCD. diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst index 6127a37aff68..f374a15dad3e 100644 --- a/boards/atmel/sam0/samd20_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -23,47 +23,7 @@ Hardware Supported Features ================== -The samd20_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig`. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -93,6 +53,8 @@ SERCOM0 is available on the EXT1 connector. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMD20 chip and is supported by OpenOCD. diff --git a/boards/atmel/sam0/samd21_xpro/doc/index.rst b/boards/atmel/sam0/samd21_xpro/doc/index.rst index 057d6d80b8de..a7b2245e1586 100644 --- a/boards/atmel/sam0/samd21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd21_xpro/doc/index.rst @@ -23,53 +23,7 @@ Hardware Supported Features ================== -The samd21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - USB - - on-chip - - Universal Serial Bus device ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -134,6 +88,8 @@ SERCOM5 is connected to an 8 megabit SPI flash. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMD21 chip and is supported by OpenOCD. diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml index 2ffa9435ca52..cdecfc364503 100644 --- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -21,5 +21,6 @@ supported: - spi - uart - usb_device + - usbd - watchdog vendor: atmel diff --git a/boards/atmel/sam0/same54_xpro/doc/index.rst b/boards/atmel/sam0/same54_xpro/doc/index.rst index 61b127d7a1b5..3e76b6492d37 100644 --- a/boards/atmel/sam0/same54_xpro/doc/index.rst +++ b/boards/atmel/sam0/same54_xpro/doc/index.rst @@ -3,7 +3,7 @@ Overview ******** -The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and +The `SAM E54 Xplained Pro Evaluation Kit`_ is ideal for evaluation and prototyping with the SAM E54 Cortex®-M4F processor-based microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional @@ -36,61 +36,7 @@ Hardware Supported Features ================== -The same54_xpro board configuration supports the following hardware -features: - -+---------------+------------+----------------------------+ -| Interface | Controller | Driver/Component | -+===============+============+============================+ -| ADC | on-chip | adc | -+---------------+------------+----------------------------+ -| DAC | on-chip | dac | -+---------------+------------+----------------------------+ -| DMAC | on-chip | dma | -+---------------+------------+----------------------------+ -| EEPROM | i2c | eeprom, EUI-48 MAC Address | -+---------------+------------+----------------------------+ -| EIC | on-chip | interrupt_controller | -+---------------+------------+----------------------------+ -| GMAC | on-chip | ethernet, mdio | -+---------------+------------+----------------------------+ -| GPIO | on-chip | gpio | -+---------------+------------+----------------------------+ -| MPU | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVIC | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVMCTRL | on-chip | flash | -+---------------+------------+----------------------------+ -| PORT | on-chip | pinctrl | -+---------------+------------+----------------------------+ -| RTC | on-chip | timer | -+---------------+------------+----------------------------+ -| SERCOM I2C | on-chip | i2c | -+---------------+------------+----------------------------+ -| SERCOM SPI | on-chip | spi | -+---------------+------------+----------------------------+ -| SERCOM USART | on-chip | serial, console | -+---------------+------------+----------------------------+ -| Serial Number | on-chip | hwinfo | -+---------------+------------+----------------------------+ -| SYSTICK | on-chip | timer | -+---------------+------------+----------------------------+ -| TC | on-chip | counter | -+---------------+------------+----------------------------+ -| TCC | on-chip | counter, pwm | -+---------------+------------+----------------------------+ -| TRNG | on-chip | entropy | -+---------------+------------+----------------------------+ -| USB | on-chip | usb | -+---------------+------------+----------------------------+ -| WDT | on-chip | watchdog | -+---------------+------------+----------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/same54_xpro/same54_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -98,8 +44,9 @@ Pin Mapping The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These controllers are responsible for pin muxing, input/output, pull-up, etc. -For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 -Xplained Pro Schematic`_. +For more details please refer to `SAM D5x/E5x Family Datasheet (Web)`_, the `SAM E54 +Xplained Pro Schematic (Blue PCB)`_, or `SAM E54 +Xplained Pro Schematic (Red PCB)`_. .. image:: img/ATSAME54-XPRO-pinout.jpg :align: center @@ -165,6 +112,8 @@ Authentication device. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAME54 chip and is supported by OpenOCD. @@ -213,11 +162,17 @@ References .. target-notes:: -.. _Microchip website: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO +.. _SAM E54 Xplained Pro Evaluation Kit: + https://www.microchip.com/en-us/development-tool/ATSAME54-XPRO + +.. _SAM D5x/E5x Family Datasheet (Web): + https://onlinedocs.microchip.com/oxy/GUID-AA358083-AEED-4BA8-8511-9F986D3390A5-en-US-2/index.html + +.. _Sam D5x/E5x Family Datasheet (PDF): + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/UserGuides/70005321A.pdf -.. _SAM D5x/E5x Family Datasheet: - http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf +.. _SAM E54 Xplained Pro Schematic (Blue PCB): + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/BoardDesignFiles/SAM-E54-Xplained-Pro-Design-Documentation-Rev9.zip -.. _SAM E54 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip +.. _SAM E54 Xplained Pro Schematic (Red PCB): + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/BoardDesignFiles/SAM-E54-Xplained-Pro-Design-Documentation-Rev11.zip diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml index bd46418551fd..346c7fe0869e 100644 --- a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml @@ -22,4 +22,5 @@ supported: - spi - uart - usb_device + - usbd vendor: atmel diff --git a/boards/atmel/sam0/saml21_xpro/doc/index.rst b/boards/atmel/sam0/saml21_xpro/doc/index.rst index b92e1bf09a70..90ee26760882 100644 --- a/boards/atmel/sam0/saml21_xpro/doc/index.rst +++ b/boards/atmel/sam0/saml21_xpro/doc/index.rst @@ -23,50 +23,7 @@ Hardware Supported Features ================== -The saml21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -136,6 +93,8 @@ The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAML21 chip and is supported by OpenOCD. diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst index e04b4d7a711f..94db3100c6ee 100644 --- a/boards/atmel/sam0/samr21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -23,33 +23,7 @@ Hardware Supported Features ================== -The samr21_xpro board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+--------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+--------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+--------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+--------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+--------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+--------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+--------------------------------------+ -| I2C | on-chip | I2C Peripheral Interface ports | -+-----------+------------+--------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -160,6 +134,8 @@ echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMR21 chip and is supported by OpenOCD. diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml index 77e032878b2e..0513a8f60231 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml @@ -23,6 +23,7 @@ supported: - spi - uart - usb_device + - usbd - xpro_gpio - xpro_i2c - xpro_serial diff --git a/boards/atmel/sam0/samr34_xpro/doc/index.rst b/boards/atmel/sam0/samr34_xpro/doc/index.rst index 4a38544be350..001233e11808 100644 --- a/boards/atmel/sam0/samr34_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr34_xpro/doc/index.rst @@ -28,63 +28,7 @@ Hardware Supported Features ================== -The samr34_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -The following hardware features are supported by Zephyr, but not yet fully -supported by the SOC: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - LoRa Radio - - on-chip - - Internal SX1276 LoRa Radio - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig`. +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -150,6 +94,8 @@ The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This provides a debug interface to the SAMR34 chip and is supported by OpenOCD. diff --git a/boards/bbc/microbit/board.cmake b/boards/bbc/microbit/board.cmake index b6bae59502cb..aad2286503c5 100644 --- a/boards/bbc/microbit/board.cmake +++ b/boards/bbc/microbit/board.cmake @@ -9,6 +9,7 @@ set(OPENOCD_NRF5_SUBFAMILY "nrf51") set(OPENOCD_NRF5_INTERFACE "cmsis-dap") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/bbc/microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst index 1d829d89a89a..9224cd4f24da 100644 --- a/boards/bbc/microbit/doc/index.rst +++ b/boards/bbc/microbit/doc/index.rst @@ -13,13 +13,6 @@ magnetometer sensors, Bluetooth and USB connectivity, a display consisting of external battery pack. The device inputs and outputs are through five ring connectors that are part of the 23-pin edge connector. -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`RTC (nRF RTC System Clock)` -* UART -* GPIO -* FLASH -* RADIO (Bluetooth Low Energy) - More information about the board can be found at the `microbit website`_. Hardware @@ -39,29 +32,13 @@ The micro:bit has the following physical features: Supported Features ================== -The bbc_microbit board configuration supports the following nRF51 -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/bbc/microbit_v2/board.cmake b/boards/bbc/microbit_v2/board.cmake index c94ffa163069..0dd45ff28f76 100644 --- a/boards/bbc/microbit_v2/board.cmake +++ b/boards/bbc/microbit_v2/board.cmake @@ -9,6 +9,7 @@ set(OPENOCD_NRF5_SUBFAMILY "nrf52") # in which case the following line should be removed to default back to "jlink" OpenOCD interface set(OPENOCD_NRF5_INTERFACE "cmsis-dap") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/bbc/microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst index 62c3cee2252c..24fbaf5d2a36 100644 --- a/boards/bbc/microbit_v2/doc/index.rst +++ b/boards/bbc/microbit_v2/doc/index.rst @@ -33,29 +33,13 @@ The micro:bit-v2 has the following physical features: Supported Features ================== -The bbc_microbit_v2 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/bcdevices/plt_demo_v2/board.cmake b/boards/bcdevices/plt_demo_v2/board.cmake index 293556379734..ebf0cf5bffa9 100644 --- a/boards/bcdevices/plt_demo_v2/board.cmake +++ b/boards/bcdevices/plt_demo_v2/board.cmake @@ -4,6 +4,7 @@ set(OPENOCD_NRF5_SUBFAMILY "nrf52") board_runner_args(nrfjprog "--nrf-family=NRF52") board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52832" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/bcdevices/plt_demo_v2/doc/index.rst b/boards/bcdevices/plt_demo_v2/doc/index.rst index 646e5c920250..cdab9ada052e 100644 --- a/boards/bcdevices/plt_demo_v2/doc/index.rst +++ b/boards/bcdevices/plt_demo_v2/doc/index.rst @@ -41,40 +41,7 @@ Hardware Supported Features ================== -The Blue Clover PLT Demo V2 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -105,6 +72,8 @@ NFC Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``blueclover_plt_demo_v2/nrf52832`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts index 804abfd95660..c8676ebce825 100644 --- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts @@ -19,6 +19,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -43,6 +46,12 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1 0>, <&mbox1 1>; + mbox-names = "tx", "rx"; + }; }; &i2c6 { diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index 3191eccb6252..ec24ee9f6bf4 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -23,6 +23,7 @@ mcuboot-button0 = &button0; sensor0 = &light; sensor1 = &humidity; + watchdog0 = &wdt0; }; chosen { @@ -285,3 +286,7 @@ zephyr,resolution = <12>; }; }; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/beagle/beagleconnect_freedom/doc/index.rst b/boards/beagle/beagleconnect_freedom/doc/index.rst index 8bf3bf4e6e60..3fac0a1f08de 100644 --- a/boards/beagle/beagleconnect_freedom/doc/index.rst +++ b/boards/beagle/beagleconnect_freedom/doc/index.rst @@ -24,41 +24,7 @@ GPIO expander. Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| HWINFO | on-chip | hwinfo | -+-----------+------------+----------------------+ -| I2C | off-chip | OPT3001 | -+-----------+------------+----------------------+ -| I2C | off-chip | HDC2010 | -+-----------+------------+----------------------+ -| I2C | off-chip | BCF_BRIDGE_MCU | -+-----------+------------+----------------------+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | ieee802154 | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts index 43dd64f9c1cd..b72290420e4d 100644 --- a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts +++ b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts @@ -16,6 +16,7 @@ aliases { led0 = &led0; led1 = &led1; + watchdog0 = &wdt0; }; chosen { @@ -93,3 +94,7 @@ &ieee802154g { status = "okay"; }; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst index 24665eafce18..7f38c4589c73 100644 --- a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst +++ b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst @@ -55,23 +55,7 @@ BeaglePlay ARM Cortex-A53 CPUs typically run Linux, while the CC1352P7 Cortex-M4 Supported Features ================== -The ``beagleplay/cc1352p7`` board target supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| RADIO | on-chip | ieee802154 | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -137,6 +121,8 @@ CC1352 reset is connected to AM62 GPIO0_14. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts index 5bf213b64445..ac4d2b46e2ed 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts @@ -18,6 +18,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -42,6 +45,12 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox3 0>, <&mbox3 1>; + mbox-names = "tx", "rx"; + }; }; &uart1 { diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts index e2957226a66e..2c6f9f8c5f4f 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts @@ -18,6 +18,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -42,6 +45,12 @@ reg = <0xa1200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1 0>, <&mbox1 1>; + mbox-names = "tx", "rx"; + }; }; &uart1 { diff --git a/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 new file mode 100644 index 000000000000..6a74baa34601 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 @@ -0,0 +1,9 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_POCKETBEAGLE_2 + select SOC_AM6232_A53 if BOARD_POCKETBEAGLE_2_AM6232_A53 + select SOC_AM6232_M4 if BOARD_POCKETBEAGLE_2_AM6232_M4 diff --git a/boards/beagle/pocketbeagle_2/board.cmake b/boards/beagle/pocketbeagle_2/board.cmake new file mode 100644 index 000000000000..d1f7b9aff412 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/board.cmake @@ -0,0 +1,10 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_AM6232_M4) + board_runner_args(openocd "--no-init" "--no-halt" "--no-targets" "--gdb-client-port=3339") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/beagle/pocketbeagle_2/board.yml b/boards/beagle/pocketbeagle_2/board.yml new file mode 100644 index 000000000000..03f54cde3bb1 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/board.yml @@ -0,0 +1,12 @@ +board: + name: pocketbeagle_2 + full_name: PocketBeagle 2 + vendor: beagle + socs: + - name: am6232 + revision: + format: custom + exact: true + default: "A0" + revisions: + - name: "A0" diff --git a/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp b/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp new file mode 100644 index 000000000000..34ecf2d1e000 Binary files /dev/null and b/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp differ diff --git a/boards/beagle/pocketbeagle_2/doc/index.rst b/boards/beagle/pocketbeagle_2/doc/index.rst new file mode 100644 index 000000000000..51852ffb8c4f --- /dev/null +++ b/boards/beagle/pocketbeagle_2/doc/index.rst @@ -0,0 +1,177 @@ +.. zephyr:board:: pocketbeagle_2 + +Overview +******** + +PocketBeagle 2 is a computational platform powered by TI AM62x SoC (there are two +revisions, AM6232 and AM6254). + +The board configuration provides support for the ARM Cortex-M4F MCU core. + +See the `PocketBeagle 2 Product Page`_ for details. + +Hardware +******** +PocketBeagle 2 features the TI AM62x SoC based around an Arm Cortex-A53 multicore +cluster with an Arm Cortex-M4F microcontroller, Imagination Technologies AXE-1-16 +graphics processor (from revision A1) and TI programmable real-time unit subsystem +microcontroller cluster coprocessors. + +Zephyr is ported to run on the both A53 cores and/or M4F core. + +The following listed hardware specifications are used: + +- Dual ARM Cortex-A53 cores +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 512MB of DDR4 + +Currently supported PocketBeagle 2 revisions: + +- A0: Comes wth SOC AM6232 + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board has 512MB of DDR RAM available. This board configuration +allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). + +Serial Port +----------- + +A53 Cores +^^^^^^^^^ + +This board configuration uses single serial communication channel with the MAIN domain UART +(MAIN_UART6, i.e. debug port). + +M4F Core +^^^^^^^^ + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0, i.e. P2.05 as RX and P2.07 as TX). + +SD Card +******* + +A53 Cores +========= + +Download BeagleBoard.org's official `BeagleBoard Imaging Utility`_ to create bootable +SD-card with the Zephyr image. Optionally, the Zephyr SD Card images can be downloaded from +`bb-zephyr-images`_. + +M4F Core +======== + +Download BeagleBoard.org's official `BeagleBoard Imaging Utility`_ to create bootable +SD-card with the Linux distro image. This will boot Linux on the A53 application +cores. These cores will then load the Zephyr binary on the M4 core using remoteproc. + +Flashing +******** + +A53 Core +======== + +The testing requires the binary to be copied to the BOOT partition in SD card. + +To test the A53 core, we build the :zephyr:code-sample:`hello_world` sample with the following command. + +.. zephyr-app-commands:: + :board: pocketbeagle_2/am6232/a53 + :zephyr-app: samples/hello_world + :goals: build + +We now copy this binary onto the SD card in the :file:`/boot/` directory and name it as +:file:`zephyr.bin`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the bin to the /boot/ + sudo cp --remove-destination zephyr.bin sdcard/boot/zephyr.bin + +The SD card can now be used for booting. + +The binary will run and print Hello world to the debug port. + +M4F Core +======== + +The board supports remoteproc using the OpenAMP resource table. + +The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. + +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. + +.. zephyr-app-commands:: + :board: pocketbeagle_2/am6232/m4 + :zephyr-app: samples/hello_world + :goals: build + +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. + +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am62-mcu-m4f0_0-fw`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the elf to the /lib/firmware directory + sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw + +The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. + +The binary will run and print Hello world to the MCU_UART0 port. + +Debugging +********* + +M4F Core +======== + +The board supports debugging M4 core from the A53 cores running Linux. Since the target needs +superuser privilege, openocd needs to be launched separately for now: + +.. code-block:: console + + sudo openocd -f board/ti_am625_swd_native.cfg + + +Start debugging + +.. zephyr-app-commands:: + :goals: debug + +References +********** + +* `PocketBeagle 2 Product Page`_ +* `Documentation `_ + +.. _PocketBeagle 2 Product Page: + https://www.beagleboard.org/boards/pocketbeagle-2 + +.. _BeagleBoard Imaging Utility: + https://github.com/beagleboard/bb-imager-rs/releases + +.. _bb-zephyr-images: + https://github.com/beagleboard/bb-zephyr-images/releases diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi new file mode 100644 index 000000000000..862a798952c4 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + main_uart6_rx_default: main_uart6_rx_default { + pinmux = ; + }; + + main_uart6_tx_default: main_uart6_tx_default { + pinmux = ; + }; + + main_i2c2_sda_default: main_i2c2_sda_default { + /* (K24) GPMC0_CSn3.I2C2_SDA */ + pinmux = ; + }; + + main_i2c2_scl_default: main_i2c2_scl_default { + /* (K22) GPMC0_CSn2.I2C2_SCL */ + pinmux = ; + }; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts new file mode 100644 index 000000000000..b035519f59e5 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "pocketbeagle_2_am6232_a53-pinctrl.dtsi" + +/ { + model = "BeagleBoard.org PocketBeagle 2"; + compatible = "beagle,pocketbeagle_2_a53"; + + chosen { + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + zephyr,sram = &ddr0; + }; + + cpus { + cpu@0 { + status = "okay"; + }; + + cpu@1 { + status = "okay"; + }; + }; + + ddr0: memory@80000000 { + reg = <0x80000000 DT_SIZE_M(512)>; + }; +}; + +&uart6 { + pinctrl-0 = <&main_uart6_rx_default &main_uart6_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-0 = <&main_i2c2_sda_default &main_i2c2_scl_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml new file mode 100644 index 000000000000..30d04fc35512 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml @@ -0,0 +1,12 @@ +identifier: pocketbeagle_2/am6232/a53 +name: BeagleBoard.org PocketBeagle 2 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 524288 +vendor: beagle +supported: + - uart + - i2c diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig new file mode 100644 index 000000000000..d7ee894fcf4c --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig @@ -0,0 +1,32 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Platform Configuration + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Multicore Support +CONFIG_SMP=y diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi new file mode 100644 index 000000000000..7f54984345a2 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + mcu_uart0_rx_default: mcu_uart0_rx_default { + pinmux = ; + }; + + mcu_uart0_tx_default: mcu_uart0_tx_default { + pinmux = ; + }; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts new file mode 100644 index 000000000000..6b1c256976b5 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "pocketbeagle_2_am6232_m4-pinctrl.dtsi" + +/ { + model = "BeagleBoard.org PocketBeagle 2"; + compatible = "beagle,pocketbeagle_2_m4"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; + zephyr,sram1 = &ddr1; + }; + + cpus { + cpu@0 { + status = "okay"; + clock-frequency = <400000000>; + }; + }; + + ddr0: memory@9cb00000 { + compatible = "mmio-sram"; + reg = <0x9cb00000 DT_SIZE_M(1)>; + }; + + rsc_table: memory@9cc00000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x9cc00000 DT_SIZE_K(4)>; + zephyr,memory-region = "RSC_TABLE"; + }; + + ddr1: memory@9cc01000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x9cc01000 (DT_SIZE_M(15) - DT_SIZE_K(4))>; + zephyr,memory-region = "DDR"; + }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox0 0>, <&mbox0 1>; + mbox-names = "tx", "rx"; + }; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&mcu_uart0_rx_default &mcu_uart0_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml new file mode 100644 index 000000000000..fc258c2e383d --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml @@ -0,0 +1,10 @@ +identifier: pocketbeagle_2/am6232/m4 +name: BeagleBoard.org PocketBeagle 2 +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: beagle +supported: + - uart diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig new file mode 100644 index 000000000000..02a9f623a271 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig @@ -0,0 +1,18 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/beagle/pocketbeagle_2/revision.cmake b/boards/beagle/pocketbeagle_2/revision.cmake new file mode 100644 index 000000000000..f7698f24bf31 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/revision.cmake @@ -0,0 +1,10 @@ +set(BOARD_REVISIONS "A0") + +# If BOARD_REVISION not set, use the default revision +if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION ${LIST_BOARD_REVISION_DEFAULT}) +endif() + +if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for PocketBeagle 2. Accepted revisions: ${BOARD_REVISIONS}") +endif() diff --git a/boards/beagle/pocketbeagle_2/support/openocd.cfg b/boards/beagle/pocketbeagle_2/support/openocd.cfg new file mode 100644 index 000000000000..f0cff3f9e2db --- /dev/null +++ b/boards/beagle/pocketbeagle_2/support/openocd.cfg @@ -0,0 +1,7 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +source [find board/ti_am625_swd_native.cfg] diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk b/boards/bflb/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk new file mode 100644 index 000000000000..806d0c5ca003 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk @@ -0,0 +1,6 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL604E_IOT_DVK + select SOC_BL604E20Q2I diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi new file mode 100644 index 000000000000..f5cce349d3ca --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021-2025 ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + pinmux = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts new file mode 100644 index 000000000000..87e986cbfe4e --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2022-2025 ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "bl604e_iot_dvk-pinctrl.dtsi" + +/ { + model = "BL604E IOT DVK development board"; + compatible = "bflb,bl604"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0xc00000>; + + flash0: flash@0 { + compatible = "issi,is25lp128", "jedec,spi-nor"; + status = "disabled"; + size = ; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = ; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml new file mode 100644 index 000000000000..51b1065ff228 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl604e_iot_dvk +name: BL604E IOT DVK development board +type: mcu +arch: riscv +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +supported: + - pinctrl + - uart +vendor: bflb diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig new file mode 100644 index 000000000000..a512dfb34f7c --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake new file mode 100644 index 000000000000..29a318dbdb8a --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake @@ -0,0 +1,26 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") + +board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") +board_runner_args(openocd --gdb-init "set architecture riscv:rv32") +board_runner_args(openocd --gdb-init "set remotetimeout 250") +board_runner_args(openocd --gdb-init "set print asm-demangle on") +board_runner_args(openocd --gdb-init "set backtrace limit 32") +board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") +board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") +board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") +board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") +board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(bflb_mcu_tool --chipname bl602) +board_runner_args(bflb_mcu_tool --dev-id /dev/ttyACM0) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/board.yml b/boards/bflb/bl60x/bl604e_iot_dvk/board.yml new file mode 100644 index 000000000000..843d38b0e8a2 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/board.yml @@ -0,0 +1,6 @@ +board: + name: bl604e_iot_dvk + full_name: BL604E IOT DVK development board + vendor: bflb + socs: + - name: bl604e20q2i diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp b/boards/bflb/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp new file mode 100644 index 000000000000..a4e60232febd Binary files /dev/null and b/boards/bflb/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp differ diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst b/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst new file mode 100644 index 000000000000..0c440d596915 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst @@ -0,0 +1,103 @@ +.. zephyr:board:: bl604e_iot_dvk + +Overview +******** + +BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used +for low power consumption and high performance application development. The +wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 +baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU +with low power consumption, cache and memory. The power management unit +controls the low power consumption mode. In addition, it also supports +various security features. The external interfaces include SDIO, SPI, UART, +I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. + +The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU, +it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, +2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 +with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed +image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key +Accelerator). + +Hardware +******** + +For more information about the Bouffalo Lab BL-60x MCU: + +- `Bouffalo Lab BL60x MCU Website`_ +- `Bouffalo Lab BL60x MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The BL604E Development Board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``bl604e_iot_dvk`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl604e_iot_dvk + :goals: build flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release RST button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0 *** + Hello World! bl604e_iot_dvk/bl604e20q2i + +Congratulations, you have ``bl604e_iot_dvk`` configured and running Zephyr. + + +.. _Bouffalo Lab BL60x MCU Website: + https://en.bouffalolab.com/product/?type=detail&id=6 + +.. _Bouffalo Lab BL60x MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg b/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg new file mode 100644 index 000000000000..fcabb2c4e7c0 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME riscv +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +if { [info exists WORKAREAADDR] } { + set _WORKAREAADDR $WORKAREAADDR +} else { + set _WORKAREAADDR 0x22020000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x20000c05 +} + +transport select jtag +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME + +$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + + adapter speed 100 + + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x23000000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" + + adapter speed 3000 +} + +$_TARGETNAME.0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME.0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +gdb_memory_map enable +gdb_flash_program enable + +# 'progbuf', 'sysbus' or 'abstract' +riscv set_mem_access sysbus +riscv set_command_timeout_sec 1 + +init +reset init diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/support/openocd.cfg b/boards/bflb/bl60x/bl604e_iot_dvk/support/openocd.cfg new file mode 100644 index 000000000000..ffd60cfb196c --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/support/openocd.cfg @@ -0,0 +1,19 @@ +# OpenOCD Script for PineCone connected via Sipeed JTAG Debugger (FTDI FT2232D) +# Ref: bl_iot_sdk/tools/debug/if_bflb_link.cfg +# source [find interface/if_bflb_link.cfg] + +# Uncomment to enable debug messages +# debug_level 4 + +# BouffaloLab USB-JTAG/TTL adapter +# Or Sipeed JTAG Debugger based on FTDI FT2232D + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +# Sipeed JTAG Debugger uses FTDI Channel 0, not 1 +ftdi channel 0 +# ftdi_channel 1 + +ftdi layout_init 0x00f8 0x00fb +adapter speed 4000 diff --git a/boards/bflb/index.rst b/boards/bflb/index.rst new file mode 100644 index 000000000000..f0380b6b45c7 --- /dev/null +++ b/boards/bflb/index.rst @@ -0,0 +1,10 @@ +.. _boards-bouffalolab: + +Bouffalo Lab Intelligent Technology (Nanjing) Co., Ltd. +####################################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/blues/cygnet/Kconfig.cygnet b/boards/blues/cygnet/Kconfig.cygnet new file mode 100644 index 000000000000..f907d27024ba --- /dev/null +++ b/boards/blues/cygnet/Kconfig.cygnet @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Blues +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CYGNET + select SOC_STM32L433XX diff --git a/boards/blues/cygnet/Kconfig.defconfig b/boards/blues/cygnet/Kconfig.defconfig new file mode 100644 index 000000000000..898cdfcf29a7 --- /dev/null +++ b/boards/blues/cygnet/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L433CC Cygnet board configuration + +# Copyright (c) 2025 Blues +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CYGNET + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_CYGNET diff --git a/boards/blues/cygnet/board.cmake b/boards/blues/cygnet/board.cmake new file mode 100644 index 000000000000..3f2cb7628591 --- /dev/null +++ b/boards/blues/cygnet/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32L433CC" "--speed=4000") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/blues/cygnet/board.yml b/boards/blues/cygnet/board.yml new file mode 100644 index 000000000000..4341ee22c8e2 --- /dev/null +++ b/boards/blues/cygnet/board.yml @@ -0,0 +1,6 @@ +board: + name: cygnet + full_name: Cygnet + vendor: blues + socs: + - name: stm32l433xx diff --git a/boards/blues/cygnet/cygnet.dts b/boards/blues/cygnet/cygnet.dts new file mode 100644 index 000000000000..00fd5282bd2e --- /dev/null +++ b/boards/blues/cygnet/cygnet.dts @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2025 Blues + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "feather_connector.dtsi" +#include + +/ { + model = "Blues Cygnet"; + compatible = "blues,cygnet"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + + user_led: led_0 { + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + label = "User Button"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <20>; + div-p = <7>; + div-q = <2>; + div-r = <4>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + +&lpuart1 { + pinctrl-0 = <&lpuart1_tx_pb11 &lpuart1_rx_pb10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&timers2 { + status = "okay"; + + pwm2: pwm { + status = "okay"; + pinctrl-0 = <&tim2_ch1_pa0>; + pinctrl-names = "default"; + }; +}; + +&can1 { + pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Reserve the final 16 KiB for file system partition + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/boards/blues/cygnet/cygnet.yaml b/boards/blues/cygnet/cygnet.yaml new file mode 100644 index 000000000000..88af7f3d91d3 --- /dev/null +++ b/boards/blues/cygnet/cygnet.yaml @@ -0,0 +1,22 @@ +identifier: cygnet +name: Blues Cygnet +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 256 +supported: + - nvs + - can + - spi + - i2c + - pwm + - gpio + - counter + - feather_serial + - feather_i2c + - feather_spi +vendor: blues diff --git a/boards/blues/cygnet/cygnet_defconfig b/boards/blues/cygnet/cygnet_defconfig new file mode 100644 index 000000000000..674354645c17 --- /dev/null +++ b/boards/blues/cygnet/cygnet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/blues/cygnet/doc/img/cygnet-pinout.webp b/boards/blues/cygnet/doc/img/cygnet-pinout.webp new file mode 100644 index 000000000000..9499bcaa82eb Binary files /dev/null and b/boards/blues/cygnet/doc/img/cygnet-pinout.webp differ diff --git a/boards/blues/cygnet/doc/img/cygnet.webp b/boards/blues/cygnet/doc/img/cygnet.webp new file mode 100644 index 000000000000..a1355669cb22 Binary files /dev/null and b/boards/blues/cygnet/doc/img/cygnet.webp differ diff --git a/boards/blues/cygnet/doc/index.rst b/boards/blues/cygnet/doc/index.rst new file mode 100644 index 000000000000..8283eb15db69 --- /dev/null +++ b/boards/blues/cygnet/doc/index.rst @@ -0,0 +1,204 @@ +.. zephyr:board:: cygnet + +Overview +******** + +The Blues Cygnet board features an ARM Cortex-M4 based STM32L433CC MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Cygnet board: + +- STM32L4 microcontroller in LQFP48 package +- Adafruit Feather connector +- User LED +- User push-button +- USB Type-C connector + +More information about the board can be found at the `Blues Cygnet website`_. + +Hardware +******** + +The STM32L433CC SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- 11x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 21 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 256 KB single bank Flash, proprietary code readout protection + - 64 KB of SRAM including 16 KB with hardware parity check + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC output channels, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 17x communication interfaces + + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + +More information about STM32L433CC can be found here: + +- `STM32L433CC on www.st.com`_ +- `STM32L432 reference manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: CAN feature requires a CAN transceiver. + +Connections and IOs +=================== + +The Cygnet board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins +-------------- +.. image:: img/cygnet-pinout.webp + :align: center + :alt: Cygnet Pinout + +For more details please refer to `Blues Cygnet User Manual`_. + +Default Zephyr Peripheral Mapping +--------------------------------- + +- LPUART_1_TX : PB11 +- LPUART_1_RX : PB10 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- SPI_1: SCK/MISO/MOSI : PA5/PA6/PB5 + +System Clock +------------ + +The Cygnet board System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +The Cygnet board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned +to LPUART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Cygnet board requires an ST-LINK embedded debug tool in order to be programmed and debugged. + +Applications for the ``cygnet`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to Cygnet +--------------------------------- + +Connect the Cygnet to the ST-LINK debugger, then run a serial host program to connect with your Cygnet board. + +.. code-block:: console + + $ picocom /dev/ttyACM0 -b 115200 + +Now build and flash an application. Here is an example for +:zephyr:code-sample:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cygnet + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! cygnet + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cygnet + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Blues Cygnet website: + https://www.blues.dev/ + +.. _Blues Cygnet User Manual: + https://dev.blues.io/feather-mcus/cygnet/cygnet-introduction/ + +.. _STM32L433CC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l433cc.html + +.. _STM32L432 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/blues/cygnet/feather_connector.dtsi b/boards/blues/cygnet/feather_connector.dtsi new file mode 100644 index 000000000000..da08fb458847 --- /dev/null +++ b/boards/blues/cygnet/feather_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Blues Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 2 0>, /* A2 */ + <3 0 &gpioa 3 0>, /* A3 */ + <4 0 &gpiob 1 0>, /* A4 */ + <5 0 &gpioa 7 0>, /* A5 */ + <6 0 &gpioa 5 0>, /* SCK */ + <7 0 &gpiob 5 0>, /* MOSI */ + <8 0 &gpioa 6 0>, /* MISO */ + <9 0 &gpioa 10 0>, /* RX */ + <10 0 &gpioa 9 0>, /* TX */ + <11 0 &gpiob 1 0>, /* D4 */ + <12 0 &gpiob 7 0>, /* SDA */ + <13 0 &gpiob 6 0>, /* SCL */ + <14 0 &gpiob 8 0>, /* D5 */ + <15 0 &gpiob 9 0>, /* D6 */ + <16 0 &gpiob 14 0>, /* D9 */ + <17 0 &gpiob 13 0>, /* D10 */ + <18 0 &gpiob 0 0>, /* D11 */ + <19 0 &gpiob 15 0>, /* D12 */ + <20 0 &gpiob 4 0>; /* D13 */ + }; +}; + +feather_serial: &usart1 {}; +feather_i2c: &i2c1 {}; +feather_spi: &spi1 {}; diff --git a/boards/blues/cygnet/support/openocd.cfg b/boards/blues/cygnet/support/openocd.cfg new file mode 100644 index 000000000000..cd566c1fa1c9 --- /dev/null +++ b/boards/blues/cygnet/support/openocd.cfg @@ -0,0 +1,7 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l4x.cfg] + +reset_config srst_only diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst index 51212bd4c642..0c2c796abd4c 100644 --- a/boards/blues/swan_r5/doc/index.rst +++ b/boards/blues/swan_r5/doc/index.rst @@ -85,37 +85,7 @@ More information about Swan can be found here: Supported Features ================== -The Zephyr Swan board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/blues/swan_r5/swan_r5_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -189,6 +159,8 @@ assigned to LPUART. Default settings are 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Connect Swan to your host computer using the USB port. Then build and flash an application. Here is an example for the :zephyr:code-sample:`hello_world` application. diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts index 2054d6bd2e2e..b3be00fc171e 100644 --- a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts @@ -93,15 +93,15 @@ int-gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; - temperature_sensor: tmp116@4a { + temperature_sensor: tmp11x@4a { status = "okay"; - compatible = "ti,tmp116"; + compatible = "ti,tmp11x"; reg = <0x4a>; #address-cells = <1>; #size-cells = <0>; - eeprom: ti_tmp116_eeprom@0 { - compatible = "ti,tmp116-eeprom"; + eeprom: ti_tmp11x_eeprom@0 { + compatible = "ti,tmp11x-eeprom"; reg = <0x0>; read-only; }; diff --git a/boards/bytesatwork/bytesensi_l/doc/index.rst b/boards/bytesatwork/bytesensi_l/doc/index.rst index d1b220a778b9..35e402497edc 100644 --- a/boards/bytesatwork/bytesensi_l/doc/index.rst +++ b/boards/bytesatwork/bytesensi_l/doc/index.rst @@ -12,33 +12,7 @@ Hardware Supported Features ================== -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPS | u-blox | gnss | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RADIO | Semtech | LoRa | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -121,6 +95,8 @@ External GPS Antenna @ J3 Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== The byteSENSI-L board can be flashed with the SEGGER JLink programmer. diff --git a/boards/circuitdojo/feather/board.cmake b/boards/circuitdojo/feather/board.cmake index 9c0c33243af6..91aec43ebb51 100644 --- a/boards/circuitdojo/feather/board.cmake +++ b/boards/circuitdojo/feather/board.cmake @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi index 186f6ef4662c..d99760f762c8 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi @@ -183,4 +183,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/common/bflb_mcu_tool.board.cmake b/boards/common/bflb_mcu_tool.board.cmake new file mode 100644 index 000000000000..73862b0f5e19 --- /dev/null +++ b/boards/common/bflb_mcu_tool.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(bflb_mcu_tool) +board_finalize_runner_args(bflb_mcu_tool) diff --git a/boards/common/esp32.board.cmake b/boards/common/esp32.board.cmake index cfe7b7683fc1..4669c2e620be 100644 --- a/boards/common/esp32.board.cmake +++ b/boards/common/esp32.board.cmake @@ -13,4 +13,4 @@ board_runner_args(openocd --gdb-init "thb main") set(ESP_IDF_PATH ${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}) assert(ESP_IDF_PATH "ESP_IDF_PATH is not set") -board_finalize_runner_args(esp32 "--esp-idf-path=${ESP_IDF_PATH}") +board_runner_args(esp32 "--esp-idf-path=${ESP_IDF_PATH}") diff --git a/boards/common/nios2.board.cmake b/boards/common/nios2.board.cmake deleted file mode 100644 index 4a59927171bc..000000000000 --- a/boards/common/nios2.board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(nios2) -board_set_debugger_ifnset(nios2) - -board_finalize_runner_args(nios2 - # TODO: merge this script into nios2.py - "--quartus-flash=${ZEPHYR_BASE}/scripts/support/quartus-flash.py" - ) diff --git a/boards/common/openocd-adi-max32.boards.cmake b/boards/common/openocd-adi-max32.boards.cmake index 93409dd6901f..c815a0db64f3 100644 --- a/boards/common/openocd-adi-max32.boards.cmake +++ b/boards/common/openocd-adi-max32.boards.cmake @@ -3,35 +3,26 @@ # # SPDX-License-Identifier: Apache-2.0 -# Default cmsis-dap, it will be overwritten below if requires -set(MAX32_INTERFACE_CFG "cmsis-dap.cfg") +if(CONFIG_ARCH STREQUAL "riscv") + set(MAX32_TARGET_CFG "${CONFIG_SOC}_riscv.cfg") + set(MAX32_INTERFACE_CFG "olimex-arm-usb-ocd-h.cfg") +else() + set(MAX32_TARGET_CFG "${CONFIG_SOC}.cfg") + set(MAX32_INTERFACE_CFG "cmsis-dap.cfg") +endif() -if(CONFIG_SOC_MAX32655_M4) - set(MAX32_TARGET_CFG "max32655.cfg") -elseif(CONFIG_SOC_MAX32662) - set(MAX32_TARGET_CFG "max32662.cfg") -elseif(CONFIG_SOC_MAX32666) +# MAX32666 share the same target configuration file with MAX32665 +if(CONFIG_SOC_MAX32666) set(MAX32_TARGET_CFG "max32665.cfg") -elseif(CONFIG_SOC_MAX32670) - set(MAX32_TARGET_CFG "max32670.cfg") -elseif(CONFIG_SOC_MAX32672) - set(MAX32_TARGET_CFG "max32672.cfg") -elseif(CONFIG_SOC_MAX32675) - set(MAX32_TARGET_CFG "max32675.cfg") -elseif(CONFIG_SOC_MAX32680_M4) - set(MAX32_TARGET_CFG "max32680.cfg") -elseif(CONFIG_SOC_MAX32690_M4) - set(MAX32_TARGET_CFG "max32690.cfg") -elseif(CONFIG_SOC_MAX78000_M4) - set(MAX32_TARGET_CFG "max78000.cfg") -elseif(CONFIG_SOC_MAX78002_M4) - set(MAX32_TARGET_CFG "max78002.cfg") +elseif(CONFIG_SOC_MAX32657) + set(MAX32_INTERFACE_CFG "jlink.cfg") endif() board_runner_args(openocd --cmd-pre-init "source [find interface/${MAX32_INTERFACE_CFG}]") board_runner_args(openocd --cmd-pre-init "source [find target/${MAX32_TARGET_CFG}]") +board_runner_args(openocd "--target-handle=_CHIPNAME.cpu") -if(CONFIG_SOC_FAMILY_MAX32_M4) +if(CONFIG_SOC_FAMILY_MAX32_M4 OR CONFIG_SOC_FAMILY_MAX32_M33) board_runner_args(openocd --cmd-pre-init "allow_low_pwr_dbg") board_runner_args(openocd "--cmd-erase=max32xxx mass_erase 0") endif() diff --git a/boards/common/openocd-stm32.board.cmake b/boards/common/openocd-stm32.board.cmake index 855411fa34b1..cecaba235299 100644 --- a/boards/common/openocd-stm32.board.cmake +++ b/boards/common/openocd-stm32.board.cmake @@ -18,3 +18,5 @@ elseif(CONFIG_SOC_SERIES_STM32F2X OR CONFIG_SOC_SERIES_STM32F7X) board_runner_args(openocd "--cmd-erase=stm32f2x mass_erase 0") endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/common/openocd.board.cmake b/boards/common/openocd.board.cmake index b1d09fe0a2dd..14d32d4be254 100644 --- a/boards/common/openocd.board.cmake +++ b/boards/common/openocd.board.cmake @@ -20,6 +20,3 @@ board_finalize_runner_args(openocd --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" ) - -# Manufacturer common options -include(${CMAKE_CURRENT_LIST_DIR}/openocd-stm32.board.cmake) diff --git a/boards/common/rfp.board.cmake b/boards/common/rfp.board.cmake new file mode 100644 index 000000000000..afce0c8019cc --- /dev/null +++ b/boards/common/rfp.board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(rfp) + +board_finalize_runner_args(rfp) diff --git a/boards/contextualelectronics/abc/board.cmake b/boards/contextualelectronics/abc/board.cmake index 261663eef4e2..1482c471b4cd 100644 --- a/boards/contextualelectronics/abc/board.cmake +++ b/boards/contextualelectronics/abc/board.cmake @@ -3,6 +3,7 @@ set(OPENOCD_NRF5_SUBFAMILY "nrf52") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/contextualelectronics/abc/doc/index.rst b/boards/contextualelectronics/abc/doc/index.rst index d7f12bc4738c..02ddb9689e5f 100644 --- a/boards/contextualelectronics/abc/doc/index.rst +++ b/boards/contextualelectronics/abc/doc/index.rst @@ -35,38 +35,8 @@ is 32.768 kHz. The frequency of the main clock is 32 MHz. Supported Features ================== -The contextualelectronics_abc board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| Modem | on-board | quectel_bg9x | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `ABC Board website`_ for more details on this board, and `Nordic Semiconductor Infocenter`_ for a complete list of SoC features. @@ -74,6 +44,8 @@ features. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``contextualelectronics_abc`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/croxel/croxel_cx1825/board.cmake b/boards/croxel/croxel_cx1825/board.cmake index f95878945bed..506a13398403 100644 --- a/boards/croxel/croxel_cx1825/board.cmake +++ b/boards/croxel/croxel_cx1825/board.cmake @@ -2,6 +2,7 @@ board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/croxel/croxel_cx1825/doc/index.rst b/boards/croxel/croxel_cx1825/doc/index.rst index ab88c4dd4321..cee944d5f97a 100644 --- a/boards/croxel/croxel_cx1825/doc/index.rst +++ b/boards/croxel/croxel_cx1825/doc/index.rst @@ -46,12 +46,7 @@ Hardware Supported Features ================== -- Discrete LEDs (red and green) -- Buttons (User and Reset) -- Sensors (Accelerometer, Light, Temperature and Humidity, Pressure and Hall-Effect sensors) -- Beeper -- Radio (Bluetooth, IEEE 802.15.4) -- SOC peripherals (ADC, Clock, Flash, GPIO, I2C, MPU, NVIC, PWM, Radio, RTC, SPI, USB, WDT) +.. zephyr:board-supported-hw:: Future Feature Support ====================== @@ -81,6 +76,8 @@ Digital Inputs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``croxel_cx1825/nrf52840`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/ct/ctcc/board.cmake b/boards/ct/ctcc/board.cmake index 11d0511404b1..65f36c72e6c8 100644 --- a/boards/ct/ctcc/board.cmake +++ b/boards/ct/ctcc/board.cmake @@ -3,6 +3,7 @@ if(CONFIG_BOARD_CTCC_NRF52840) board_runner_args(nrfjprog "--softreset") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) elseif(CONFIG_BOARD_CTCC_NRF9161 OR CONFIG_BOARD_CTCC_NRF9161_NS) @@ -14,6 +15,7 @@ elseif(CONFIG_BOARD_CTCC_NRF9161 OR CONFIG_BOARD_CTCC_NRF9161_NS) endif() board_runner_args(nrfjprog "--softreset") board_runner_args(pyocd "--target=nrf9161" "--frequency=4000000") + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) endif() diff --git a/boards/ct/ctcc/board.yml b/boards/ct/ctcc/board.yml index 826b1846af5d..e36afe64d4cc 100644 --- a/boards/ct/ctcc/board.yml +++ b/boards/ct/ctcc/board.yml @@ -1,6 +1,7 @@ board: name: ctcc full_name: CTHINGS.CO Connectivity Card + vendor: ct socs: - name: nrf52840 - name: nrf9161 diff --git a/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi index c48b2987b85d..10eece2fd56e 100644 --- a/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi +++ b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi @@ -25,28 +25,6 @@ }; }; - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - uart1_sleep: uart1_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - spi3_default: spi3_default { group1 { psels = , diff --git a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi index 92a2a757c55a..38b48f9f5eea 100644 --- a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi +++ b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi @@ -39,10 +39,6 @@ }; }; -&adc { - status = "okay"; -}; - &gpiote { status = "okay"; }; @@ -59,14 +55,6 @@ pinctrl-names = "default", "sleep"; }; -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - &spi3 { compatible = "nordic,nrf-spim"; status = "okay"; @@ -88,4 +76,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst index 97780246a742..5a890893c230 100644 --- a/boards/ct/ctcc/doc/index.rst +++ b/boards/ct/ctcc/doc/index.rst @@ -57,63 +57,7 @@ Hardware Supported Features ================== -The ``ctcc/nrf52840`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``ctcc/nrf9161`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| FLASH | external | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | LTE-M/NB-IoT, | -| | | DECT NR\+ | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -137,6 +81,8 @@ nRF9161: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for ``ctcc`` boards can be built in the usual way (see :ref:`build_an_application` for more details). diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst index 01ad4696ea23..8a5090a5ed4a 100644 --- a/boards/cypress/cy8ckit_062_ble/doc/index.rst +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -1,7 +1,4 @@ -.. _cy8ckit_062_ble: - -INFINEON PSOC 63 BLE Pioneer Kit -################################ +.. zephyr:board:: cy8ckit_062_ble Overview ******** @@ -30,10 +27,6 @@ enabling you to emulate a BLE host on your computer. The Cortex-M0+ is a primary core on the board's SoC. It starts first and enables the CM4 core. -.. image:: img/cy8ckit-062-ble.jpg - :align: center - :alt: CY8CKIT_062_BLE - 1. Battery charging indicator (LED6) 2. USB PD output voltage availability indicator (LED7) 3. KitProg2 USB Type-C connector (J10) @@ -147,6 +140,8 @@ To get the OpenOCD package, it is required that you Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with mass storage programming to provide debugging, flash programming, and serial communication over USB. There are also PSOC 6 program and debug headers J11 diff --git a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst index a0ad601ad633..dc201ecc7a78 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst +++ b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst @@ -1,7 +1,4 @@ -.. _cy8ckit_062_wifi_bt: - -INFINEON PSOC 6 WiFi-BT Pioneer Kit -################################### +.. zephyr:board:: cy8ckit_062_wifi_bt Overview ******** @@ -23,10 +20,6 @@ The PSOC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. The Cortex-M0+ is a primary core on the board's SoC. It starts first and enables the CM4 core. -.. image:: img/cy8ckit_062_wifi_bt_m0.jpg - :align: center - :alt: CY8CKIT_062_WIFI_BT - 1. USB PD output voltage availability indicator (LED7) 2. Battery charging indicator (LED6) 3. KitProg2 USB Type-C connector (J10) @@ -134,6 +127,8 @@ To get the OpenOCD package, it is required that you Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with mass storage programming to provide debugging, flash programming, and serial communication over USB. There are also PSOC 6 program and debug headers J11 diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 78a960ec2e4a..29959964a856 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -16,6 +16,15 @@ set(adafruit_feather_DEPRECATED adafruit_feather_nrf52840/nrf52840 ) +set(arduino_uno_r4_minima_DEPRECATED + arduino_uno_r4@minima +) +set(arduino_uno_r4_wifi_DEPRECATED + arduino_uno_r4@wifi +) +set(esp32c6_devkitc_DEPRECATED + esp32c6_devkitc/esp32c6/hpcore +) set(qemu_xtensa_DEPRECATED qemu_xtensa/dc233c ) @@ -37,3 +46,21 @@ set(mimxrt1060_evk_DEPRECATED set(mimxrt1060_evkb_DEPRECATED mimxrt1060_evk@B/mimxrt1062/qspi ) +set(neorv32_DEPRECATED + neorv32/neorv32/up5kdemo +) +set(xiao_esp32c6_DEPRECATED + xiao_esp32c6/esp32c6/hpcore +) +set(esp32_devkitc_wroom/esp32/procpu_DEPRECATED + esp32_devkitc/esp32/procpu +) +set(esp32_devkitc_wrover/esp32/procpu_DEPRECATED + esp32_devkitc/esp32/procpu +) +set(esp32_devkitc_wroom/esp32/appcpu_DEPRECATED + esp32_devkitc/esp32/appcpu +) +set(esp32_devkitc_wrover/esp32/appcpu_DEPRECATED + esp32_devkitc/esp32/appcpu +) diff --git a/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit b/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit new file mode 100644 index 000000000000..634561d9d121 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit @@ -0,0 +1,5 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DT_BL10_DEVKIT + select SOC_BL602C20Q2I diff --git a/boards/doiting/dt_bl10_devkit/board.cmake b/boards/doiting/dt_bl10_devkit/board.cmake new file mode 100644 index 000000000000..d8e6ac401479 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(bflb_mcu_tool --chipname bl602) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/doiting/dt_bl10_devkit/board.yml b/boards/doiting/dt_bl10_devkit/board.yml new file mode 100644 index 000000000000..9c080ef4bce4 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/board.yml @@ -0,0 +1,6 @@ +board: + name: dt_bl10_devkit + full_name: DT-BL10 coexistence Module Development Kit + vendor: doiting + socs: + - name: bl602c20q2i diff --git a/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp new file mode 100644 index 000000000000..e65768b9fab4 Binary files /dev/null and b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp differ diff --git a/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp new file mode 100644 index 000000000000..2efa8764c61a Binary files /dev/null and b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp differ diff --git a/boards/doiting/dt_bl10_devkit/doc/index.rst b/boards/doiting/dt_bl10_devkit/doc/index.rst new file mode 100644 index 000000000000..2f351a77f253 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/doc/index.rst @@ -0,0 +1,124 @@ +.. zephyr:board:: dt_bl10_devkit + +DT-BL10 Development Kit +####################### + +Overview +******** + +DT-BL10 Wi-Fi and BLE coexistence Module is a highly integrated single-chip +low power 802.11n Wireless LAN (WLAN) network controller. It combines an RISC +CPU, WLAN MAC, a lT1R capable WLAN baseband, RF, and Bluetooth in a single chip. +It also provides a bunch of configurable GPIO, which are configured as digital +peripherals for different applications and control usage. + +DT-BL10 WiFi Module use BL602 as Wi-Fi and BLE coexistence soc chip. DT-BL10 +WiFi Module integrates internal memories for complete WIFI protocol functions. +The embedded memory configuration also provides simple application developments. + +DT-BL10 WiFi module supports the standard IEEE 802.11 b/g/n/e/i protocol and the +complete TCP/IP protocol stack. User can use it to add the WiFi function for the +installed devices, and also can be viewed as a independent network controller. + +Hardware +******** + +For more information about the Bouffalo Lab BL-602 MCU: + +- `Bouffalo Lab BL602 MCU Website`_ +- `Bouffalo Lab BL602 MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `dt_bl10_devkit Schematic`_ +- `Doctors of Intelligence & Technology (www.doiting.com)`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The DT-BL10 board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``dt_bl10_devkit`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dt_bl10_devkit + :goals: build + +#. To flash an image using blflash runner: + + #. Press D8 button + + #. Press and release EN button + + #. Release D8 button + + .. code-block:: console + + west flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release EN button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0-4682-g21b20de1eb34 *** + Hello World! dt_bl10_devkit/bl602c20q2i + +Congratulations, you have ``dt_bl10_devkit`` configured and running Zephyr. + + +.. _Bouffalo Lab BL602 MCU Website: + https://www.bouffalolab.com/bl602 + +.. _Bouffalo Lab BL602 MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _dt_bl10_devkit Schematic: + https://github.com/SmartArduino/Doiting_BL/blob/master/board/DT-BL10%20User%20Mannual.pdf + +.. _Doctors of Intelligence & Technology (www.doiting.com): + https://www.doiting.com + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi new file mode 100644 index 000000000000..6909cc447159 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021-2025 ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + pinmux = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts new file mode 100644 index 000000000000..34ce0613736a --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021-2025 ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "dt_bl10_devkit-pinctrl.dtsi" + +/ { + model = "2.4GHz Wi-Fi and BLE coexistence Module Development Kit"; + compatible = "bflb,bl602"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0xc00000>; + + flash0: flash@0 { + compatible = "issi,is25lp128", "jedec,spi-nor"; + status = "disabled"; + size = ; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = ; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml new file mode 100644 index 000000000000..8a0921fd9d88 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +identifier: dt_bl10_devkit +name: DT-BL10 coexistence Module Development Kit +type: mcu +arch: riscv +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +supported: + - pinctrl + - uart +vendor: doiting diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig new file mode 100644 index 000000000000..b4c911b77c40 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/doiting/index.rst b/boards/doiting/index.rst new file mode 100644 index 000000000000..8be7f522dbde --- /dev/null +++ b/boards/doiting/index.rst @@ -0,0 +1,10 @@ +.. _boards-doiting: + +Doctors of Intelligence & Technology +#################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/dptechnics/walter/doc/index.rst b/boards/dptechnics/walter/doc/index.rst index c77e266f52be..eb5dc5e3d50f 100644 --- a/boards/dptechnics/walter/doc/index.rst +++ b/boards/dptechnics/walter/doc/index.rst @@ -58,47 +58,7 @@ Form factor Supported Features ================== -Current Zephyr's Walter board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ -| Cellular | on-board | modem_cellular | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Prerequisites ------------- @@ -117,6 +77,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.dts b/boards/dptechnics/walter/walter_esp32s3_procpu.dts index 8d864885e0f0..0568d597960b 100644 --- a/boards/dptechnics/walter/walter_esp32s3_procpu.dts +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.dts @@ -49,6 +49,7 @@ status = "okay"; compatible = "sqn,gm02s"; mdm-reset-gpios = <&gpio1 13 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + mdm-wake-gpios = <&gpio1 14 (GPIO_OPEN_SOURCE | GPIO_ACTIVE_HIGH)>; }; }; @@ -120,3 +121,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst index 999c809a90f4..d5981b51817b 100644 --- a/boards/dragino/lsn50/doc/index.rst +++ b/boards/dragino/lsn50/doc/index.rst @@ -78,24 +78,7 @@ More information about STM32L072CZ can be found here: Supported Features ================== -The Zephyr Dragino LSN50 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/dragino/lsn50/dragino_lsn50_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -130,6 +113,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``dragino_lsn50`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst index c18bb7eee401..c99e6c87bdcd 100644 --- a/boards/dragino/nbsn95/doc/index.rst +++ b/boards/dragino/nbsn95/doc/index.rst @@ -77,24 +77,7 @@ More information about STM32L072CZ can be found here: Supported Features ================== -The Zephyr Dragino NBSN95 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/dragino/nbsn95/dragino_nbsn95_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -129,6 +112,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``dragino_nbsn95`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/ebyte/e73_tbb/board.cmake b/boards/ebyte/e73_tbb/board.cmake index f99446d144d0..5db65eede593 100644 --- a/boards/ebyte/e73_tbb/board.cmake +++ b/boards/ebyte/e73_tbb/board.cmake @@ -2,6 +2,7 @@ board_runner_args(jlink "--device=nrf52" "--speed=4000") board_runner_args(pyocd "--target=nrf52" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst index 5d1327e322c7..68bd2608dc91 100644 --- a/boards/ebyte/e73_tbb/doc/index.rst +++ b/boards/ebyte/e73_tbb/doc/index.rst @@ -39,42 +39,8 @@ and solder NFC antenna using NFC_ANT connector. Supported Features ================== -The ebyte_e73_tbb/nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. +.. zephyr:board-supported-hw:: + See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_ for a complete list of nRF52832 hardware features. @@ -169,6 +135,8 @@ NFC_ANT Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/electronut/nrf52840_blip/doc/index.rst b/boards/electronut/nrf52840_blip/doc/index.rst index 03dfff0bf566..376412e4d407 100644 --- a/boards/electronut/nrf52840_blip/doc/index.rst +++ b/boards/electronut/nrf52840_blip/doc/index.rst @@ -34,43 +34,7 @@ is 32 MHz. Supported Features ================== -The nrf52840_blip board configuration supports the following -hardware features currently: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -116,6 +80,8 @@ MicroSD is connected to these pins, and CS pin is connected to P0.17. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``nrf52840_blip`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details); The onboard Black Magic diff --git a/boards/electronut/nrf52840_papyr/board.cmake b/boards/electronut/nrf52840_papyr/board.cmake index 65580b0fef53..3ca8757d6132 100644 --- a/boards/electronut/nrf52840_papyr/board.cmake +++ b/boards/electronut/nrf52840_papyr/board.cmake @@ -2,4 +2,5 @@ board_runner_args(nrfjprog "--softreset") include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) diff --git a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst index 391175eebc26..f674496b0218 100644 --- a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst +++ b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst @@ -36,41 +36,7 @@ is 32 MHz. Supported Features ================== -The nrf52840_papyr board configuration supports the following -hardware features currently: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -123,6 +89,8 @@ Other pins used by the e-paper display are: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``nrf52840_papyr`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details); Black Magic diff --git a/boards/element14/warp7/doc/index.rst b/boards/element14/warp7/doc/index.rst index d0940f5271ac..016681c30ab0 100644 --- a/boards/element14/warp7/doc/index.rst +++ b/boards/element14/warp7/doc/index.rst @@ -68,33 +68,7 @@ For more information about the i.MX7 SoC and WaRP7, see these references: Supported Features ================== -The WaRP7 configuration supports the following hardware features on the -Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4_defconfig` - -Other hardware features are not currently supported by the port. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -136,6 +110,8 @@ the number 6 is used in the mikroBUS connector. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by the A7 core. The A7 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml index 24bcdb296fb6..db5295b3b693 100644 --- a/boards/element14/warp7/warp7_mcimx7d_m4.yaml +++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml @@ -20,4 +20,3 @@ testing: supported: - gpio - i2c -vendor: nxp diff --git a/boards/ene/kb1200_evb/doc/index.rst b/boards/ene/kb1200_evb/doc/index.rst index 6558b8dad545..2bd60859af77 100644 --- a/boards/ene/kb1200_evb/doc/index.rst +++ b/boards/ene/kb1200_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _ene_kb1200_evb: - -ENE KB1200_EVB -############## +.. zephyr:board:: kb1200_evb Overview ******** @@ -24,38 +21,7 @@ Hardware Supported Features ================== -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port/controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PMU | on-chip | power management | -+-----------+------------+-------------------------------------+ -| PSL | on-chip | power switch logic | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pulse width modulator | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer sensor | -+-----------+------------+-------------------------------------+ -| SER | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) +.. zephyr:board-supported-hw:: System Clock ============ @@ -67,6 +33,8 @@ See Processor clock control register (refer 5.1 General Configuration) Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/enjoydigital/litex_vexriscv/board.yml b/boards/enjoydigital/litex_vexriscv/board.yml index c5cd6829183c..c74d1ff23216 100644 --- a/boards/enjoydigital/litex_vexriscv/board.yml +++ b/boards/enjoydigital/litex_vexriscv/board.yml @@ -1,6 +1,6 @@ board: name: litex_vexriscv full_name: LiteX VexRiscv - vendor: litex + vendor: enjoydigital socs: - name: litex_vexriscv diff --git a/boards/enjoydigital/litex_vexriscv/doc/index.rst b/boards/enjoydigital/litex_vexriscv/doc/index.rst index f9764907eb44..bd47c381a73b 100644 --- a/boards/enjoydigital/litex_vexriscv/doc/index.rst +++ b/boards/enjoydigital/litex_vexriscv/doc/index.rst @@ -1,7 +1,4 @@ -.. _litex-vexriscv: - -LiteX VexRiscv -############## +.. zephyr:board:: litex_vexriscv LiteX VexRiscv is an example of a system on a chip (SoC) that consists of a `VexRiscv processor `_ @@ -20,10 +17,6 @@ LiteX VexRiscv SoC implementation generated for the `_ or `SDI-MIPI Video Converter `_. -.. image:: img/litex_vexriscv.jpg - :align: center - :alt: LiteX VexRiscv on Digilent Arty 35T Board - LiteX is based on `Migen `_/`MiSoC SoC builder `_ and provides ready-made system components such as buses, streams, interconnects, @@ -49,6 +42,11 @@ using the `Zephyr on LiteX VexRiscv `_ reference platform. You can also use the official LiteX SoC Builder. +Supported Features +****************** + +.. zephyr:board-supported-hw:: + Bitstream generation ******************** diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts index 19f56f8b2897..cb3082619031 100644 --- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts +++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts @@ -72,6 +72,10 @@ status = "okay"; }; +&i2c1 { + status = "okay"; +}; + &pwm0 { status = "okay"; }; diff --git a/boards/espressif/esp32_devkitc/Kconfig b/boards/espressif/esp32_devkitc/Kconfig new file mode 100644 index 000000000000..3187645aa972 --- /dev/null +++ b/boards/espressif/esp32_devkitc/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32_DEVKITC_ESP32_PROCPU + default 256 if BOARD_ESP32_DEVKITC_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc b/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc new file mode 100644 index 000000000000..b843530ace2d --- /dev/null +++ b/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc @@ -0,0 +1,7 @@ +# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC + select SOC_ESP32_WROVER_E_N4R8 + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild b/boards/espressif/esp32_devkitc/Kconfig.sysbuild similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc/Kconfig.sysbuild diff --git a/boards/espressif/esp32_devkitc_wroom/board.cmake b/boards/espressif/esp32_devkitc/board.cmake similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/board.cmake rename to boards/espressif/esp32_devkitc/board.cmake diff --git a/boards/espressif/esp32_devkitc/board.yml b/boards/espressif/esp32_devkitc/board.yml new file mode 100644 index 000000000000..fbd9c38a48a3 --- /dev/null +++ b/boards/espressif/esp32_devkitc/board.yml @@ -0,0 +1,6 @@ +board: + name: esp32_devkitc + full_name: ESP32-DevKitC + vendor: espressif + socs: + - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg b/boards/espressif/esp32_devkitc/doc/img/esp32_devkitc_wrover.jpg similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg rename to boards/espressif/esp32_devkitc/doc/img/esp32_devkitc_wrover.jpg diff --git a/boards/espressif/esp32_devkitc/doc/index.rst b/boards/espressif/esp32_devkitc/doc/index.rst new file mode 100644 index 000000000000..b7bf86406b03 --- /dev/null +++ b/boards/espressif/esp32_devkitc/doc/index.rst @@ -0,0 +1,256 @@ +.. zephyr:board:: esp32_devkitc + +Overview +******** + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. For more information, check `ESP32-DevKitC`_. + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference +manual at `ESP32 Technical Reference Manual`_. + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DevKitC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32_devkitc + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc + +Debugging +********* + +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. + +On the ESP32-DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +References +********** + +.. target-notes:: + +.. _`ESP32-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitc/index.html +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc-pinctrl.dtsi b/boards/espressif/esp32_devkitc/esp32_devkitc-pinctrl.dtsi new file mode 100644 index 000000000000..dbfd9d07b803 --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc-pinctrl.dtsi @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart2_default: uart2_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts new file mode 100644 index 000000000000..62427d3d2ded --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml new file mode 100644 index 000000000000..8f2cf6b9cb8d --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc/esp32/appcpu +name: ESP32-DevkitC APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu_defconfig similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig rename to boards/espressif/esp32_devkitc/esp32_devkitc_appcpu_defconfig diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts new file mode 100644 index 000000000000..b92d20ec1361 --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Espressif ESP32-DevkitC PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml new file mode 100644 index 000000000000..7a1a124e7d7b --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml @@ -0,0 +1,22 @@ +identifier: esp32_devkitc/esp32/procpu +name: ESP32-DevkitC PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - i2s + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +vendor: espressif diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig new file mode 100644 index 000000000000..ea5684dc83ec --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/espressif/esp32_devkitc_wroom/support/openocd.cfg b/boards/espressif/esp32_devkitc/support/openocd.cfg similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/support/openocd.cfg rename to boards/espressif/esp32_devkitc/support/openocd.cfg diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig deleted file mode 100644 index 391149964122..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - default 256 if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom deleted file mode 100644 index 148838c43185..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROOM - select SOC_ESP32_WROOM_32UE_N4 - select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/board.yml b/boards/espressif/esp32_devkitc_wroom/board.yml deleted file mode 100644 index e0d766da0d1c..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32_devkitc_wroom - full_name: ESP32-DevKitC-WROOM - vendor: espressif - socs: - - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg b/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg deleted file mode 100644 index 2b8317e29ebb..000000000000 Binary files a/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg and /dev/null differ diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst deleted file mode 100644 index 228660a603aa..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ /dev/null @@ -1,292 +0,0 @@ -.. zephyr:board:: esp32_devkitc_wroom - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. For more information, check `ESP32-DevKitC-WROOM`_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference -manual at `ESP32 Technical Reference Manual`_. - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DevKitC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-DevKitC-WROOM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -Simple boot -=========== - -The board could be loaded using the single binary image, without 2nd stage bootloader. -It is the default option when building the application without additional configuration. - -.. note:: - - Simple boot does not provide any security features nor OTA updates. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be built (and flashed) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - - .. code:: cfg - - CONFIG_BOOTLOADER_MCUBOOT=y - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be built one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wroom - -Debugging -********* - -ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. - -On the ESP32-DevKitC-WROOM board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. - -Here is an example for building the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -References -********** - -.. target-notes:: - -.. _`ESP32-DevKitC-WROOM`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# -.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf -.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi deleted file mode 100644 index b1f03780559b..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -&pinctrl { - - uart0_default: uart0_default { - group1 { - pinmux = ; - output-high; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart1_default: uart1_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart2_default: uart2_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - spim2_default: spim2_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - spim3_default: spim3_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , - ; - bias-pull-up; - drive-open-drain; - output-high; - }; - }; -}; - diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts deleted file mode 100644 index c88ae757867f..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include - -/ { - model = "Espressif ESP32-DevkitC APPCPU"; - compatible = "espressif,esp32"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&ipm0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml deleted file mode 100644 index 26d4e67df3fd..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wroom/esp32/appcpu -name: ESP32 DEVKITC WROOM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig deleted file mode 100644 index cc70c2779600..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CLOCK_CONTROL=y -CONFIG_CONSOLE=n -CONFIG_SERIAL=n -CONFIG_UART_CONSOLE=n -CONFIG_GPIO=n diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts deleted file mode 100644 index 783a8f2a7f7b..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wroom-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "Espressif ESP32-DevkitC PROCPU"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&psram0 { - status = "disabled"; -}; - -&esp32_bt_hci { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml deleted file mode 100644 index 7bc3c8feb55f..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: esp32_devkitc_wroom/esp32/procpu -name: ESP32-DevkitC-WROOM-32D -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig deleted file mode 100644 index 172a46d10057..000000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig deleted file mode 100644 index 6442ca472791..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - default 256 if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover deleted file mode 100644 index 1e107bf8b4a2..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROVER - select SOC_ESP32_WROVER_E_N4R8 - select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/board.cmake b/boards/espressif/esp32_devkitc_wrover/board.cmake deleted file mode 100644 index ad53de11770b..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") - set(OPENOCD OPENOCD-NOTFOUND) -endif() - -find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) - -include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32_devkitc_wrover/board.yml b/boards/espressif/esp32_devkitc_wrover/board.yml deleted file mode 100644 index 2a8e2a226fd8..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32_devkitc_wrover - full_name: ESP32-DevKitC-WROVER - vendor: espressif - socs: - - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst deleted file mode 100644 index cf1fb64f32f2..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ /dev/null @@ -1,292 +0,0 @@ -.. zephyr:board:: esp32_devkitc_wrover - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. For more information, check `ESP32-DevKitC-WROVER`_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference -manual at `ESP32 Technical Reference Manual`_. - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DevKitC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-DevKitC-WROVER board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -Simple boot -=========== - -The board could be loaded using the single binary image, without 2nd stage bootloader. -It is the default option when building the application without additional configuration. - -.. note:: - - Simple boot does not provide any security features nor OTA updates. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be built (and flashed) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - - .. code:: cfg - - CONFIG_BOOTLOADER_MCUBOOT=y - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be built one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wrover - -Debugging -********* - -ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. - -On the ESP32-DevKitC-WROVER board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. - -Here is an example for building the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -References -********** - -.. target-notes:: - -.. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# -.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf -.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi deleted file mode 100644 index f4f51cce98ae..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -&pinctrl { - - uart0_default: uart0_default { - group1 { - pinmux = ; - output-high; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart1_default: uart1_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart2_default: uart2_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - spim2_default: spim2_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - spim3_default: spim3_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , - ; - bias-pull-up; - drive-open-drain; - output-high; - }; - }; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts deleted file mode 100644 index f6fb39576f2e..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include - -/ { - model = "Espressif ESP32-DevkitC WROVER-E APPCPU"; - compatible = "espressif,esp32"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&ipm0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml deleted file mode 100644 index 040828238016..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wrover/esp32/appcpu -name: ESP32-DevkitC-WROVER-E APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts deleted file mode 100644 index 33f0f3f134b3..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wrover-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&esp32_bt_hci { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml deleted file mode 100644 index 62e40f71e937..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: esp32_devkitc_wrover/esp32/procpu -name: ESP32-DevkitC-WROVER-E PROCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig deleted file mode 100644 index 172a46d10057..000000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index 7233284d3141..22a942989fda 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -34,6 +34,13 @@ features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger. +Hardware +******** + +Supported Features +================== + +.. zephyr:board-supported-hw:: Functionality Overview ====================== @@ -425,6 +432,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi index 3e30654db8b8..1b6bd6b701cc 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Grant Ramsay + * Copyright (c) 2022-2025 Grant Ramsay * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,4 +40,33 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; }; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts index 799c17ad8495..bf2fbbd6d3a7 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Grant Ramsay + * Copyright (c) 2022-2025 Grant Ramsay * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,6 +43,18 @@ status = "okay"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; @@ -89,3 +101,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml index fb3c3cdd704a..f6fd5a5f410c 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml @@ -10,4 +10,5 @@ supported: - uart - nvs - pwm + - i2s vendor: espressif diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst index a57d0be26235..eae08a6b8fcc 100644 --- a/boards/espressif/esp32c3_devkitc/doc/index.rst +++ b/boards/espressif/esp32c3_devkitc/doc/index.rst @@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-C3-DevKitC board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements ******************* @@ -98,6 +64,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts index 86326fcc077f..ec61f303a6c6 100644 --- a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts @@ -97,3 +97,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index 24eb23bc7b8a..d4fcb4e1713a 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-C3-Devkitm board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements ******************* @@ -98,6 +64,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index 25bd583daee3..2e1b41edfc19 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -103,3 +103,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst index a6f41a01866c..144b6948b85e 100644 --- a/boards/espressif/esp32c3_rust/doc/index.rst +++ b/boards/espressif/esp32c3_rust/doc/index.rst @@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-C3-DevKit-RUST board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: I2C Peripherals =============== @@ -143,6 +109,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.dts b/boards/espressif/esp32c3_rust/esp32c3_rust.dts index 867fa84adcf6..9c931e91f578 100644 --- a/boards/espressif/esp32c3_rust/esp32c3_rust.dts +++ b/boards/espressif/esp32c3_rust/esp32c3_rust.dts @@ -128,3 +128,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32c6_devkitc/Kconfig b/boards/espressif/esp32c6_devkitc/Kconfig index c6a99b1032dc..e24ba970a9bb 100644 --- a/boards/espressif/esp32c6_devkitc/Kconfig +++ b/boards/espressif/esp32c6_devkitc/Kconfig @@ -3,4 +3,5 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int - default 4096 + default 4096 if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE + default 256 if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc index 4bd1fce4efc3..9b30251fea4f 100644 --- a/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc +++ b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc @@ -5,3 +5,5 @@ config BOARD_ESP32C6_DEVKITC select SOC_ESP32_C6_WROOM_1U_N8 + select SOC_ESP32C6_HPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE + select SOC_ESP32C6_LPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst index ab81b187d746..ee0f04afaa77 100644 --- a/boards/espressif/esp32c6_devkitc/doc/index.rst +++ b/boards/espressif/esp32c6_devkitc/doc/index.rst @@ -84,43 +84,7 @@ manual at `ESP32-C6 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-C6-DevKitC board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements ******************* @@ -142,6 +106,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== @@ -183,7 +149,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west :zephyr-app: samples/hello_world - :board: esp32c6_devkitc + :board: esp32c6_devkitc/esp32c6/hpcore :goals: build :west-args: --sysbuild :compact: @@ -232,7 +198,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: esp32c6_devkitc + :board: esp32c6_devkitc/esp32c6/hpcore :goals: build The usual ``flash`` target will work with the ``esp32c6_devkitc`` board @@ -241,7 +207,7 @@ application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: esp32c6_devkitc + :board: esp32c6_devkitc/esp32c6/hpcore :goals: flash Open the serial monitor using the following command: @@ -256,7 +222,7 @@ message in the monitor: .. code-block:: console ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32c6_devkitc + Hello World! esp32c6_devkitc/esp32c6/hpcore Debugging ********* @@ -273,7 +239,7 @@ Here is an example for building the :zephyr:code-sample:`hello_world` applicatio .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: esp32c6_devkitc + :board: esp32c6_devkitc/esp32c6/hpcore :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= @@ -281,9 +247,32 @@ You can debug an application in the usual way. Here is an example for the :zephy .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: esp32c6_devkitc + :board: esp32c6_devkitc/esp32c6/hpcore :goals: debug +Low-Power CPU (LP CORE) +*********************** + +The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE). +The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus +interface for memory and peripheral access. + +The LP Core is in sleep mode by default. It has two application scenarios: + +- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations. +- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events. + +For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference +manual at `ESP32-C6 Technical Reference Manual`_. + +The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding +the following configuration to the project: + +.. code:: cfg + + CONFIG_ULP_COPROC_ENABLED=y + +See :zephyr:code-sample-category:`lp-core` folder as code reference. References ********** diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts deleted file mode 100644 index 896ae30530cc..000000000000 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "esp32c6_devkitc-pinctrl.dtsi" -#include -#include - -/ { - model = "esp32c6_devkitc"; - compatible = "espressif,esp32c6"; - - chosen { - zephyr,sram = &sramhp; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - sw0 = &user_button1; - watchdog0 = &wdt0; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button1: button_1 { - label = "User SW1"; - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml deleted file mode 100644 index 95385596d9de..000000000000 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: esp32c6_devkitc -name: ESP32-C6 -vendor: espressif -type: mcu -arch: riscv -toolchain: - - zephyr -supported: - - adc - - gpio - - watchdog - - uart - - dma - - pwm - - spi - - counter - - entropy - - i2c diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore-pinctrl.dtsi similarity index 100% rename from boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi rename to boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore-pinctrl.dtsi diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts new file mode 100644 index 000000000000..ef8dbea59b38 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c6_devkitc_hpcore-pinctrl.dtsi" +#include +#include + +/ { + model = "esp32c6_devkitc HP Core"; + compatible = "espressif,esp32c6"; + + chosen { + zephyr,sram = &sramhp; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button1; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml new file mode 100644 index 000000000000..4bc3c0cde260 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml @@ -0,0 +1,22 @@ +identifier: esp32c6_devkitc/esp32c6/hpcore +name: ESP32-C6-DevKitC HP Core +vendor: espressif +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy + - i2c + - i2s +testing: + ignore_tags: + - bluetooth diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore_defconfig similarity index 100% rename from boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig rename to boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore_defconfig diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts new file mode 100644 index 000000000000..739781e692b5 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "Espressif ESP32C6-DevkitC LPCORE"; + compatible = "espressif,esp32c6"; + + chosen { + zephyr,sram = &sramlp; + zephyr,code-partition = &slot0_lpcore_partition; + zephyr,console = &lp_uart; + zephyr,shell-uart = &lp_uart; + }; +}; + +&lp_uart { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml new file mode 100644 index 000000000000..49e25bcdba0a --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml @@ -0,0 +1,19 @@ +identifier: esp32c6_devkitc/esp32c6/lpcore +name: ESP32-C6-DevKitC LP Core +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - cpu + - uart + - serial +testing: + only_tags: + - introduction + ignore_tags: + - kernel + - posix + - chre + - cpp +vendor: espressif diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig new file mode 100644 index 000000000000..04974098f6ce --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +# Memory protection +CONFIG_THREAD_STACK_INFO=n +CONFIG_THREAD_CUSTOM_DATA=n + +# Boot +CONFIG_BOOT_BANNER=n + +# Console +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_PRINTK=n +CONFIG_CBPRINTF_NANO=y + +# Build +CONFIG_SIZE_OPTIMIZATIONS=y +CONFIG_BUSYWAIT_CPU_LOOPS_PER_USEC=4 diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index e5cb0ff6191d..63bf3eca409b 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -41,39 +41,7 @@ manual at `ESP32-S2 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-S2-devkitc board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements =================== @@ -95,6 +63,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi index 756aaf9b5b72..434260d9486e 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -65,4 +65,19 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; }; diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts index f60ce264843f..337a63b6b56d 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -96,6 +96,12 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &trng0 { status = "okay"; }; @@ -123,3 +129,7 @@ &dac { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml index 44a6f971e3b7..b3598a28d9c0 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml @@ -9,6 +9,7 @@ supported: - dac - gpio - i2c + - i2s - watchdog - uart - nvs @@ -19,4 +20,7 @@ supported: - input - can - dma +testing: + ignore_tags: + - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index a2ad776acfed..d86a986b5e63 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -41,39 +41,7 @@ manual at `ESP32-S2 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-S2-Saola board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements =================== @@ -95,6 +63,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi index 7ab4fc671194..5b402c838cfa 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi +++ b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -65,4 +65,19 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; }; diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts index 88490f1d551c..23249ceb3f64 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola.dts +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -96,6 +96,12 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &trng0 { status = "okay"; }; @@ -119,3 +125,7 @@ &wdt0 { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml index bebe2a293a8a..e8a37ffd2edc 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml @@ -9,6 +9,7 @@ supported: - dac - gpio - i2c + - i2s - watchdog - uart - nvs @@ -17,4 +18,7 @@ supported: - counter - entropy - input +testing: + ignore_tags: + - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index 008b64fecae7..4d5b07797a2e 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -81,41 +81,7 @@ manual at `ESP32-S3 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-S3-DevKitC board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Prerequisites ------------- @@ -134,6 +100,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index 48806ab5a4c7..a7dec600f433 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -147,3 +147,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index ada774ec2a1e..044a3a6a6607 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -81,41 +81,7 @@ manual at `ESP32-S3 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP32-S3-DevKitM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Prerequisites ------------- @@ -134,6 +100,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts index 89c5b8c16418..c468871e25e3 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts @@ -147,3 +147,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst index 662c4e519987..0657fa201805 100644 --- a/boards/espressif/esp32s3_eye/doc/index.rst +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -3,8 +3,8 @@ Overview ******** -The ESP32-S3-EYE is a small-sized AI development board produced by [Espressif](https://espressif.com). -It is based on the [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) SoC. +The ESP32-S3-EYE is a small-sized AI development board produced by `Espressif`_. +It is based on the `ESP32-S3`_ SoC. It features a 2-Megapixel camera, an LCD display, and a microphone, which are used for image recognition and audio processing. ESP32-S3-EYE offers plenty of storage, with an 8 MB Octal PSRAM and a 8 MB flash. @@ -17,6 +17,11 @@ ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display. The main board and sub board are connected through pin headers. +Supported Features +------------------ + +.. zephyr:board-supported-hw:: + Block Diagram ------------- @@ -130,6 +135,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot ----------- @@ -251,7 +258,7 @@ Debugging ESP32-S3 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of the project. The custom OpenOCD can be obtained at -`OpenOCD ESP32`_ +`OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the @@ -275,3 +282,7 @@ application. :goals: debug .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +.. _`Espressif`: https://espressif.com + +.. _`ESP32-S3`: https://www.espressif.com/en/products/socs/esp32-s3 diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts index 1b2afa8b83af..7391ad2357e4 100644 --- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts @@ -204,3 +204,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst index 79c729461503..c5e00b5b5b44 100644 --- a/boards/espressif/esp8684_devkitm/doc/index.rst +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -46,33 +46,7 @@ For detailed information check `ESP8684 Technical Reference Manual`_. Supported Features ================== -Current Zephyr's ESP8684-DevKitM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: For a getting started user guide, please check `ESP8684-DevKitM User Guide`_. @@ -96,6 +70,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts index a6a76ac4756b..8081d955c8fd 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts @@ -60,3 +60,7 @@ &timer0 { status = "disabled"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 96f1c0570c2d..0c5a2ee8dd4e 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -441,45 +441,7 @@ Turn the Power Switch to ON, the 5V Power On LED should light up. Supported Features ================== -Current Zephyr's ESP32-Wrover-Kit board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: System requirements =================== @@ -501,6 +463,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts index 614bd1ec54f5..552829c4c526 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts @@ -218,3 +218,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/ezurio/bl5340_dvk/Kconfig b/boards/ezurio/bl5340_dvk/Kconfig deleted file mode 100644 index e84a37972a00..000000000000 --- a/boards/ezurio/bl5340_dvk/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2021 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "bl5340_dvk/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the bl5340_dvk_cpunet for - Bluetooth applications. - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -if BOARD_BL5340_DVK_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "bl5340_dvk/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi index 2fc651230f45..b85e3d03dc2d 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi @@ -57,5 +57,5 @@ reg = <0x20040000 0x30000>; }; -/* Include default shared RAM configuration file */ -#include +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi index 1f5fc0bb3405..ce2e145d5875 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi @@ -63,5 +63,5 @@ }; }; -/* Include default shared RAM configuration file */ -#include +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi new file mode 100644 index 000000000000..fbb059494c36 --- /dev/null +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019 Nordic Semiconductor ASA + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Default shared SRAM planning when building for BL5340 DVK. + * This file is included by both nRF5340 CPUAPP (Application MCU) + * and nRF5340 CPUNET (Network MCU). + * - 64 kB SRAM allocated as Shared memory (sram0_shared) + * - Region defined after the image SRAM of Application MCU + */ + +/ { + chosen { + /* shared memory reserved for the inter-processor communication */ + zephyr,ipc_shm = &sram0_shared; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_shared: memory@20070000 { + /* SRAM allocated to shared memory */ + reg = <0x20070000 0x10000>; + }; + }; +}; diff --git a/boards/ezurio/bl5340_dvk/board.cmake b/boards/ezurio/bl5340_dvk/board.cmake index 15aec8e6a36d..41a597dead84 100644 --- a/boards/ezurio/bl5340_dvk/board.cmake +++ b/boards/ezurio/bl5340_dvk/board.cmake @@ -16,6 +16,6 @@ if(CONFIG_TFM_FLASH_MERGED_BINARY) set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) endif() -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst index b19a0516c30d..35ce806fc535 100644 --- a/boards/ezurio/bl5340_dvk/doc/index.rst +++ b/boards/ezurio/bl5340_dvk/doc/index.rst @@ -56,78 +56,8 @@ is 32MHz. Supported Features ================== -The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `Nordic Semiconductor Infocenter`_ for a complete list of hardware features. @@ -261,6 +191,8 @@ Security components Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The BL5340's application core supports the Armv8-M Security Extension. Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default boot in the Secure state. diff --git a/boards/ezurio/bl54l15_dvk/Kconfig b/boards/ezurio/bl54l15_dvk/Kconfig new file mode 100644 index 000000000000..412d5c5b3dd6 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# BL54L15 DVK board configuration + +if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS + +DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS diff --git a/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk b/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk new file mode 100644 index 000000000000..739ab7de8a59 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL54L15_DVK + select SOC_NRF54L10_CPUAPP if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS + select SOC_NRF54L15_CPUAPP if BOARD_BL54L15_DVK_NRF54L15_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15_DVK_NRF54L15_CPUFLPR || \ + BOARD_BL54L15_DVK_NRF54L15_CPUFLPR_XIP diff --git a/boards/ezurio/bl54l15_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig new file mode 100644 index 000000000000..61d46eebccfb --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP + +if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi new file mode 100644 index 000000000000..62aa39437b8c --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +/* Get a node label for wi-fi spi to use in shield files */ +wifi_spi: &spi22 {}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts new file mode 100644 index 000000000000..3d9336bbeab9 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54l_10_15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp"; + model = "Ezurio BL54L15 DVK nRF54L10 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +/* FLPR not supported yet, give all SRAM and RRAM to the APP core */ +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(192)>; + ranges = <0x0 0x20000000 DT_SIZE_K(192)>; +}; + +&cpuapp_rram { + reg = <0x0 DT_SIZE_K(1022)>; +}; + +/* These partition sizes assume no FLPR area in RRAM */ +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(224)>; + }; + + slot0_ns_partition: partition@48000 { + label = "image-0-nonsecure"; + reg = <0x48000 DT_SIZE_K(224)>; + }; + + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x80000 DT_SIZE_K(224)>; + }; + + slot1_ns_partition: partition@b8000 { + label = "image-1-nonsecure"; + reg = <0xb8000 DT_SIZE_K(224)>; + }; + + /* 32K from 0xf0000 to 0xf7fff reserved for TF-M partitions */ + + storage_partition: partition@f8000 { + label = "storage"; + reg = <0xf8000 DT_SIZE_K(28)>; + }; + + /* 2K from 0xff000 to 0xff7ff unused */ + }; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml new file mode 100644 index 000000000000..0a53875b7494 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l10/cpuapp +name: BL54L15-DVK-nRF54L10-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 192 +flash: 230 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig new file mode 100644 index 000000000000..c460d11847e9 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts new file mode 100644 index 000000000000..02d900390cca --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include "nrf54l_10_15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp"; + model = "Ezurio BL54L15 DVK nRF54L10 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &sram0_ns; + zephyr,entropy = &psa_rng; + }; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; +}; + +/ { + /* + * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support. + * - Lowest 96 kB SRAM allocated to Secure image (sram0_s). + * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns). + * + * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for + * the FLPR MCU. + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 DT_SIZE_K(72)>; + }; + + sram0_ns: image_ns@20012000 { + /* Non-Secure image memory */ + reg = <0x20012000 DT_SIZE_K(72)>; + }; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + /* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the + * last 62kB are reserved for the FLPR MCU. + * + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(384)>; + }; + + tfm_ps_partition: partition@60000 { + label = "tfm-ps"; + reg = <0x00060000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@64000 { + label = "tfm-its"; + reg = <0x00064000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@68000 { + label = "tfm-otp"; + reg = <0x00068000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@6A000 { + label = "image-0-nonsecure"; + reg = <0x0006A000 DT_SIZE_K(504)>; + }; + + storage_partition: partition@E8000 { + label = "storage"; + reg = <0x000E8000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml new file mode 100644 index 000000000000..d2ad19f03c4a --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l10/cpuapp/ns +name: BL54L15-DVK-nRF54l10-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 192 +flash: 1022 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig new file mode 100644 index 000000000000..dea04c45f20c --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# Support for silence logging is not supported at the moment +# Tracked by: NCSDK-31930 +CONFIG_TFM_LOG_LEVEL_SILENCE=n + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts new file mode 100644 index 000000000000..ef92bda99301 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54l_10_15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp"; + model = "Ezurio BL54L15_DVK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(324)>; + }; + + slot0_ns_partition: partition@61000 { + label = "image-0-nonsecure"; + reg = <0x61000 DT_SIZE_K(324)>; + }; + + slot1_partition: partition@b2000 { + label = "image-1"; + reg = <0xb2000 DT_SIZE_K(324)>; + }; + + slot1_ns_partition: partition@103000 { + label = "image-1-nonsecure"; + reg = <0x103000 DT_SIZE_K(324)>; + }; + + /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ + storage_partition: partition@15c000 { + label = "storage"; + reg = <0x15c000 DT_SIZE_K(36)>; + }; + }; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml new file mode 100644 index 000000000000..abcf0f54482a --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l15/cpuapp +name: BL54L15-DVK-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 188 +flash: 324 +supported: + - adc + - counter + - dmic + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig new file mode 100644 index 000000000000..c460d11847e9 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts new file mode 100644 index 000000000000..38712ba70744 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include "nrf54l_10_15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp"; + model = "Ezurio BL54L15 DVK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &sram0_ns; + zephyr,entropy = &psa_rng; + }; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; +}; + +/ { + /* + * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support + * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). + * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). + * + * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for + * the FLPR MCU. + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 DT_SIZE_K(80)>; + }; + + sram0_ns: image_ns@20014000 { + /* Non-Secure image memory */ + reg = <0x20014000 DT_SIZE_K(80)>; + }; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the + * last 96kB are reserved for the FLPR MCU. + * + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(512)>; + }; + + tfm_ps_partition: partition@80000 { + label = "tfm-ps"; + reg = <0x00080000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@84000 { + label = "tfm-its"; + reg = <0x00084000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@88000 { + label = "tfm-otp"; + reg = <0x00088000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@8A000 { + label = "image-0-nonsecure"; + reg = <0x0008A000 DT_SIZE_K(844)>; + }; + + storage_partition: partition@15D000 { + label = "storage"; + reg = <0x00015D000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 000000000000..83ef14a15a34 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l15/cpuapp/ns +name: BL54L15-DVK-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 000000000000..dea04c45f20c --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# Support for silence logging is not supported at the moment +# Tracked by: NCSDK-31930 +CONFIG_TFM_LOG_LEVEL_SILENCE=n + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts new file mode 100644 index 000000000000..0e00b2d1e5e4 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl54l15_dvk_common.dtsi" + +/ { + model = "Ezurio BL54L15 DVK nRF54L15 FLPR MCU"; + compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + /* size must be increased due to booting from SRAM */ + reg = <0x20028000 DT_SIZE_K(96)>; + ranges = <0x0 0x20028000 0x18000>; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml new file mode 100644 index 000000000000..a324778c0e4a --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l15/cpuflpr +name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig new file mode 100644 index 000000000000..9695bd3f5df1 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts new file mode 100644 index 000000000000..f1bbe27b447d --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bl54l15_dvk_nrf54l15_cpuflpr.dts" + +&cpuflpr_sram { + reg = <0x2002f000 DT_SIZE_K(68)>; + ranges = <0x0 0x2002f000 0x11000>; +}; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml new file mode 100644 index 000000000000..0c473591f9ce --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15_dvk/nrf54l15/cpuflpr/xip +name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 68 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..b433045216a7 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi new file mode 100644 index 000000000000..1377b613e2f0 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * Copyright (c) 2025 Ezurio LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ grtc_default: grtc_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ grtc_sleep: grtc_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/ezurio/bl54l15_dvk/board.cmake b/boards/ezurio/bl54l15_dvk/board.cmake new file mode 100644 index 000000000000..53b6961dee04 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/board.cmake @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L10_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +elseif(CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(jlink "--device=nRF54L15_RV32") +elseif(CONFIG_SOC_NRF54L10_CPUFLPR) + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l_10_15_cpuflpr.JLinkScript) + board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") +endif() + +if(CONFIG_BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS OR CONFIG_BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl54l15_dvk/board.yml b/boards/ezurio/bl54l15_dvk/board.yml new file mode 100644 index 000000000000..841dec0f4ae3 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/board.yml @@ -0,0 +1,52 @@ +board: + name: bl54l15_dvk + full_name: BL54L15 DVK + vendor: ezurio + socs: + - name: nrf54l10 + variants: + - name: ns + cpucluster: cpuapp + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp +runners: + run_once: + '--recover': + - runners: + - nrfjprog + - nrfutil + run: first + groups: + - boards: + - bl54l15_dvk/nrf54l15/cpuapp + - bl54l15_dvk/nrf54l15/cpuapp/ns + - bl54l15_dvk/nrf54l15/cpuflpr + - bl54l15_dvk/nrf54l15/cpuflpr/xip + '--erase': + - runners: + - nrfjprog + - jlink + - nrfutil + run: first + groups: + - boards: + - bl54l15_dvk/nrf54l15/cpuapp + - bl54l15_dvk/nrf54l15/cpuapp/ns + - bl54l15_dvk/nrf54l15/cpuflpr + - bl54l15_dvk/nrf54l15/cpuflpr/xip + '--reset': + - runners: + - nrfjprog + - jlink + - nrfutil + run: last + groups: + - boards: + - bl54l15_dvk/nrf54l15/cpuapp + - bl54l15_dvk/nrf54l15/cpuapp/ns + - bl54l15_dvk/nrf54l15/cpuflpr + - bl54l15_dvk/nrf54l15/cpuflpr/xip diff --git a/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst b/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst new file mode 100644 index 000000000000..f5f7c798b01e --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst @@ -0,0 +1,142 @@ +.. zephyr:board:: bl54l15_dvk + +Overview +******** + +.. note:: + You can find more information about the BL54L15 module on the `BL54L15 website`_. + + You can find more information about the BL54L10 module on the `BL54L10 website`_. + + You can find more information about the underlying nRF54L15 SoC on the + `nRF54L15 website`_. For the nRF54L15 technical documentation and other + resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page. + +The BL54L15 Development Kit provides support for the Ezurio BL54L15 and BL54L10 +range of modules. + +The modules are based on the Nordic Semiconductor nRF54L15 and nRF54L10 Arm Cortex-M33 CPUs. + +The BL54L15 module incorporates the QFN package nRF54L15 (1524kB Flash, 256kB RAM). The BL54L10 +module the QFN package nRF54L10 (1022kB Flash, 192kB RAM). Both parts feature up to 31 configurable +GPIOs and BLE Radio TX Power up to 7dBm. + +The modules include the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* MEMCONF +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +Hardware +******** + +The BL54L15 DVK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +Applications for the ``bl54l15_dvk/nrf54l15/cpuapp`` and ``bl54l15_dvk/nrf54l10/cpuapp`` +board targets can be built, flashed, and debugged in the usual way. +See :ref:`build_an_application` and :ref:`application_run` for more +details on building and running. + +Applications for the ``bl54l15_dvk/nrf54l15/cpuflpr`` board target need to be built +using sysbuild to include the ``vpr_launcher`` image for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core: + +.. code-block:: console + + west build -p -b bl54l15_dvk/nrf54l15/cpuflpr --sysbuild + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the BL54L15 DVK, complete the following steps: + +First, connect the BL54L15 DVK to your computer using the IMCU USB port on the DVK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl54l15_dvk/nrf54l15/cpuapp + :goals: build flash + +Testing the LEDs and buttons on the BL54L15 DVK +************************************************ + +Test the BL54L15 DVK with a :zephyr:code-sample:`blinky` sample. + +.. _BL54L15 website: https://www.ezurio.com/product/bl54l15-series-bluetooth-le-80215-4-nfc +.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc +.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15 +.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html + +.. _bl54l15_dvk_nrf54l10: + +BL54L10 emulation on BL54L15 DVK +******************************** + +Overview +======== + +The ``bl54l15_dvk/nrf54l10`` board is a modified version of the BL54L15 DVK +that enforces the limitations imposed by the nRF54L10 IC, upon which the BL54L10 is based. +The nRF54L10 is a cost-reduced variant of the original nRF54L15. Since Ezurio does not offer a +development kit for the BL54L10 you can use this board to develop for this +module while using the BL54L15 Development Kit (453-00001-K1, 453-00044-K1). + +See above for more information about the development board. Refer to +the `BL54L10 website`_ for details of the BL54L10 module and the `nRF54L10 website`_ for +the official reference on the underlying SoC. + +.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc +.. _nRF54L10 website: https://www.nordicsemi.com/Products/nRF54L10 diff --git a/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp b/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp new file mode 100644 index 000000000000..9bdc924af83c Binary files /dev/null and b/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp differ diff --git a/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi b/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi new file mode 100644 index 000000000000..8671beb29cf6 --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include "bl54l15_dvk_common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + status = "okay"; + reg = <0>; + spi-max-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript b/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript new file mode 100644 index 000000000000..1cf94ee52a4d --- /dev/null +++ b/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript @@ -0,0 +1,5 @@ +int InitTarget(void) { + // Base address where DMI registers can be found in the APB address space + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400"); + return 0; +} diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig b/boards/ezurio/bl54l15u_dvk/Kconfig new file mode 100644 index 000000000000..b1623fe1b824 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# BL54L15U DVK board configuration + +if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS + +DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk b/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk new file mode 100644 index 000000000000..f807b23268ea --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL54L15U_DVK + select SOC_NRF54L15_CPUAPP if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP || BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR || \ + BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR_XIP diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig new file mode 100644 index 000000000000..4ee4dc3e6d2d --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP + +if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi new file mode 100644 index 000000000000..72206859685e --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bl54l15u_dvk_nrf54l15-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +/* Get a node label for wi-fi spi to use in shield files */ +wifi_spi: &spi22 {}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi new file mode 100644 index 000000000000..1377b613e2f0 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * Copyright (c) 2025 Ezurio LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ grtc_default: grtc_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ grtc_sleep: grtc_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts new file mode 100644 index 000000000000..7ea5099aa3f5 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54l15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp"; + model = "Ezurio BL54L15u_DVK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(324)>; + }; + + slot0_ns_partition: partition@61000 { + label = "image-0-nonsecure"; + reg = <0x61000 DT_SIZE_K(324)>; + }; + + slot1_partition: partition@b2000 { + label = "image-1"; + reg = <0xb2000 DT_SIZE_K(324)>; + }; + + slot1_ns_partition: partition@103000 { + label = "image-1-nonsecure"; + reg = <0x103000 DT_SIZE_K(324)>; + }; + + /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ + storage_partition: partition@15c000 { + label = "storage"; + reg = <0x15c000 DT_SIZE_K(36)>; + }; + }; +}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml new file mode 100644 index 000000000000..264368c2baf1 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15u_dvk/nrf54l15/cpuapp +name: BL54L15u-DVK-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 188 +flash: 324 +supported: + - adc + - counter + - dmic + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig new file mode 100644 index 000000000000..c460d11847e9 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts new file mode 100644 index 000000000000..f03eb6a5e810 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include "nrf54l15_cpuapp_common.dtsi" + +/ { + compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp"; + model = "Ezurio BL54L15u DVK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &sram0_ns; + zephyr,entropy = &psa_rng; + }; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; +}; + +/ { + /* + * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support + * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). + * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). + * + * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for + * the FLPR MCU. + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 DT_SIZE_K(80)>; + }; + + sram0_ns: image_ns@20014000 { + /* Non-Secure image memory */ + reg = <0x20014000 DT_SIZE_K(80)>; + }; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the + * last 96kB are reserved for the FLPR MCU. + * + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(512)>; + }; + + tfm_ps_partition: partition@80000 { + label = "tfm-ps"; + reg = <0x00080000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@84000 { + label = "tfm-its"; + reg = <0x00084000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@88000 { + label = "tfm-otp"; + reg = <0x00088000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@8A000 { + label = "image-0-nonsecure"; + reg = <0x0008A000 DT_SIZE_K(844)>; + }; + + storage_partition: partition@15D000 { + label = "storage"; + reg = <0x00015D000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 000000000000..11a3347969dd --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: bl54l15u_dvk/nrf54l15/cpuapp/ns +name: BL54L15u-DVK-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 000000000000..24848d53b821 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# Support for silence logging is not supported at the moment +# Tracked by: NCSDK-31930 +CONFIG_TFM_LOG_LEVEL_SILENCE=n + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts new file mode 100644 index 000000000000..12e280a9a90e --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl54l15u_dvk_common.dtsi" + +/ { + model = "Ezurio BL54L15u DVK nRF54L15 FLPR MCU"; + compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + /* size must be increased due to booting from SRAM */ + reg = <0x20028000 DT_SIZE_K(96)>; + ranges = <0x0 0x20028000 0x18000>; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml new file mode 100644 index 000000000000..bf3c14b52bf1 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15u_dvk/nrf54l15/cpuflpr +name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig new file mode 100644 index 000000000000..9695bd3f5df1 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts new file mode 100644 index 000000000000..2380f2cdf258 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bl54l15u_dvk_nrf54l15_cpuflpr.dts" + +&cpuflpr_sram { + reg = <0x2002f000 DT_SIZE_K(68)>; + ranges = <0x0 0x2002f000 0x11000>; +}; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml new file mode 100644 index 000000000000..27d584351dee --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: bl54l15u_dvk/nrf54l15/cpuflpr/xip +name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 68 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..b433045216a7 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y diff --git a/boards/ezurio/bl54l15u_dvk/board.cmake b/boards/ezurio/bl54l15u_dvk/board.cmake new file mode 100644 index 000000000000..f8e306c4bcc5 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/board.cmake @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +elseif(CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(jlink "--device=nRF54L15_RV32") +endif() + +if(CONFIG_BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl54l15u_dvk/board.yml b/boards/ezurio/bl54l15u_dvk/board.yml new file mode 100644 index 000000000000..1553980eaa8f --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/board.yml @@ -0,0 +1,48 @@ +board: + name: bl54l15u_dvk + full_name: BL54L15u DVK + vendor: ezurio + socs: + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp +runners: + run_once: + '--recover': + - runners: + - nrfjprog + - nrfutil + run: first + groups: + - boards: + - bl54l15u_dvk/nrf54l15/cpuapp + - bl54l15u_dvk/nrf54l15/cpuapp/ns + - bl54l15u_dvk/nrf54l15/cpuflpr + - bl54l15u_dvk/nrf54l15/cpuflpr/xip + '--erase': + - runners: + - nrfjprog + - jlink + - nrfutil + run: first + groups: + - boards: + - bl54l15u_dvk/nrf54l15/cpuapp + - bl54l15u_dvk/nrf54l15/cpuapp/ns + - bl54l15u_dvk/nrf54l15/cpuflpr + - bl54l15u_dvk/nrf54l15/cpuflpr/xip + '--reset': + - runners: + - nrfjprog + - jlink + - nrfutil + run: last + groups: + - boards: + - bl54l15u_dvk/nrf54l15/cpuapp + - bl54l15u_dvk/nrf54l15/cpuapp/ns + - bl54l15u_dvk/nrf54l15/cpuflpr + - bl54l15u_dvk/nrf54l15/cpuflpr/xip diff --git a/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst b/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst new file mode 100644 index 000000000000..3e3e705be8d7 --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst @@ -0,0 +1,115 @@ +.. zephyr:board:: bl54l15u_dvk + +Overview +******** + +.. note:: + You can find more information about the BL54L15u module on the `BL54L15u website`_. + + You can find more information about the underlying nRF54L15 SoC on the + `nRF54L15 website`_. For the nRF54L15 technical documentation and other + resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page. + +The BL54L15u Development Kit provides support for the Ezurio BL54L15u module. + +The module is based on the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU. + +The BL54L15u module incorporates the WLCSP package nRF54L15 (1524kB Flash, 256kB RAM). +The part features up to 32 configurable GPIOs and BLE Radio TX Power up to 8dBm. + +The module includes the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* MEMCONF +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +Hardware +******** + +The BL54L15u DVK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +Applications for the ``bl54l15u_dvk/nrf54l15/cpuapp`` board target can be built, +flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Applications for the ``bl54l15u_dvk/nrf54l15/cpuflpr`` board target need to be +built using sysbuild to include the ``vpr_launcher`` image for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core: + +.. code-block:: console + + west build -p -b bl54l15u_dvk/nrf54l15/cpuflpr --sysbuild + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the BL54L15u DVK, complete the following steps: + +First, connect the BL54L15u DVK to your computer using the IMCU USB port on the DVK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl54l15u_dvk/nrf54l15/cpuapp + :goals: build flash + +Testing the LEDs and buttons on the BL54L15u DVK +************************************************ + +Test the BL54L15u DVK with a :zephyr:code-sample:`blinky` sample. + +.. _BL54L15u website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l15-micro-series-bluetooth-le-802-15-4-nfc +.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15 +.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html diff --git a/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp b/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp new file mode 100644 index 000000000000..bef2a629baf0 Binary files /dev/null and b/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp differ diff --git a/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi b/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi new file mode 100644 index 000000000000..e630abab4a9c --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include "bl54l15u_dvk_common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + status = "okay"; + reg = <0>; + spi-max-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript b/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript new file mode 100644 index 000000000000..1cf94ee52a4d --- /dev/null +++ b/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript @@ -0,0 +1,5 @@ +int InitTarget(void) { + // Base address where DMI registers can be found in the APB address space + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400"); + return 0; +} diff --git a/boards/ezurio/bl652_dvk/board.cmake b/boards/ezurio/bl652_dvk/board.cmake index 9449b78cd471..29682197edc8 100644 --- a/boards/ezurio/bl652_dvk/board.cmake +++ b/boards/ezurio/bl652_dvk/board.cmake @@ -2,5 +2,6 @@ board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst index 27ec3f929288..cdceadb2a34b 100644 --- a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst @@ -43,42 +43,8 @@ Hardware Supported Features ================== -The BL652 DVK board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `BL652 Module Website`_. Connections and IOs @@ -196,6 +162,8 @@ J32/J22 Digital I/O Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/ezurio/bl653_dvk/board.cmake b/boards/ezurio/bl653_dvk/board.cmake index 12b0d2996be7..a19979a7e27b 100644 --- a/boards/ezurio/bl653_dvk/board.cmake +++ b/boards/ezurio/bl653_dvk/board.cmake @@ -3,6 +3,7 @@ board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52833_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52833" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst index e4de59757e85..811ce96a5178 100644 --- a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst @@ -33,45 +33,8 @@ Hardware Supported Features ================== -The BL653 DVK board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `BL653 website`_ for a complete list of BL653 Development Kit board hardware features. @@ -98,6 +61,8 @@ Push buttons Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bl653_dvk`` board configuration can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. diff --git a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts index d826a466bfd3..ee5d7260fa4e 100644 --- a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts +++ b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts @@ -9,7 +9,8 @@ / { /* Information from Nordic SDK-Based Application Development and SKY66112 datasheet */ - sky66112_fem: fem { + nrf_radio_fem: fem { + status = "okay"; compatible = "generic-fem-two-ctrl-pins"; ctx-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; crx-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; @@ -21,5 +22,5 @@ }; &radio { - fem = <&sky66112_fem>; + fem = <&nrf_radio_fem>; }; diff --git a/boards/ezurio/bl654_dvk/board.cmake b/boards/ezurio/bl654_dvk/board.cmake index a99f3ce86932..32b02a35258b 100644 --- a/boards/ezurio/bl654_dvk/board.cmake +++ b/boards/ezurio/bl654_dvk/board.cmake @@ -2,5 +2,6 @@ board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst index 5a59932df25a..30e238665871 100644 --- a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst @@ -44,45 +44,8 @@ Hardware Supported Features ================== -The BL654 DVK board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `BL654 website`_ for a complete list of BL654 Development Kit board hardware features. @@ -109,6 +72,8 @@ Push buttons Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bl654_dvk`` board configuration can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. diff --git a/boards/ezurio/bl654_sensor_board/board.cmake b/boards/ezurio/bl654_sensor_board/board.cmake index c1ca3bd12cf6..170466978324 100644 --- a/boards/ezurio/bl654_sensor_board/board.cmake +++ b/boards/ezurio/bl654_sensor_board/board.cmake @@ -4,5 +4,6 @@ board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst index 373e9bf1bdcb..605b5eb8c7fb 100644 --- a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -40,43 +40,7 @@ Hardware Supported Features ================== -The BL654 Sensor Board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `BL654 website`_ for a complete list of BL654 module hardware features. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -119,6 +83,8 @@ be blobbed. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bl654_sensor_board`` board configuration can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. An external diff --git a/boards/ezurio/bl654_usb/doc/bl654_usb.rst b/boards/ezurio/bl654_usb/doc/bl654_usb.rst index 33bf2a554dda..04ac5759753f 100644 --- a/boards/ezurio/bl654_usb/doc/bl654_usb.rst +++ b/boards/ezurio/bl654_usb/doc/bl654_usb.rst @@ -36,35 +36,8 @@ Hardware Supported Features ================== -The BL654 USB board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `BL654 website`_ for a complete list of BL654 USB adapter hardware features. @@ -92,6 +65,8 @@ Zephyr console output is available as follows: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The ``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK diff --git a/boards/ezurio/bt510/board.cmake b/boards/ezurio/bt510/board.cmake index c1ca3bd12cf6..170466978324 100644 --- a/boards/ezurio/bt510/board.cmake +++ b/boards/ezurio/bt510/board.cmake @@ -4,5 +4,6 @@ board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/bt510/doc/bt510.rst b/boards/ezurio/bt510/doc/bt510.rst index fdfd9312ffeb..74b4c48703cf 100644 --- a/boards/ezurio/bt510/doc/bt510.rst +++ b/boards/ezurio/bt510/doc/bt510.rst @@ -36,39 +36,7 @@ Hardware Supported Features ================== -The BT510 Sensor supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -116,6 +84,8 @@ The BT510 incorporates an I2C Silabs SI7055 temperature sensor. Refer to the `Si Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bt510`` board configuration can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. diff --git a/boards/ezurio/bt610/board.cmake b/boards/ezurio/bt610/board.cmake index 0a2feda9ee2e..4d421a07db61 100644 --- a/boards/ezurio/bt610/board.cmake +++ b/boards/ezurio/bt610/board.cmake @@ -3,6 +3,7 @@ board_runner_args(nrfjprog "--nrf-family=NRF52") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ezurio/bt610/doc/bt610.rst b/boards/ezurio/bt610/doc/bt610.rst index 0ae62035a48b..afa138eac63d 100644 --- a/boards/ezurio/bt610/doc/bt610.rst +++ b/boards/ezurio/bt610/doc/bt610.rst @@ -40,43 +40,7 @@ Hardware Supported Features ================== -The BT610 Sensor supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: .. figure:: img/bt610_board.jpg :align: center @@ -473,6 +437,8 @@ Required pins are as follows. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``bt610`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details); however, the standard diff --git a/boards/ezurio/mg100/board.cmake b/boards/ezurio/mg100/board.cmake index 790ab533b4a4..4a350c831677 100644 --- a/boards/ezurio/mg100/board.cmake +++ b/boards/ezurio/mg100/board.cmake @@ -3,6 +3,7 @@ board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ezurio/mg100/doc/index.rst b/boards/ezurio/mg100/doc/index.rst index 5f66c65e1478..b2baed38724a 100644 --- a/boards/ezurio/mg100/doc/index.rst +++ b/boards/ezurio/mg100/doc/index.rst @@ -49,47 +49,7 @@ Hardware Supported Features ================== -The MG100 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| LIS3DH | I2C(M) | sensor/lis3dh | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ -| SDMMC | SPI(M) | SD Card via SPI | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: See `MG100 website`_ for a complete list of MG100 hardware features. @@ -149,6 +109,8 @@ SPI MISO = P0.12 Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``mg100`` board configuration can be built and flashed in the usual way. (see :ref:`build_an_application` and :ref:`application_run` for more details) diff --git a/boards/ezurio/pinnacle_100_dvk/board.cmake b/boards/ezurio/pinnacle_100_dvk/board.cmake index d5f3c19d7844..829cac0ce82a 100644 --- a/boards/ezurio/pinnacle_100_dvk/board.cmake +++ b/boards/ezurio/pinnacle_100_dvk/board.cmake @@ -3,6 +3,7 @@ board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ezurio/pinnacle_100_dvk/doc/index.rst b/boards/ezurio/pinnacle_100_dvk/doc/index.rst index 71511d8dfc81..d9f8b260efd2 100644 --- a/boards/ezurio/pinnacle_100_dvk/doc/index.rst +++ b/boards/ezurio/pinnacle_100_dvk/doc/index.rst @@ -52,49 +52,7 @@ Hardware Supported Features ================== -The Pinnacle 100 development board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| BME680 | I2C(M) | sensor/bme680 | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: See `Pinnacle 100 website`_ for a complete list of Pinnacle 100 Development Kit hardware features. @@ -122,6 +80,8 @@ Push buttons Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``pinnacle_100_dvk`` board configuration can be built and flashed in the usual way. (see :ref:`build_an_application` and :ref:`application_run` for more details) diff --git a/boards/ezurio/rm1xx_dvk/board.cmake b/boards/ezurio/rm1xx_dvk/board.cmake index 677dc6bdf2b1..1f0cea559d11 100644 --- a/boards/ezurio/rm1xx_dvk/board.cmake +++ b/boards/ezurio/rm1xx_dvk/board.cmake @@ -2,5 +2,6 @@ board_runner_args(nrfjprog "--nrf-family=NRF51") board_runner_args(jlink "--device=nRF51822_xxAC" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ezurio/rm1xx_dvk/doc/index.rst b/boards/ezurio/rm1xx_dvk/doc/index.rst index 8462f92c1b25..ebb994540eba 100644 --- a/boards/ezurio/rm1xx_dvk/doc/index.rst +++ b/boards/ezurio/rm1xx_dvk/doc/index.rst @@ -48,40 +48,8 @@ is 16MHz. Supported Features ================== -The rm1xx_dvk board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: + See `Nordic Semiconductor Infocenter`_ for a complete list of hardware features. @@ -125,6 +93,8 @@ Refer to the `Semtech SX1272 datasheet`_ for further details. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6 b/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6 new file mode 100644 index 000000000000..b429435dd096 --- /dev/null +++ b/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 zack jiang, Honbo He +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FK743M5_XIH6 + select SOC_STM32H743XX diff --git a/boards/fanke/fk743m5_xih6/board.cmake b/boards/fanke/fk743m5_xih6/board.cmake new file mode 100644 index 000000000000..10170d65424f --- /dev/null +++ b/boards/fanke/fk743m5_xih6/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H743XI" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/fanke/fk743m5_xih6/board.yml b/boards/fanke/fk743m5_xih6/board.yml new file mode 100644 index 000000000000..b6a9f42f25d7 --- /dev/null +++ b/boards/fanke/fk743m5_xih6/board.yml @@ -0,0 +1,6 @@ +board: + name: fk743m5_xih6 + full_name: FK743M5-XIH6 + vendor: fanke + socs: + - name: stm32h743xx diff --git a/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp b/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp new file mode 100644 index 000000000000..733b0efc806b Binary files /dev/null and b/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp differ diff --git a/boards/fanke/fk743m5_xih6/doc/index.rst b/boards/fanke/fk743m5_xih6/doc/index.rst new file mode 100644 index 000000000000..0c7dbbfbe44e --- /dev/null +++ b/boards/fanke/fk743m5_xih6/doc/index.rst @@ -0,0 +1,131 @@ +.. zephyr:board:: fk743m5_xih6 + +Overview +******** + +The FK743M5-XIH6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller +platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H743XIH6 microcontroller. +This board is an ideal solution for developers looking to create high-performance +applications, leveraging its robust capabilities and support for sophisticated display +and image processing technologies. + +The FK743M5-XIH6 is designed as a reference design for user application development before +transitioning to the final product, significantly simplifying the development process. +Its wide range of hardware features, including advanced display and image processing capabilities, +allowing for comprehensive evaluation and testing of peripherals and functionalities. + +Hardware +******** + +FK743M5-XIH6 provides the following hardware components: + +- STM32H743XI in 265-TFBGA package +- ARM 32-bit Cortex-M7 CPU with FPU +- 480 MHz max CPU frequency +- 2048 KB Flash +- 1 MB SRAM: 192 Kbytes TCM RAM (64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM), 864 Kbytes user SRAM, and 4 Kbytes SRAM in Backup domain +- Main clock: External 25MHz crystal oscillator. +- RTC: 32.768kHz crystal oscillator. +- high-resolution timers(2.1 ns max resolution, 1) +- 32-bit timers(2) +- 16-bit timers(17) +- 1 reset button, and 1 BOOT button +- 1 user LED +- External 64-Mbit QSPI (W25Q64) NOR Flash memory. +- USB OTG Full Speed and High Speed(1) +- 1 micro SD card +- 1 DCMI camera interface +- 1 SPI LCD interface +- SWD and serial port accessibility through a pin header +- Bring out 83 IO ports + +More information about STM32H743XI can be found here: + +- `STM32H743XI on www.st.com`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Pin Mapping +=========== + +FK743M5-XIH6 board has 5 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Default Zephyr Peripheral Mapping +--------------------------------- + +The FK743M5-XIH6 board is configured as follows + +- UART_1 TX/RX : PA9/PA10 (available on the header pins) +- User LED (blue) : PC13 +- SPI5 NCS/CLK/MOSI : PE11/PE12/PE14 (SPI LCD) +- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PG6/PF10/PF8/PF9/PF7/PF6 (NOR Flash) +- USB DM/DP : PA11/PA12 + +System Clock +============ + +The FK743M5-XIH6 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 480MHz, +driven by an 25MHz external crystal oscillator. + +Serial Port +=========== + +The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``fk743m5_xih6`` board target can be built and flashed in the usual +way (see :ref:`build_an_application` and :ref:`application_run` for more details). + +Flashing +======== + +The FK743M5-XIH6 board does not include an on-board debugger. As a result, it requires +an external debugger, such as ST-Link, for programming and debugging purposes. + +The board provides header pins for the Serial Wire Debug (SWD) interface. + +Flashing an application to FK743M5-XIH6 +--------------------------------------- + +To begin, connect the ST-Link Debug Programmer to the FK743M5-XIH6 board using the SWD +interface. Next, connect the ST-Link to your host computer via a USB port. +Once this setup is complete, you can proceed to build and flash your application to the board + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: fk743m5_xih6 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, press the RESET button, you should see the following message: + +.. code-block:: console + + Hello World! fk743m5_xih6 + +Debugging +========= + +This current Zephyr port does not support debugging. + +References +********** + +.. target-notes:: +.. _STM32H743XI on www.st.com: https://www.st.com/en/microcontrollers/stm32h743xi.html diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts new file mode 100644 index 000000000000..93f9cd88847e --- /dev/null +++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2025 zack jiang, Honbo He + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "FANKE FK743M5-XIH6 board"; + compatible = "fanke,fk743m5-xih6"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + user_led: led_0 { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + label = "User LED"; + }; + }; + + aliases { + led0 = &user_led; + }; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll3 { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <20>; + div-r = <99>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&quadspi { + pinctrl-0 = <&quadspi_bk1_io0_pf8 &quadspi_bk1_io1_pf9 + &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6 + &quadspi_clk_pf10 &quadspi_bk1_ncs_pg6>; + pinctrl-names = "default"; + status = "okay"; + + /* Winbond external flash */ + w25q64_qspi: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */ + qspi-max-frequency = <40000000>; + status = "okay"; + spi-bus-width = <4>; + writeoc = "PP_1_1_4"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(8)>; + }; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&backup_sram { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml new file mode 100644 index 000000000000..932fcb5f3f44 --- /dev/null +++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml @@ -0,0 +1,16 @@ +identifier: fk743m5_xih6 +name: FANKE FK743M5-XIH6 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 1024 +flash: 2048 +supported: + - uart + - gpio + - spi + - backup_sram + - qspi +vendor: fanke diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig b/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig new file mode 100644 index 000000000000..13a1289e51c4 --- /dev/null +++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) zack jiang, Honbo He +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/fanke/fk743m5_xih6/support/openocd.cfg b/boards/fanke/fk743m5_xih6/support/openocd.cfg new file mode 100644 index 000000000000..4ea6d13db0ba --- /dev/null +++ b/boards/fanke/fk743m5_xih6/support/openocd.cfg @@ -0,0 +1,25 @@ +# Copyright (c) zack jiang, Honbo He +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/stlink-dap.cfg] +transport select "dapdirect_swd" + +set WORKAREASIZE 0x8000 + +set CHIPNAME STM32H743XI +set BOARDNAME FK743M5-XIH6 + +source [find target/stm32h7x.cfg] + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 diff --git a/boards/fanke/fk750m1_vbt6/doc/index.rst b/boards/fanke/fk750m1_vbt6/doc/index.rst index 6a558bddc087..f5340f336b6b 100644 --- a/boards/fanke/fk750m1_vbt6/doc/index.rst +++ b/boards/fanke/fk750m1_vbt6/doc/index.rst @@ -46,35 +46,7 @@ More information about STM32H750VB can be found here: Supported Features ================== -The Zephyr ``fk750m1_vbt6`` board target supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi bus | -+-------------+------------+-------------------------------------+ -| QUADSPI | on-chip | quadspi | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in -:zephyr_file:`boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig` +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -108,6 +80,8 @@ The Zephyr console output is assigned to UART1. The default communication settin Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``fk750m1_vbt6`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/firefly/roc_rk3568_pc/doc/index.rst b/boards/firefly/roc_rk3568_pc/doc/index.rst index bd55e747c519..e26092db5766 100644 --- a/boards/firefly/roc_rk3568_pc/doc/index.rst +++ b/boards/firefly/roc_rk3568_pc/doc/index.rst @@ -42,18 +42,7 @@ has frequency up to 2.0GHz. Zephyr OS is ported to run on it. Supported Features ================== -The Zephyr roc_rk3568_pc board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Devices ======== @@ -72,6 +61,8 @@ CPU's UART2. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Use U-Boot to load the zephyr.bin to the memory and kick it: .. code-block:: console diff --git a/boards/franzininho/esp32s2_franzininho/board.yml b/boards/franzininho/esp32s2_franzininho/board.yml index 530d5dcec4e5..25b481d709d0 100644 --- a/boards/franzininho/esp32s2_franzininho/board.yml +++ b/boards/franzininho/esp32s2_franzininho/board.yml @@ -1,6 +1,6 @@ board: name: esp32s2_franzininho full_name: ESP32-S2 Franzininho - vendor: espressif + vendor: franzininho socs: - name: esp32s2 diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst index 47f223b83ca2..bdbc20574ecd 100644 --- a/boards/franzininho/esp32s2_franzininho/doc/index.rst +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -47,6 +47,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index 2b182b569cbe..f5e6429233ac 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -111,3 +111,7 @@ &wdt0 { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml index da3da1bdc3ac..4fc82a2f23d7 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml @@ -14,4 +14,5 @@ supported: testing: ignore_tags: - heap + - bluetooth vendor: franzininho diff --git a/boards/fysetc/ucan/doc/index.rst b/boards/fysetc/ucan/doc/index.rst index f9b4b53809f8..725d87e62a4d 100644 --- a/boards/fysetc/ucan/doc/index.rst +++ b/boards/fysetc/ucan/doc/index.rst @@ -16,28 +16,7 @@ drawings are available in the `UCAN GitHub repository`_. Supported Features ================== -The ``ucan`` board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB | -+-----------+------------+-------------------------------------+ -| CAN1 | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/fysetc/ucan/ucan_defconfig`. - -Other hardware features are not currently supported by the port. +.. zephyr:board-supported-hw:: System Clock ============ @@ -48,6 +27,8 @@ configured to provide a system clock of 48 MHz. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/gaisler/generic_leon3/doc/index.rst b/boards/gaisler/generic_leon3/doc/index.rst index 9f7781f3e211..0dde96f2fc76 100644 --- a/boards/gaisler/generic_leon3/doc/index.rst +++ b/boards/gaisler/generic_leon3/doc/index.rst @@ -17,6 +17,8 @@ M2GL-EVAL-KIT. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Building ======== diff --git a/boards/gaisler/gr716a_mini/doc/index.rst b/boards/gaisler/gr716a_mini/doc/index.rst index 0f7233061055..77cf72311921 100644 --- a/boards/gaisler/gr716a_mini/doc/index.rst +++ b/boards/gaisler/gr716a_mini/doc/index.rst @@ -26,6 +26,8 @@ if enabled in GRMON, is preserved. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Building ======== diff --git a/boards/gardena/sgrm/doc/index.rst b/boards/gardena/sgrm/doc/index.rst index 40d05a9f4f34..5b0da0a61c73 100644 --- a/boards/gardena/sgrm/doc/index.rst +++ b/boards/gardena/sgrm/doc/index.rst @@ -24,24 +24,7 @@ Hardware Supported Features ================== -The ``sgrm`` board target supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -77,6 +60,8 @@ Connections and IOs Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/gardena/sgrm/sgrm.dts b/boards/gardena/sgrm/sgrm.dts index 58a9e90e97e6..c261592c6b9e 100644 --- a/boards/gardena/sgrm/sgrm.dts +++ b/boards/gardena/sgrm/sgrm.dts @@ -15,9 +15,9 @@ chosen { zephyr,console = &usart1; zephyr,flash = &flash0; + zephyr,ppp-uart = &usart0; zephyr,shell-uart = &usart1; zephyr,sram = &sram0; - zephyr,ppp-uart = &usart0; }; }; @@ -41,9 +41,9 @@ &usart0 { current-speed = <500000>; + hw-flow-control; pinctrl-0 = <&usart0_default>; pinctrl-names = "default"; - hw-flow-control; status = "okay"; }; @@ -80,13 +80,13 @@ #size-cells = <1>; slot0_partition: partition@0 { - label = "image-0"; reg = <0x00000000 DT_SIZE_K(192)>; + label = "image-0"; }; storage_partition: partition@30000 { - label = "storage"; reg = <0x00030000 DT_SIZE_K(64)>; + label = "storage"; }; }; }; diff --git a/boards/gd/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst index 8fcec05bdc34..27e715227a70 100644 --- a/boards/gd/gd32a503v_eval/doc/index.rst +++ b/boards/gd/gd32a503v_eval/doc/index.rst @@ -39,47 +39,7 @@ For more information about the GD32A503 SoC and GD32A503V-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v8m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - PINMUX - - :kconfig:option:`CONFIG_PINCTRL` - - :dtcompatible:`gd,gd32-pinctrl-af` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`gd,gd32-adc` - * - DAC - - :kconfig:option:`CONFIG_DAC` - - :dtcompatible:`gd,gd32-dac` - * - FMC - - N/A - - :dtcompatible:`gd,gd32-flash-controller` - * - SPI - - :kconfig:option:`CONFIG_SPI` - - :dtcompatible:`gd,gd32-spi` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -90,6 +50,8 @@ is UART0 at PIN-72 and PIN-73. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before program your board make sure to configure boot setting and serial port. The default serial port is USART0. diff --git a/boards/gd/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst index 382bed8c7de0..49d6f799199d 100644 --- a/boards/gd/gd32e103v_eval/doc/index.rst +++ b/boards/gd/gd32e103v_eval/doc/index.rst @@ -43,24 +43,7 @@ For more information about the GD32E103 SoC and GD32E103V-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - +.. zephyr:board-supported-hw:: Serial Port =========== @@ -71,6 +54,8 @@ is UART0 at PIN-9 and PIN-10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before program your board make sure to configure boot setting and serial port. The default serial port is USART0. This port uses header JP-5/6 to route signals between USB VBUS/ID and USART J2. diff --git a/boards/gd/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst index a8b8f7a94696..68eaf60ef49d 100644 --- a/boards/gd/gd32e507v_start/doc/index.rst +++ b/boards/gd/gd32e507v_start/doc/index.rst @@ -30,34 +30,7 @@ For more information about the GD32E507 SoC and GD32E507V-START board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v8m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - -Other peripherals may be used if shields are connected to the board. +.. zephyr:board-supported-hw:: Serial Port =========== @@ -69,6 +42,8 @@ virtual COM port via the CN3 USB connector. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot jumpers as follows: diff --git a/boards/gd/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst index 610562b3eae2..f43863fbadb3 100644 --- a/boards/gd/gd32e507z_eval/doc/index.rst +++ b/boards/gd/gd32e507z_eval/doc/index.rst @@ -40,32 +40,7 @@ For more information about the GD32E507 SoC and GD32E507Z-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v8m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -77,6 +52,8 @@ virtual COM port via the J1 USB connector. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot jumpers as follows: diff --git a/boards/gd/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst index 2c7ad7263527..e30ab453690e 100644 --- a/boards/gd/gd32f350r_eval/doc/index.rst +++ b/boards/gd/gd32f350r_eval/doc/index.rst @@ -35,29 +35,7 @@ For more information about the GD32F350 SoC and GD32F350R-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - PINMUX - - :kconfig:option:`CONFIG_PINCTRL` - - :dtcompatible:`gd,gd32-pinctrl-af` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`gd,gd32-adc` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -68,6 +46,8 @@ is USART0 with TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: - J4: Select 2-3 for both (labeled as ``L``) diff --git a/boards/gd/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst index d304094a3e76..7d2ca320ca7b 100644 --- a/boards/gd/gd32f403z_eval/doc/index.rst +++ b/boards/gd/gd32f403z_eval/doc/index.rst @@ -43,27 +43,7 @@ For more information about the GD32F403 SoC and GD32F403Z-Eval board: Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| EXTI | on-chip | EXTI interrupt | -| | | controller | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling | -+-----------+------------+-----------------------+ -| ADC | on-chip | ADC | -+-----------+------------+-----------------------+ +.. zephyr:board-supported-hw:: Serial Port =========== @@ -74,6 +54,8 @@ is UART0 at PIN-9 and PIN-10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before program your board make sure to configure boot setting and serial port. The default serial port is USART0. This port uses header JP-5/6 to route signals between USB VBUS/ID and USART J2. diff --git a/boards/gd/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst index 68332eb51b8d..615659bf8209 100644 --- a/boards/gd/gd32f407v_start/doc/index.rst +++ b/boards/gd/gd32f407v_start/doc/index.rst @@ -30,34 +30,7 @@ For more information about the GD32F407 SoC and GD32F407V-START board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - -Other peripherals may be used if shields are connected to the board. +.. zephyr:board-supported-hw:: Serial Port =========== @@ -68,6 +41,8 @@ is USART0 with TX connected at PB6 and RX at PB7. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot jumpers as follows: diff --git a/boards/gd/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst index d342cc9774d0..05b2c20ba7a6 100644 --- a/boards/gd/gd32f450i_eval/doc/index.rst +++ b/boards/gd/gd32f450i_eval/doc/index.rst @@ -43,44 +43,7 @@ For more information about the GD32F450 SoC and GD32F450I-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - DAC - - :kconfig:option:`CONFIG_DAC` - - :dtcompatible:`gd,gd32-dac` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`gd,gd32-i2c` - * - EEPROM - - :kconfig:option:`CONFIG_EEPROM` - - :dtcompatible:`atmel,at24` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`gd,gd32-adc` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -91,6 +54,8 @@ is USART0 with TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: diff --git a/boards/gd/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst index 36870e0c6674..6105b6afc16b 100644 --- a/boards/gd/gd32f450v_start/doc/index.rst +++ b/boards/gd/gd32f450v_start/doc/index.rst @@ -30,34 +30,7 @@ For more information about the GD32F450 SoC and GD32F450V-START board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v8m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - -Other peripherals may be used if shields are connected to the board. +.. zephyr:board-supported-hw:: Serial Port =========== @@ -70,6 +43,8 @@ UART-USB adapter. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot jumpers as follows: diff --git a/boards/gd/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst index 5a8d8b74763e..7b012d1ddb2c 100644 --- a/boards/gd/gd32f450z_eval/doc/index.rst +++ b/boards/gd/gd32f450z_eval/doc/index.rst @@ -41,41 +41,7 @@ For more information about the GD32F450 SoC and GD32F450Z-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - DAC - - :kconfig:option:`CONFIG_DAC` - - :dtcompatible:`gd,gd32-dac` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`gd,gd32-i2c` - * - EEPROM - - :kconfig:option:`CONFIG_EEPROM` - - :dtcompatible:`atmel,at24` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -86,6 +52,8 @@ is USART0 with TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: diff --git a/boards/gd/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst index 1a8865f4d06f..4c90c4d3f124 100644 --- a/boards/gd/gd32f470i_eval/doc/index.rst +++ b/boards/gd/gd32f470i_eval/doc/index.rst @@ -42,44 +42,7 @@ For more information about the GD32F470 SoC and GD32F470I-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - DAC - - :kconfig:option:`CONFIG_DAC` - - :dtcompatible:`gd,gd32-dac` - * - I2C - - :kconfig:option:`CONFIG_I2C` - - :dtcompatible:`gd,gd32-i2c` - * - EEPROM - - :kconfig:option:`CONFIG_EEPROM` - - :dtcompatible:`atmel,at24` - * - SPI - - :kconfig:option:`CONFIG_SPI` - - :dtcompatible:`gd,gd32-spi` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -90,6 +53,8 @@ is USART0 with TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: diff --git a/boards/gd/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst index d67708562560..d025a2bf96e9 100644 --- a/boards/gd/gd32l233r_eval/doc/index.rst +++ b/boards/gd/gd32l233r_eval/doc/index.rst @@ -34,35 +34,7 @@ For more information about the GD32L233 SoC and GD32L233R-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - EXTI - - :kconfig:option:`CONFIG_GD32_EXTI` - - :dtcompatible:`gd,gd32-exti` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - NVIC - - N/A - - :dtcompatible:`arm,v8m-nvic` - * - SYSTICK - - N/A - - N/A - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - PINMUX - - :kconfig:option:`CONFIG_PINCTRL` - - :dtcompatible:`gd,gd32-pinctrl-af` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`gd,gd32-adc` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -74,6 +46,8 @@ CH04E serial connector with Mini-USB. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Using J-Link ============= diff --git a/boards/gd/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst index 40b22fa18c5a..a443dbde5f3c 100644 --- a/boards/gd/gd32vf103c_starter/doc/index.rst +++ b/boards/gd/gd32vf103c_starter/doc/index.rst @@ -30,29 +30,7 @@ For more information about the GD32VF103 SoC and GD32VF103C-STARTER board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - Machine timer - - :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER` - - :dtcompatible:`riscv,machine-timer` - * - Nuclei ECLIC Interrupt Controller - - :kconfig:option:`CONFIG_NUCLEI_ECLIC` - - :dtcompatible:`nuclei,eclic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -63,6 +41,8 @@ TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: diff --git a/boards/gd/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst index 773262c8eabe..2f8dd496f615 100644 --- a/boards/gd/gd32vf103v_eval/doc/index.rst +++ b/boards/gd/gd32vf103v_eval/doc/index.rst @@ -37,32 +37,7 @@ For more information about the GD32VF103 SoC and GD32VF103V-EVAL board: Supported Features ================== -The board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`gd,gd32-gpio` - * - Machine timer - - :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER` - - :dtcompatible:`riscv,machine-timer` - * - Nuclei ECLIC Interrupt Controller - - :kconfig:option:`CONFIG_NUCLEI_ECLIC` - - :dtcompatible:`nuclei,eclic` - * - PWM - - :kconfig:option:`CONFIG_PWM` - - :dtcompatible:`gd,gd32-pwm` - * - USART - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`gd,gd32-usart` - * - ADC - - :kconfig:option:`CONFIG_ADC` - - :dtcompatible:`gd,gd32-adc` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -73,6 +48,8 @@ is USART0 with TX connected at PA9 and RX at PA10. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Before programming your board make sure to configure boot and serial jumpers as follows: diff --git a/boards/google/dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst index 3f717a84341f..ed5c8c111359 100644 --- a/boards/google/dragonclaw/doc/index.rst +++ b/boards/google/dragonclaw/doc/index.rst @@ -26,6 +26,8 @@ Peripherial Mapping Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Build application as usual for the ``dragonclaw`` board, and flash using μServo or an external J-Link connected to J4. If μServo is used, please follow the `Chromium EC Flashing Documentation`_. diff --git a/boards/google/icetower/doc/index.rst b/boards/google/icetower/doc/index.rst index 45ecb81be2dc..7106102f718f 100644 --- a/boards/google/icetower/doc/index.rst +++ b/boards/google/icetower/doc/index.rst @@ -26,6 +26,8 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Build application as usual for the ``google_icetower`` board, and flash using μServo or an external J-Link connected to J4. If μServo is used, please follow the `Chromium EC Flashing Documentation`_. diff --git a/boards/google/quincy/doc/index.rst b/boards/google/quincy/doc/index.rst index 12dc09329ca4..ec960007ec8b 100644 --- a/boards/google/quincy/doc/index.rst +++ b/boards/google/quincy/doc/index.rst @@ -26,6 +26,8 @@ Peripheral Mapping Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Build application as usual for the ``google_quincy`` board target, and flash using μServo or an external J-Link connected to J4. If μServo is used, please follow the `Chromium EC Flashing Documentation`_ and diff --git a/boards/google/twinkie_v2/doc/index.rst b/boards/google/twinkie_v2/doc/index.rst index 3ba2f42e2672..89450cf04ffa 100644 --- a/boards/google/twinkie_v2/doc/index.rst +++ b/boards/google/twinkie_v2/doc/index.rst @@ -14,22 +14,7 @@ Hardware Supported Features ================== -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/google/twinkie_v2/google_twinkie_v2_defconfig` +.. zephyr:board-supported-hw:: Pin Mapping =========== @@ -45,6 +30,8 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Build application as usual for the ``google_twinkie_v2`` board, and flash using dfu-util or J-Link. diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst index 0963435fa3d4..3c14c9c23b0f 100644 --- a/boards/hardkernel/odroid_go/doc/index.rst +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -51,23 +51,7 @@ External Connector Supported Features ================== -The Zephyr odroid_go board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: System requirements ******************* @@ -89,6 +73,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts index 386627ff3583..38510fbeadfd 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts @@ -174,3 +174,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst index c4987a76b8fc..abe91f4ca90d 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -39,6 +39,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts index c641e773e072..426a7a133787 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts @@ -115,5 +115,9 @@ status = "okay"; }; +&wifi { + status = "okay"; +}; + /* Required by the ssd1306_128x64 shield which enables the OLED display */ arduino_i2c: &i2c0 {}; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst index 4f6430965e5a..431f83d41ebe 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -20,13 +20,8 @@ The main hardware features are: Supported Features ================== -- LoRa via SPI -- UART0 (USB Serial via CP2102) -- UART1 -- I2C -- CAN (optional, need to enable) -- PWM LED -- User Switch / Button + +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -146,6 +141,8 @@ below to retrieve those files. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts index 9e02e3db483c..631d873cd10b 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts @@ -176,3 +176,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/holyiot/yj16019/board.cmake b/boards/holyiot/yj16019/board.cmake index 4ffa4da95783..6de15b50c296 100644 --- a/boards/holyiot/yj16019/board.cmake +++ b/boards/holyiot/yj16019/board.cmake @@ -1,4 +1,5 @@ board_runner_args(nrfjprog "--softreset") board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/holyiot/yj16019/doc/index.rst b/boards/holyiot/yj16019/doc/index.rst index 86575a0838bc..867fbdf88a6e 100644 --- a/boards/holyiot/yj16019/doc/index.rst +++ b/boards/holyiot/yj16019/doc/index.rst @@ -30,34 +30,7 @@ The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a fr Supported Features ================== -The holyiot_yj16019 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -71,6 +44,8 @@ LED and push button Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``holyiot_yj16019`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details); however, an external diff --git a/boards/iar/index.rst b/boards/iar/index.rst new file mode 100644 index 000000000000..3cc895fdb555 --- /dev/null +++ b/boards/iar/index.rst @@ -0,0 +1,10 @@ +.. _boards-iar: + +IAR +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca b/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca new file mode 100644 index 000000000000..f04f3979a7ea --- /dev/null +++ b/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca @@ -0,0 +1,6 @@ +# Copyright (c) 2016 Linaro Limited. +# Copyright (c) 2025 IAR Systems. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F429II_ACA + select SOC_STM32F429XX diff --git a/boards/iar/stm32f429ii_aca/board.cmake b/boards/iar/stm32f429ii_aca/board.cmake new file mode 100644 index 000000000000..1d0b4be283d6 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32F429II" "--speed=4000") +board_runner_args(pyocd "--target=stm32f429xi") +board_runner_args(pyocd "--flash-opt=-O reset_type=hw") +board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/iar/stm32f429ii_aca/board.yml b/boards/iar/stm32f429ii_aca/board.yml new file mode 100644 index 000000000000..67419bb50680 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/board.yml @@ -0,0 +1,6 @@ +board: + name: stm32f429ii_aca + full_name: STM32F429II-ACA + vendor: iar + socs: + - name: stm32f429xx diff --git a/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp b/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp new file mode 100644 index 000000000000..1ce5bb76c168 Binary files /dev/null and b/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp differ diff --git a/boards/iar/stm32f429ii_aca/doc/index.rst b/boards/iar/stm32f429ii_aca/doc/index.rst new file mode 100644 index 000000000000..cc95c94a0ff5 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/doc/index.rst @@ -0,0 +1,138 @@ +.. zephyr:board:: stm32f429ii_aca + +Overview +******** + +The IAR STM32F429II-ACA evaluation board features an ARM Cortex-M4 based STM32F429II MCU. +Here are some highlights of the STM32F429II-ACA board: + +- STM32 microcontroller in LQFP144 package +- JTAG/SWD debugger/programmer interface +- Flexible board power supply + + - JTAG/SWD connector + - USB HS connector + +- 3x user push-buttons and 1x RESET push-button +- Open-close switch and on-auto-off switch +- 2x capacitive touch panels +- USB OTG with mini-USB connector +- Small speaker +- Trimmer potentiometer +- Nine LEDs + + - 1x power LED + - 3x car traffic light LEDs + - 2x pedestrian traffic light LEDs + - 1x car interior light LED + - 2x user LEDs + +Schematics for the board can be found `here `_ + +Hardware +******** + +The STM32F429II-ACA evaluation board provides the following hardware components: + +- STM32F429II in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Internal Flash +- 4 Mbit External Flash +- 256+4 KB SRAM including 64-KB of core coupled memory +- GPIO with external interrupt capability +- 12-bit ADC +- 12-bit DAC +- RTC +- General Purpose Timers +- I2C +- SPI +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F429II can be found here: + +- `STM32F429II on www.st.com`_ +- `STM32F429 Reference Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Default Zephyr Peripheral Mapping: +---------------------------------- +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB7 +- I2C_2_SCL : PH4 +- I2C_2_SDA : PH5 +- SPI_5_NSS : PF6 +- SPI_5_SCK : PF7 +- SPI_5_MISO : PF8 +- SPI_5_MOSI : PF9 +- OTG_HS_ID : PB12 +- OTG_HS_DM : PB14 +- OTG_HS_DP : PB15 + +Serial Port +=========== + +By default, the STM32F429II-ACA evaluation board has no physical serial port available. +The board has up to 8 UARTs, of which none are used. + +USB Port +======== + +The STM32F429II-ACA evaluation board has a USB HS capable Mini-USB port. It is connected to the on-chip +OTG_HS peripheral. + +Programming and Debugging +************************* + +Applications for the ``stm32f429ii_aca`` board configuration can be built +and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +In order to flash this board using west, an external debug probe such as a Segger J-Link +has to be connected through the JTAG/SWD connector on the board. +By default, the board is set to be flashed using the jlink runner. +Alternatively, openocd, or pyocd can also be used as runners to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + +First, connect the STM32F429II-ACA evaluation board to your host computer using +your debug probe through the JTAG/SWD connector to prepare it for flashing. +Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f429ii_aca + :goals: build flash + +LED0 should then begin to blink continuously with a 1-second delay. + +References +********** + +.. target-notes:: + +.. _stm32f429ii-aca-schematics: + https://iar.my.salesforce.com/sfc/p/#30000000YATY/a/Qx000000vZVh/EzlIqYKIBVXN8PN4Q8MgtowSZrR_vZarwLiNJXw7UJw + +.. _STM32F429II on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f429ii.html + +.. _STM32F429 Reference Manual: + https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts new file mode 100644 index 000000000000..ff7635b676d3 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 IAR Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "IAR STM32F429II-ACA board"; + compatible = "iar,stm32f429ii-aca"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,ccm = &ccm0; + }; + + sdram2: sdram@d0000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0xd0000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM2"; + }; + + leds { + compatible = "gpio-leds"; + + traffic_red_led: led_0 { + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + + traffic_yellow_led: led_1 { + gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + traffic_green_led: led_2 { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + + car_led: led_3 { + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + + pedestrian_red_led: led_4 { + gpios = <&gpiod 7 GPIO_ACTIVE_LOW>; + label = "LED4"; + }; + + pedestrian_green_led: led_5 { + gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; + label = "LED5"; + }; + + user_led_1: led_6 { + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + label = "LED6"; + }; + + user_led_2: led_7 { + gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + label = "LED7"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button0: button_0 { + label = "BUT0"; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + button1: button_1 { + label = "BUT1"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + button2: button_2 { + label = "BUT2"; + gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + open_close_switch: switch_0 { + label = "OPEN/CLOSE SWITCH"; + gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + + interior_light_switch_on: switch_1 { + label = "ON"; + gpios = <&gpioi 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + interior_light_switch_auto: switch_2 { + label = "AUTO"; + gpios = <&gpioi 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + interior_light_switch_off: switch_3 { + label = "OFF"; + gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + cap_button0: cap_button_0 { + label = "CAP_BUT0"; + gpios = <&gpioh 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + cap_button1: cap_button_1 { + label = "CAP_BUT1"; + gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &traffic_red_led; + led1 = &traffic_yellow_led; + led2 = &traffic_green_led; + led3 = &car_led; + led4 = &pedestrian_red_led; + led5 = &pedestrian_green_led; + led6 = &user_led_1; + led7 = &user_led_2; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &open_close_switch; + sw4 = &interior_light_switch_on; + sw5 = &interior_light_switch_auto; + sw6 = &interior_light_switch_off; + sw7 = &cap_button0; + sw8 = &cap_button1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <336>; + div-p = <2>; + div-q = <7>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_ph5>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + + +&spi5 { + pinctrl-0 = <&spi5_nss_pf6 &spi5_sck_pf7 + &spi5_miso_pf8 &spi5_mosi_pf9>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>; +}; + +&fmc { + status = "okay"; + pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 + &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3 + &fmc_sdne0_pc2 &fmc_sdnras_pf11 &fmc_sdncas_pg15 + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 + &fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 + &fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 + &fmc_a12_pg2 &fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5 + &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 + &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 + &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 + &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>; + pinctrl-names = "default"; + + sdram { + status = "okay"; + + power-up-delay = <100>; + num-auto-refresh = <1>; + mode-register = <0>; + refresh-rate = <1386>; + + bank@1 { + reg = <1>; + + st,sdram-control = ; + st,sdram-timing = <2 7 4 7 2 2 2>; + }; + }; +}; + +&adc2 { + compatible = "st,stm32f4-adc", "st,stm32-adc"; + pinctrl-0 = <&adc2_in6_pa6>; + pinctrl-names = "default"; + st,adc-prescaler = <2>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + reg = <6>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&dac1 { + pinctrl-0 = <&dac_out2_pa5>; + pinctrl-names = "default"; + status = "okay"; +}; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pb14 &usb_otg_hs_dp_pb15 &usb_otg_hs_id_pb12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml new file mode 100644 index 000000000000..b430c8f5d9bf --- /dev/null +++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml @@ -0,0 +1,15 @@ +identifier: stm32f429ii_aca +name: IAR STM32F429II ACA +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - iar +ram: 192 +flash: 2048 +supported: + - counter + - i2c + - spi +vendor: iar diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig b/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig new file mode 100644 index 000000000000..75a3154c8fb1 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/iar/stm32f429ii_aca/support/openocd.cfg b/boards/iar/stm32f429ii_aca/support/openocd.cfg new file mode 100644 index 000000000000..fa1360a71432 --- /dev/null +++ b/boards/iar/stm32f429ii_aca/support/openocd.cfg @@ -0,0 +1,17 @@ +source [find interface/cmsis-dap.cfg] + +set CHIPNAME STM32F429IITx +set BOARDNAME STM32F429II-ACA + +source [find target/stm32f4x.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/index.rst b/boards/index.rst index 0643a355e590..3cc92770cfeb 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -3,26 +3,32 @@ Supported Boards and Shields ############################ -If you are looking to add Zephyr support for a new board, please start with the -:ref:`board_porting_guide`. +This page lists all the boards and shields that are currently supported in Zephyr. -When adding support documentation for a board, remember to use the template -available under :zephyr_file:`doc/templates/board.tmpl`. +If you are looking to add Zephyr support for a new board, please start with the +:ref:`board_porting_guide`. When adding support documentation for a board, remember to use the +template available under :zephyr_file:`doc/templates/board.tmpl`. -Shields are hardware add-ons that can be stacked on top of a board to add extra -functionality. They are listed separately from boards, towards :ref:`the end of -this page `. +Shields are hardware add-ons that can be stacked on top of a board to add extra functionality. +Refer to the :ref:`shield_porting_guide` for more information on how to port a shield. .. admonition:: Search Tips :class: dropdown - * Use the form below to filter the list of supported boards. If a field is left empty, it will - not be used in the filtering process. + * Use the form below to filter the list of supported boards and shields. If a field is left + empty, it will not be used in the filtering process. + + * Filtering by name and vendor is available for both boards and shields. The rest of the fields + apply only to boards. - * A board must meet **all** criteria selected across different fields. For example, if you select - both a vendor and an architecture, only boards that match both will be displayed. Within a - single field, selecting multiple options (such as two architectures) will show boards matching - **either** option. + * A board/shield must meet **all** criteria selected across different fields. For example, if you + select both a vendor and an architecture, only boards that match both will be displayed. Within + a single field, selecting multiple options (such as two architectures) will show boards + matching **either** option. + + * The list of supported hardware features for each board is automatically generated using + information from the Devicetree. It may not be reflecting the full list of supported features + since some of them may not be enabled by default. * Can't find your exact board? Don't worry! If a similar board with the same or a closely related MCU exists, you can use it as a :ref:`starting point ` for adding @@ -36,14 +42,3 @@ this page `. */index .. zephyr:board-catalog:: - -.. _boards-shields: - -Shields -####### - -.. toctree:: - :maxdepth: 1 - :glob: - - shields/**/* diff --git a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst index 8395bcd98ce6..a7c2ad2f4f62 100644 --- a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst +++ b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst @@ -28,31 +28,7 @@ For more information about the CY8C624ABZI-S2D44 MCU SoC and CY8CKIT-062S2-AI bo Supported Features ================== -The ``cy8ckit_062s2_ai/cy8c624abzi_s2d44`` board target supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the defconfig and dts files: - - - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig` - - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts` +.. zephyr:board-supported-hw:: System Clock ============ @@ -87,6 +63,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CKIT-062S2-AI board includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, diff --git a/boards/infineon/cy8ckit_062s4/doc/index.rst b/boards/infineon/cy8ckit_062s4/doc/index.rst index b5e3e39cc1d8..8a1efe9fe282 100644 --- a/boards/infineon/cy8ckit_062s4/doc/index.rst +++ b/boards/infineon/cy8ckit_062s4/doc/index.rst @@ -24,25 +24,7 @@ Hardware Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig` +.. zephyr:board-supported-hw:: Clock Configuration =================== @@ -77,6 +59,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CKIT-062S4 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. Infineon OpenOCD Installation diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 063b782a33f9..54183d73c1cc 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -20,6 +20,3 @@ CONFIG_GPIO=y # Enable clock controller CONFIG_CLOCK_CONTROL=y - -# Main Stack Size -CONFIG_MAIN_STACK_SIZE=2048 diff --git a/boards/infineon/cy8cproto_062_4343w/doc/index.rst b/boards/infineon/cy8cproto_062_4343w/doc/index.rst index f04c28e5d00a..c4696ca8d866 100644 --- a/boards/infineon/cy8cproto_062_4343w/doc/index.rst +++ b/boards/infineon/cy8cproto_062_4343w/doc/index.rst @@ -49,27 +49,7 @@ Kit Contents: Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` - +.. zephyr:board-supported-hw:: System Clock ============ @@ -105,6 +85,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CPROTO-062-4343W includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. Infineon OpenOCD Installation diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index 0cbfa3b2e658..51c814073a30 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -22,8 +22,5 @@ CONFIG_GPIO=y # Enable clock controller CONFIG_CLOCK_CONTROL=y -# Main Stack Size -CONFIG_MAIN_STACK_SIZE=2048 - # Add catcm0p sleep images for CM0 Devices CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y diff --git a/boards/infineon/cy8cproto_063_ble/doc/index.rst b/boards/infineon/cy8cproto_063_ble/doc/index.rst index 90623b80382e..f3c832605137 100644 --- a/boards/infineon/cy8cproto_063_ble/doc/index.rst +++ b/boards/infineon/cy8cproto_063_ble/doc/index.rst @@ -22,38 +22,7 @@ For more information about the PSOC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| SPI | on-chip | SPI | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ -| I2C | on-chip | I2C | -+-----------+------------+-----------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-----------------------+ -| Counter | on-chip | Counter | -+-----------+------------+-----------------------+ -| Bluetooth | on-chip | Bluetooth | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` +.. zephyr:board-supported-hw:: System Clock ============ @@ -89,6 +58,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + The CY8CPROTO-063-BLE includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. Infineon OpenOCD Installation diff --git a/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig index 645567a40c7e..f58a5582d26f 100644 --- a/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig +++ b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig @@ -11,3 +11,6 @@ endchoice config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 10096 + +config ROM_START_OFFSET + default 0x0 if BOOTLOADER_MCUBOOT diff --git a/boards/infineon/cyw920829m2evk_02/board.cmake b/boards/infineon/cyw920829m2evk_02/board.cmake index be95fa715a3f..76fe7d1bdc4e 100644 --- a/boards/infineon/cyw920829m2evk_02/board.cmake +++ b/boards/infineon/cyw920829m2evk_02/board.cmake @@ -2,6 +2,21 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(openocd "--target-handle=TARGET.cm33") + +# MCUboot requires a flashloader with 64k erase size, please use 'west blobs fetch hal_infineon' to download it. +if(CONFIG_BOOTLOADER_MCUBOOT) + set(flashloader_blobs_path ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/zephyr/blobs/flashloader/TARGET_CYW920829M2EVK-02) + + if(NOT EXISTS ${flashloader_blobs_path}/CYW208xx_SMIF_64K.FLM) + message(WARNING "MCUboot requires a flashloader with 64k erase size, please use 'west blobs fetch hal_infineon' to download it") + else() + board_runner_args(openocd "--openocd-search=${flashloader_blobs_path}") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_CYW208xx_SMIF_64K.cfg") + endif() +endif() + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) board_runner_args(jlink "--device=CYW20829_tm") include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +set_property(TARGET runners_yaml_props_target PROPERTY hex_file zephyr_merged.hex) diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index 92a748d2ee1b..b39883679801 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -19,7 +19,8 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &app_region; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; zephyr,console = &uart2; zephyr,shell-uart = &uart2; zephyr,bt-hci = &bluetooth; @@ -99,45 +100,48 @@ uart2: &scb2 { status = "okay"; }; -/ { - qspi_flash: qspi_flash@40890000 { - compatible = "infineon,cat1-qspi-flash"; - reg = <0x40890000 0x30000>; + +&qspi_flash { + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_M(1)>; + write-block-size = <1>; + erase-block-size = ; #address-cells = <1>; #size-cells = <1>; - flash0: flash@8000000 { - compatible = "soc-nv-flash"; - reg = <0x08000000 DT_SIZE_K(512)>; - write-block-size = <1>; - erase-block-size = ; + /* Keep bootstrap_region node to know size, finaly it will + * locate on beginning of code-partition. The BootROM copies + * bootstrap application in RAM and launches it. + */ + bootstrap_region: bootstrap_region@0 { + reg = <0 BOOTSTRAP_SIZE>; + }; + + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - toc2_region: toc2_region@8000000 { - compatible = "zephyr,memory-region", "soc-nv-flash"; - zephyr,memory-region = "APP_HEADER_FLASH"; - reg = <0x08000000 0x50>; - }; - bootstrap_region: bootstrap_region@8000050 { - compatible = "zephyr,memory-region", "soc-nv-flash"; - zephyr,memory-region = "BOOTSTRAP_FLASH"; - reg = <0x08000050 DT_SIZE_K(12)>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x20000>; + read-only; }; - app_region: app_region@8003050 { - compatible = "soc-nv-flash"; - reg = <0x08003050 0x6CFB0>; /* 435kb */ + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x20000 0x60000>; }; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x80000 0x60000>; + }; - storage_partition: storage_partition@60000 { - compatible = "soc-nv-flash"; - reg = <0x60000 DT_SIZE_K(64)>; - }; + storage_partition: storage_partition@E0000 { + compatible = "soc-nv-flash"; + reg = <0xE0000 DT_SIZE_K(64)>; }; }; }; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig index 156152944b6a..c59deaae71c2 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -20,8 +20,5 @@ CONFIG_GPIO=y # Enable clock controller CONFIG_CLOCK_CONTROL=y -# Main Stack Size -CONFIG_MAIN_STACK_SIZE=2048 - # Enable code/data relocation to move SMIF driver into RAM CONFIG_CODE_DATA_RELOCATION=y diff --git a/boards/infineon/cyw920829m2evk_02/doc/index.rst b/boards/infineon/cyw920829m2evk_02/doc/index.rst index d4c5193c3820..f1101dc3e9c9 100644 --- a/boards/infineon/cyw920829m2evk_02/doc/index.rst +++ b/boards/infineon/cyw920829m2evk_02/doc/index.rst @@ -3,9 +3,19 @@ Overview ******** -The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board peripherals enables evaluation, prototyping, and development of a wide array of Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases including industrial IoT applications, smart home, asset tracking, beacons and sensors, and medical devices. - -The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO support with extended headers and Arduino Uno R3 compatibility for third-party shields. +The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board +peripherals enables evaluation, prototyping, and development of a wide array of +Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. +The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power +amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases +including industrial IoT applications, smart home, asset tracking, beacons and sensors, and +medical devices. + +The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with +programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a +suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, +analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO +support with extended headers and Arduino Uno R3 compatibility for third-party shields. Hardware ******** @@ -20,7 +30,8 @@ Kit Features: - AIROC™ CYW20829 Bluetooth® LE MCU in 56 pin QFN package - Arduino compatible headers for hardware expansion -- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, and Infineon digital microphone +- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, + and Infineon digital microphone - User switches, RGB LED and user LEDs - USB connector for power, programming and USB-UART bridge @@ -36,26 +47,7 @@ Kit Contents: Supported Features ================== -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig` +.. zephyr:board-supported-hw:: System Clock ============ @@ -88,24 +80,40 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat Programming and Debugging ************************* -The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. +.. zephyr:board-supported-runners:: -The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. This can be enabled for an application by building with the rtt-console snippet or setting the following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y. +The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, +flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and +require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. +This can be enabled for an application by building with the rtt-console snippet or setting the +following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y. e.g. west build -p always -b cyw920829m2evk_02 samples/basic/blinky -S rtt-console -As an additional note there is currently a discrepancy in RAM address between SEGGER and the CYW920829M2EVK-02 device. So, for RTT control block, do not use "Auto Detection". Instead, set the search range to something reflecting: RAM RangeStart at 0x20000000 and RAM RangeSize of 0x3d000. +As an additional note there is currently a discrepancy in RAM address between SEGGER and the +CYW920829M2EVK-02 device. So, for RTT control block, do not use "Auto Detection". Instead, set +the search range to something reflecting: RAM RangeStart at 0x20000000 and RAM RangeSize of 0x3d000. Infineon OpenOCD Installation ============================= -Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon +OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package +is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for +your system and manually extract the files to a location of your choice. -.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled + automatically by the ModusToolbox and ModusToolbox Programming Tools installations. + When doing a minimal installation, this can be done manually by executing the + script ``openocd/udev_rules/install_rules.sh``. West Commands ============= -The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool +commands. There are multiple ways of doing this. The example below uses a permanent CMake argument +to set the CMake variable ``OPENOCD``. .. tabs:: .. group-tab:: Windows @@ -134,7 +142,101 @@ The path to the installed Infineon OpenOCD executable must be available to the ` west flash west debug -Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the CYW20829 CM33 core. +Once the gdb console starts after executing the west debug command, you may now set breakpoints and +perform other standard GDB debugging on the CYW20829 CM33 core. + +Operate in SECURE Lifecycle Stage +********************************* + +The device lifecycle stage (LCS) is a key aspect of the security of the AIROC™ +CYW20829 Bluetooth® MCU. The lifecycle stages follow a strict, irreversible progression dictated by +the programming of the eFuse bits (changing the value from "0" to "1"). This system is used to +protect the device's data and code at the level required by the user. +SECURE is the lifecycle stage of a secured device. +Follow the instructions in `AN239590 Provision CYW20829 to SECURE LCS`_ to transition the device +to SECURE LCS. In the SECURE LCS stage, the protection state is set to secure. A secured device +will only boot if the authentication of its flash content is successful. + +The following configuration options can be used to build for a device which has been provisioned +to SECURE LCS and configured to use an encrypted flash interface: + +- :kconfig:option:`CONFIG_INFINEON_SECURE_LCS`: Enable if the target device is in SECURE LCS +- :kconfig:option:`CONFIG_INFINEON_SECURE_POLICY`: Path to the policy JSON file, + which was created for provisioning the device to SECURE LCS (refer to section 3.2 "Key creation" + of `AN239590 Provision CYW20829 to SECURE LCS`_) +- :kconfig:option:`CONFIG_INFINEON_SMIF_ENCRYPTION`: Enable to use encrypted flash interface when provisioned to + SECURE LCS. + +Here is an example for building the :zephyr:code-sample:`blinky` sample application for SECURE LCS. + +.. zephyr-app-commands:: + :goals: build + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_INFINEON_SECURE_LCS=y -DCONFIG_INFINEON_SECURE_POLICY=\"policy/policy_secure.json\" + +Using MCUboot +************* + +CYW20829 devices are supported by the Cypress MCU bootloader (MCUBootApp) from the +`Cypress branch of MCUboot`_. + +Building Cypress MCU Bootloader MCUBootApp +========================================== + +Please refer to the `CYW20829 platform description`_ and follow the instructions to understand the +MCUBootApp building process for normal/secure silicon and its overall usage as a bootloader. +Place keys and policy-related folders in the cypress directory ``mcuboot/boot/cypress/``. + +Ensure the default memory map matches the memory map of the Zephyr application (refer to partitions +of flash0 in :zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts`). + +You can use ``west flash`` to flash MCUBootApp: + +.. code-block:: shell + + # Flash MCUBootApp.hex + west flash --skip-rebuild --hex-file /path/to/cypress/mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.hex + +.. note:: ``west flash`` requires an existing Zephyr build directory which can be created by first + building any Zephyr application for the target board. + +Build Zephyr application +======================== +Here is an example for building and flashing the :zephyr:code-sample:`blinky` sample application +for MCUboot. + +.. zephyr-app-commands:: + :goals: build flash + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"/path/to/cypress/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pem\" + +If you use :kconfig:option:`CONFIG_MCUBOOT_ENCRYPTION_KEY_FILE` to generate an encrypted image then the final +hex will be ``zephyr.signed.encrypted.hex`` and the corresponding bin file will +be ``zephyr.signed.encrypted.bin``. Use these files for flashing and ota uploading respectively. +For example, to build and flash an encrypted :zephyr:code-sample:`blinky` sample application +image for MCUboot: + +.. zephyr-app-commands:: + :goals: build flash + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"/path/to/cypress/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pem\" -DCONFIG_MCUBOOT_ENCRYPTION_KEY_FILE=\"/path/to/cypress/mcuboot/enc-ec256-pub.pem\" + :flash-args: --hex-file build/zephyr/zephyr.signed.encrypted.hex + + +.. _CYW20829 platform description: + https://github.com/mcu-tools/mcuboot/blob/v1.9.4-cypress/boot/cypress/platforms/CYW20829.md + +.. _Cypress branch of MCUboot: + https://github.com/mcu-tools/mcuboot/tree/cypress + +.. _AN239590 Provision CYW20829 to SECURE LCS: + https://www.infineon.com/dgdl/Infineon-AN239590_Provision_CYW20829_CYW89829_to_Secure_LCS-ApplicationNotes-v02_00-EN.pdf?fileId=8ac78c8c8d2fe47b018e3677dd517258 .. _CYW20829 SoC Website: https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/ diff --git a/boards/infineon/cyw920829m2evk_02/support/openocd.cfg b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg index fe70fb383a8a..d6578e98a03a 100644 --- a/boards/infineon/cyw920829m2evk_02/support/openocd.cfg +++ b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg @@ -2,7 +2,6 @@ # Copyright (c) 2018 Linaro Limited. # # SPDX-License-Identifier: Apache-2.0 - source [find interface/kitprog3.cfg] transport select swd diff --git a/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg b/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg new file mode 100644 index 000000000000..d1f0a09f855b --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 Linaro Limited. +# +# SPDX-License-Identifier: Apache-2.0 +set QSPI_FLASHLOADER "CYW208xx_SMIF_64K.FLM" + +source [find openocd.cfg] diff --git a/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk b/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk new file mode 100644 index 000000000000..aced322b3028 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KIT_XMC72_EVK + select SOC_XMC7200D_E272K8384_M0PLUS if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M0P + select SOC_XMC7200D_E272K8384_M7_0 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_0 + select SOC_XMC7200D_E272K8384_M7_1 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_1 diff --git a/boards/infineon/kit_xmc72_evk/board.cmake b/boards/infineon/kit_xmc72_evk/board.cmake new file mode 100644 index 000000000000..f1b6975385bc --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Connect to CM0P core. +board_runner_args(openocd "--target-handle=cat1c.cpu.cm0") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/kit_xmc72_evk/board.yml b/boards/infineon/kit_xmc72_evk/board.yml new file mode 100644 index 000000000000..84d3c3898ebb --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/board.yml @@ -0,0 +1,6 @@ +board: + name: kit_xmc72_evk + full_name: XMC7200 Evaluation Kit + vendor: infineon + socs: + - name: xmc7200d_e272k8384 diff --git a/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp b/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp new file mode 100644 index 000000000000..18338ea90ca8 Binary files /dev/null and b/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp differ diff --git a/boards/infineon/kit_xmc72_evk/doc/index.rst b/boards/infineon/kit_xmc72_evk/doc/index.rst new file mode 100644 index 000000000000..dcb62ea0e104 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/doc/index.rst @@ -0,0 +1,146 @@ +.. zephyr:board:: kit_xmc72_evk + +Overview +******** + +The XMC7200 evaluation kit enables you to evaluate and develop your applications using the XMC7200D +microcontroller(hereafter called “XMC7200D”). The XMC7200D is designed for industrial applications +and it is a true programmable embedded system-on-chip, integrating up to two 350-MHz Arm® Cortex®-M7 +as the primary application processor, a 100-MHz Arm® Cortex®-M0+ that supports the following: + +- Low-power operations +- Up to 8 MB flash and 1 MB SRAM +- Gigabit Ethernet +- CAN FD +- Secure Digital Host Controller (SDHC) supporting SD/SDIO/eMMC interfaces +- Programmable analog and digital peripherals that allow faster time-to-market + +The evaluation board has a M.2 interface connector for interfacing radio modules-based on +AIROC™ Wi-Fi & Bluetooth combos, SMIF dual header compatible with Digilent Pmod for interfacing +HYPERBUS™ memories, and headers compatible with Arduino for interfacing Arduino shields. +In addition, the board features an onboard programmer/debugger(KitProg3), a 512-Mbit QSPI NOR flash, +CAN FD transceiver, Gigabit Ethernet PHY transceiver with RJ45 connector interface, a micro-B +connector for USB device interface, three user LEDs, one potentiometer, and two push buttons. +The board supports operating voltages from 3.3 V to 5.0 V for XMC7200D. + +Hardware +******** + +For more information about XMC7200D and KIT_XMC72_EVK: + +- `XMC7200D SoC Website`_ +- `kit_xmc72_evk Board Website`_ + +Kit Features +============= + +- Evaluation board for XMC7200D-E272K8384 in BGA package with 272 pins, dual-core Arm®Cortex® M7 CPUs running at 350-MHz and an Arm® Cortex® M0+ CPU running at 100-MHz +- Full-system approach on the board, featuring Gigabit Ethernet PHY and connector, CAN FD transceiver, user LEDs, buttons, and potentiometer +- M.2 interface connector for interfacing radio modules based on AIROC™ Wi-Fi & Bluetooth®combos (currently not - supported) +- Headers compatible with Arduino for interfacing Arduino shields +- Fully compatible with ModusToolbox™ v3.0 +- KitProg3 on-board SWD programmer/debugger, USB-UART, and USB-I2C bridge functionality through USB connector +- Digilent dual PMOD SMIF header for interfacing HYPERBUS™ memories (currently not supported) +- A 512-Mbit external QSPI NOR flash +- Evaluation board supports operating voltages from 3.3 V to 5.0 V for XMC7200D + +Kit Contents +============= + +- XMC7200 evaluation board +- USB Type-A to Mirco-B cable +- 12V/3A DC power adapter with additional blades +- Six jumper wires (five inches each) +- Quick start guide + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_xmc72_evk + :goals: build + +Flashing +======== + +The KIT_XMC72_EVK includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. + +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b kit_xmc72_evk -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b kit_xmc72_evk -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. + +References +********** + +.. target-notes:: + +.. _XMC7200D SoC Website: + https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/32-bit-xmc7000-industrial-microcontroller-arm-cortex-m7/xmc7200d-e272k8384aa/ + +.. _kit_xmc72_evk Board Website: + https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc72_evk + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi new file mode 100644 index 000000000000..66cc3376f4ac --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + aliases { + uart-3 = &uart3; + led0 = &user_led0; + led1 = &user_led1; + led2 = &user_led2; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt16 1 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt16 2 GPIO_ACTIVE_LOW>; + }; + + user_led2: led_2 { + label = "LED_2"; + gpios = <&gpio_prt16 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt21 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt17 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +uart3: &scb3 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + + /* UART pins */ + pinctrl-0 = <&p13_1_scb3_uart_tx &p13_0_scb3_uart_rx + &p13_2_scb3_uart_rts &p13_3_scb3_uart_cts>; + pinctrl-names = "default"; +}; + +&gpio_prt13 { + status = "okay"; +}; + +&gpio_prt16 { + status = "okay"; +}; + +&gpio_prt21 { + status = "okay"; +}; + +&gpio_prt17 { + status = "okay"; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_mem { + status = "okay"; +}; + +&clk_peri { + status = "okay"; +}; + +&clk_slow { + status = "okay"; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi new file mode 100644 index 000000000000..56433a55d12d --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart2 pins */ +&p13_1_scb3_uart_tx { + drive-push-pull; +}; + +&p13_0_scb3_uart_rx { + input-enable; +}; + +&p13_2_scb3_uart_rts { + drive-push-pull; +}; + +&p13_3_scb3_uart_cts { + input-enable; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts new file mode 100644 index 000000000000..0820c7d66937 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + model = "Infineon Evaluation board for XMC7200D-E272K8384 M0"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + chosen { + zephyr,sram = &m0p_code; + zephyr,flash = &m0p_data; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml new file mode 100644 index 000000000000..f9c85c01943a --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml @@ -0,0 +1,15 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m0p +name: XMC7200 Evaluation Kit (M0P) +type: mcu +arch: arm +ram: 1024 +flash: 8384 +toolchain: + - zephyr + - gnuarmemb +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig new file mode 100644 index 000000000000..092553cedd53 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig @@ -0,0 +1,24 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts new file mode 100644 index 000000000000..ba9993f34c59 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + + model = "Infineon Evaluation board for XMC7200D-E272K8384 M7"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + aliases { + uart-3 = &uart3; + }; + + chosen { + zephyr,sram = &cm7_0_code; + zephyr,flash = &cm7_0_data; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml new file mode 100644 index 000000000000..745e4a09d588 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_0 +name: XMC7200 Evaluation Kit (M7_0) +type: mcu +arch: arm +ram: 1024 +flash: 8384 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig new file mode 100644 index 000000000000..ad327f905397 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts new file mode 100644 index 000000000000..ce8b078d7e4b --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + + model = "Infineon Evaluation board for XMC7200D-E272K8384 M7"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + aliases { + uart-3 = &uart3; + }; + + chosen { + zephyr,sram = &cm7_1_code; + zephyr,flash = &cm7_1_data; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml new file mode 100644 index 000000000000..e74a7b3f821c --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_1 +name: XMC7200 Evaluation Kit (M7_1) +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig new file mode 100644 index 000000000000..ad327f905397 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/support/openocd.cfg b/boards/infineon/kit_xmc72_evk/support/openocd.cfg new file mode 100644 index 000000000000..4d4249c56318 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/support/openocd.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + #default connect over Debug USB port + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +source [find target/cat1c.cfg] \ No newline at end of file diff --git a/boards/infineon/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst index bfad619aedc3..5d89d5e2dbd1 100644 --- a/boards/infineon/xmc45_relax_kit/doc/index.rst +++ b/boards/infineon/xmc45_relax_kit/doc/index.rst @@ -22,50 +22,9 @@ Details on the Relax Kit development board can be found in the `Relax Kit User M Supported Features ================== -* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz. - -The Relax Kit development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-----------------------+ -| ADC | on-chip | adc | -+-----------+------------+-----------------------+ -| DMA | on-chip | dma | -+-----------+------------+-----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-----------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-----------------------+ -| MDIO | on-chip | mdio | -+-----------+------------+-----------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-----------------------+ -| PTP | on-chip | ethernet | -+-----------+------------+-----------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-----------------------+ - -More details about the supported peripherals are available in `XMC4500 TRM`_ - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig` - -Other hardware features are not currently supported by the Zephyr kernel. +.. zephyr:board-supported-hw:: + +The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz. Build hello world sample ************************ @@ -78,6 +37,9 @@ Here is an example for building the :zephyr:code-sample:`hello_world` sample app Programming and Debugging ************************* + +.. zephyr:board-supported-runners:: + West Commands ============= Here is an example for the :zephyr:code-sample:`hello_world` application. diff --git a/boards/infineon/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst index d5796afd7ea8..09aa90843a03 100644 --- a/boards/infineon/xmc47_relax_kit/doc/index.rst +++ b/boards/infineon/xmc47_relax_kit/doc/index.rst @@ -27,47 +27,9 @@ Details on the Relax Kit development board can be found in the `Relax Kit User M Supported Features ================== -The Relax Kit development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-----------------------+ -| ADC | on-chip | adc | -+-----------+------------+-----------------------+ -| DMA | on-chip | dma | -+-----------+------------+-----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-----------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-----------------------+ -| MDIO | on-chip | mdio | -+-----------+------------+-----------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-----------------------+ -| PTP | on-chip | ethernet | -+-----------+------------+-----------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-----------------------+ +.. zephyr:board-supported-hw:: More details about the supported peripherals are available in `XMC4700 TRM`_ -Other hardware features are not currently supported by the Zephyr kernel. - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig` Build hello world sample ************************ @@ -80,6 +42,9 @@ Here is an example for building the :zephyr:code-sample:`hello_world` sample app Programming and Debugging ************************* + +.. zephyr:board-supported-runners:: + West Commands ============= Here is an example for the :zephyr:code-sample:`hello_world` application. diff --git a/boards/innblue/innblue21/board.cmake b/boards/innblue/innblue21/board.cmake index 12afc83afe36..641562c24c49 100644 --- a/boards/innblue/innblue21/board.cmake +++ b/boards/innblue/innblue21/board.cmake @@ -2,5 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst index bafb7d9911a4..6a923bc969a3 100644 --- a/boards/innblue/innblue21/doc/index.rst +++ b/boards/innblue/innblue21/doc/index.rst @@ -20,34 +20,7 @@ The following parts are built into the board: Supported Features ================== -The innblue21 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -77,6 +50,8 @@ Security components Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + innblue21 supports the Armv8m Security Extension, and by default boots in the Secure state. diff --git a/boards/innblue/innblue21/innblue21_common.dtsi b/boards/innblue/innblue21/innblue21_common.dtsi index fbe58ffbe221..6e638823e3ea 100644 --- a/boards/innblue/innblue21/innblue21_common.dtsi +++ b/boards/innblue/innblue21/innblue21_common.dtsi @@ -160,4 +160,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/innblue/innblue22/board.cmake b/boards/innblue/innblue22/board.cmake index 12afc83afe36..641562c24c49 100644 --- a/boards/innblue/innblue22/board.cmake +++ b/boards/innblue/innblue22/board.cmake @@ -2,5 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst index 9e84c4691dfa..d87a7b222a81 100644 --- a/boards/innblue/innblue22/doc/index.rst +++ b/boards/innblue/innblue22/doc/index.rst @@ -20,34 +20,7 @@ The following parts are built into the board: Supported Features ================== -The innblue22 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -77,6 +50,8 @@ Security components Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + innblue22 supports the Armv8m Security Extension, and by default boots in the Secure state. diff --git a/boards/innblue/innblue22/innblue22_common.dtsi b/boards/innblue/innblue22/innblue22_common.dtsi index 6ba2b69bf72f..433cc38c7ab3 100644 --- a/boards/innblue/innblue22/innblue22_common.dtsi +++ b/boards/innblue/innblue22/innblue22_common.dtsi @@ -163,4 +163,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/intel/adl/Kconfig.defconfig b/boards/intel/adl/Kconfig.defconfig index 3a6bcaf9ce02..4e3f649a205d 100644 --- a/boards/intel/adl/Kconfig.defconfig +++ b/boards/intel/adl/Kconfig.defconfig @@ -7,10 +7,10 @@ config BUILD_OUTPUT_STRIPPED config MP_MAX_NUM_CPUS default 2 -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +# TSC on this board is 1.5 GHz, HPET and APIC are 19.2 MHz config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC + default 1500000000 if APIC_TSC_DEADLINE_TIMER + default 1500000000 if APIC_TIMER_TSC default 19200000 if APIC_TIMER diff --git a/boards/intel/adsp/Kconfig.defconfig b/boards/intel/adsp/Kconfig.defconfig index eafedb0c550e..8c804c48c750 100644 --- a/boards/intel/adsp/Kconfig.defconfig +++ b/boards/intel/adsp/Kconfig.defconfig @@ -8,3 +8,18 @@ config DAI_SSP_HAS_POWER_CONTROL def_bool y endif + +if BOARD_INTEL_ADSP + +config MAIN_STACK_SIZE + default 2048 if BOARD_INTEL_ADSP_CAVS25 + default 2048 if BOARD_INTEL_ADSP_CAVS25_TGPH + default 2048 if BOARD_INTEL_ADSP_ACE15_MTPM + default 2048 if BOARD_INTEL_ADSP_ACE15_MTPM_SIM + default 2048 if BOARD_INTEL_ADSP_ACE20_LNL + default 2048 if BOARD_INTEL_ADSP_ACE20_LNL_SIM + default 4096 if BOARD_INTEL_ADSP_ACE30 + default 4096 if BOARD_INTEL_ADSP_ACE30_PTL + default 4096 if BOARD_INTEL_ADSP_ACE30_PTL_SIM + +endif # BOARD_INTEL_ADSP diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 225a2747ad58..ac62b9e2d52c 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -10,3 +10,5 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake index 0add65864261..e6055be6f37b 100644 --- a/boards/intel/adsp/board.cmake +++ b/boards/intel/adsp/board.cmake @@ -1,4 +1,4 @@ -# Copyright (c) 2022-2024 Intel Corporation +# Copyright (c) 2022-2025 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 @@ -47,4 +47,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI board_finalize_runner_args(intel_adsp) +elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM) + + board_set_rimage_target(wcl) + + set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") + + board_finalize_runner_args(intel_adsp) + endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index c169a14487b0..5bc812edb37a 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -17,3 +17,6 @@ boards: - name: 'ptl' variants: - name: 'sim' + - name: 'wcl' + variants: + - name: 'sim' diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig index 2237dfb963a2..9c0d2ca0cda6 100644 --- a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig index 7a0513272345..8c36c0e39dda 100644 --- a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_INTEL_ADSP_SIM=y CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig index 3d897eb96732..4f2503e2afcf 100644 --- a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig index 5f03e403e3c7..6acb302da0b7 100644 --- a/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 CONFIG_INTEL_ADSP_SIM=y CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_ace30_defconfig b/boards/intel/adsp/intel_adsp_ace30_defconfig index 913d2a8c3e3a..85f377409f7e 100644 --- a/boards/intel/adsp/intel_adsp_ace30_defconfig +++ b/boards/intel/adsp/intel_adsp_ace30_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=4096 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig index 913d2a8c3e3a..85f377409f7e 100644 --- a/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=4096 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig index 429223286bf0..5373f0c0bf84 100644 --- a/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_INTEL_ADSP_SIM=y CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl.dts b/boards/intel/adsp/intel_adsp_ace30_wcl.dts new file mode 100644 index 000000000000..e488d77181dd --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_wcl"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig new file mode 100644 index 000000000000..85f377409f7e --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts new file mode 100644 index 000000000000..fab0812265e0 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_wcl_sim"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig new file mode 100644 index 000000000000..5373f0c0bf84 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_INTEL_ADSP_SIM=y +CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_cavs25_defconfig b/boards/intel/adsp/intel_adsp_cavs25_defconfig index 24443bce131f..37aab5b06d44 100644 --- a/boards/intel/adsp/intel_adsp_cavs25_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_defconfig @@ -2,8 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig index 7e79840a033c..d842740df75c 100644 --- a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig @@ -2,8 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml index 866f8ff7a90c..c5d8c9f2759c 100644 --- a/boards/intel/adsp/twister.yaml +++ b/boards/intel/adsp/twister.yaml @@ -12,6 +12,20 @@ testing: - bluetooth - mcumgr variants: + intel_adsp/ace30/wcl: + toolchain: + - xt-clang + - zephyr + intel_adsp/ace30/wcl/sim: + type: sim + simulation: + - name: custom + exec: acesim + toolchain: + - xt-clang + - zephyr + testing: + timeout_multiplier: 8 intel_adsp/ace30/ptl: toolchain: - xt-clang diff --git a/boards/intel/btl/CMakeLists.txt b/boards/intel/btl/CMakeLists.txt new file mode 100644 index 000000000000..ee5e7343e837 --- /dev/null +++ b/boards/intel/btl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + ) +endif() diff --git a/boards/intel/btl/Kconfig.defconfig b/boards/intel/btl/Kconfig.defconfig new file mode 100644 index 000000000000..177c7c1f0d2b --- /dev/null +++ b/boards/intel/btl/Kconfig.defconfig @@ -0,0 +1,71 @@ +# Copyright (c) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 2.9 GHz, HPET is 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2900000000 if APIC_TSC_DEADLINE_TIMER + default 2900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 + +endif + +if APIC_TIMER_TSC + +config APIC_TIMER_TSC_M + default 3 + +config APIC_TIMER_TSC_N + default 249 + +endif + +config ACPI + default y + +if ACPI + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 + +config MAIN_STACK_SIZE + default 320000 + +if SHELL + +config SHELL_STACK_SIZE + default 320000 + +endif # SHELL + +endif # ACPI + +if DMA + +config DMA_64BIT + default y + +config DMA_DW_HW_LLI + default n + +config DMA_DW_CHANNEL_COUNT + default 2 + +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y if BOARD_INTEL_BTL_S_CRB + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/btl/Kconfig.intel_btl_s_crb b/boards/intel/btl/Kconfig.intel_btl_s_crb new file mode 100644 index 000000000000..19f802f0c31c --- /dev/null +++ b/boards/intel/btl/Kconfig.intel_btl_s_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_BTL_S_CRB + select SOC_RAPTOR_LAKE diff --git a/boards/intel/btl/board.cmake b/boards/intel/btl/board.cmake new file mode 100644 index 000000000000..6b01bab2aeea --- /dev/null +++ b/boards/intel/btl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/intel/btl/board.yml b/boards/intel/btl/board.yml new file mode 100644 index 000000000000..f3b6dd2e2f81 --- /dev/null +++ b/boards/intel/btl/board.yml @@ -0,0 +1,6 @@ +boards: + - name: intel_btl_s_crb + full_name: Bartlett Lake P CRB + vendor: intel + socs: + - name: raptor_lake diff --git a/boards/intel/btl/doc/index.rst b/boards/intel/btl/doc/index.rst new file mode 100644 index 000000000000..239a679eb893 --- /dev/null +++ b/boards/intel/btl/doc/index.rst @@ -0,0 +1,57 @@ +.. zephyr:board:: intel_btl_s_crb + +Overview +******** +Bartlett Lake processor is a 64-bit multi-core processor built on Intel 7 process +Technology. Bartlett Lake is based on a Hybrid architecture, utilizing +P-cores for performance and E-Cores for efficiency. + +The S-Processor line is a 2-Chip Platform that includes the Processor Die and +Platform Controller Hub (PCH-S) Die in the Package. + +For more information about Raptor Lake Processor lines, P-cores, and E-cores +please refer to `BTL`_. + +This board configuration enables kernel support for the Bartlett Lake S boards. + +Hardware +******** + +.. zephyr:board-supported-hw:: + +General information about the board can be found at the `BTL`_ website. + +Connections and IOs +=================== + +Refer to the `BTL`_ website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image for an Bartlett Lake S CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for Bartlett Lake S CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_btl_s_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _BTL: https://www.intel.com/content/www/us/en/secure/content-details/839635/bartlett-lake-s-processor-external-design-specification-eds-for-edge-platforms.html?DocID=839635 diff --git a/boards/intel/btl/intel_btl_s_crb.dts b/boards/intel/btl/intel_btl_s_crb.dts new file mode 100644 index 000000000000..3ae2d4592c8d --- /dev/null +++ b/boards/intel/btl/intel_btl_s_crb.dts @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#define DT_DRAM_SIZE DT_SIZE_M(2048) + +#include + +/ { + model = "intel_btl_s_crb"; + compatible = "intel,bartlett-lake-crb"; + + chosen { + zephyr,sram = &dram0; + zephyr,console = &uart_ec_0; + zephyr,shell-uart = &uart_ec_0; + }; + + aliases { + watchdog0 = &tco_wdt; + rtc = &rtc; + }; +}; + +&uart_ec_0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/boards/intel/btl/intel_btl_s_crb.yaml b/boards/intel/btl/intel_btl_s_crb.yaml new file mode 100644 index 000000000000..cb340c11d135 --- /dev/null +++ b/boards/intel/btl/intel_btl_s_crb.yaml @@ -0,0 +1,25 @@ +identifier: intel_btl_s_crb +name: Bartlett Lake S CRB +type: mcu +arch: x86 +toolchain: + - zephyr +ram: 2048 +supported: + - acpi + - smp + - spi + - nvme + - gpio + - uart + - tgpio + - pwm + - smbus + - rtc + - watchdog + - i2c +testing: + ignore_tags: + - net + - bluetooth +vendor: intel diff --git a/boards/intel/btl/intel_btl_s_crb_defconfig b/boards/intel/btl/intel_btl_s_crb_defconfig new file mode 100644 index 000000000000..853850deb12c --- /dev/null +++ b/boards/intel/btl/intel_btl_s_crb_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_VARIANT_NS16750=y +CONFIG_UART_CONSOLE=y +CONFIG_X2APIC=y +CONFIG_SMP=y +CONFIG_BUILD_OUTPUT_EFI=y diff --git a/boards/intel/niosv_g/board.yml b/boards/intel/niosv_g/board.yml index 811aee73f34a..3ab04d5103f1 100644 --- a/boards/intel/niosv_g/board.yml +++ b/boards/intel/niosv_g/board.yml @@ -1,5 +1,6 @@ board: name: niosv_g full_name: INTEL FPGA niosv_g + vendor: intel socs: - name: niosv_g diff --git a/boards/intel/niosv_m/board.yml b/boards/intel/niosv_m/board.yml index cc7b9bb3bf53..aeb8d988667e 100644 --- a/boards/intel/niosv_m/board.yml +++ b/boards/intel/niosv_m/board.yml @@ -1,5 +1,6 @@ board: name: niosv_m full_name: INTEL FPGA niosv_m + vendor: intel socs: - name: niosv_m diff --git a/boards/intel/rpl/Kconfig.defconfig b/boards/intel/rpl/Kconfig.defconfig index 4eb5d8c3126c..6478c25f658e 100644 --- a/boards/intel/rpl/Kconfig.defconfig +++ b/boards/intel/rpl/Kconfig.defconfig @@ -8,12 +8,26 @@ config BUILD_OUTPUT_STRIPPED config MP_MAX_NUM_CPUS default 2 -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +if BOARD_INTEL_RPL_S_CRB + +# TSC on this board is 2.4 GHz for RPL-S, HPET and APIC are 19.2 MHz config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC + default 2400000000 if APIC_TSC_DEADLINE_TIMER + default 2400000000 if APIC_TIMER_TSC default 19200000 +endif #BOARD_INTEL_RPL_S_CRB + +if BOARD_INTEL_RPL_P_CRB + +# TSC on this board is 1.8 GHz for RPL-P, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1800000000 if APIC_TSC_DEADLINE_TIMER + default 1800000000 if APIC_TIMER_TSC + default 19200000 + +endif #BOARD_INTEL_RPL_P_CRB + if APIC_TIMER config APIC_TIMER_IRQ default 24 diff --git a/boards/intel/rpl/board.yml b/boards/intel/rpl/board.yml index 9f35b6486991..58f24d3becd7 100644 --- a/boards/intel/rpl/board.yml +++ b/boards/intel/rpl/board.yml @@ -7,5 +7,11 @@ boards: - name: intel_rpl_s_crb full_name: Raptor Lake S CRB vendor: intel + revision: + format: number + default: "600" + revisions: + - name: "600" + - name: "700" socs: - name: raptor_lake diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst index e6bc4015256f..9a256300050c 100644 --- a/boards/intel/rpl/doc/index.rst +++ b/boards/intel/rpl/doc/index.rst @@ -12,7 +12,10 @@ architecture, utilizing P-cores for performance and E-Cores for efficiency. Raptor Lake S and Raptor Lake P processor lines are supported. The S-Processor line is a 2-Chip Platform that includes the Processor Die and -Platform Controller Hub (PCH-S) Die in the Package. +Platform Controller Hub (PCH-S) Die in the Package. There are 2 PCH-s versions +supported for S-Processor line 600 series (ADL) and 700 series (RPL). Default +600 series revision is selected, to select 700 series revision the board name +during build should be ``intel_rpl_s_crb@700``. The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the Processor Die and Platform Controller Hub (PCH-P) Die on the same package as diff --git a/boards/intel/rpl/intel_rpl_s_crb_700.overlay b/boards/intel/rpl/intel_rpl_s_crb_700.overlay new file mode 100644 index 000000000000..7e1aa5ba8e6f --- /dev/null +++ b/boards/intel/rpl/intel_rpl_s_crb_700.overlay @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&smbus0 { + device-id = <0x7a23>; +}; + +&i2c0 { + device-id = <0x7a4c>; +}; + +&i2c1 { + device-id = <0x7a4c>; +}; + +&i2c2 { + device-id = <0x7a4d>; +}; + +&i2c3 { + device-id = <0x7a4e>; +}; + +&i2c4 { + device-id = <0x7a7c>; +}; + +&i2c5 { + device-id = <0x7a7d>; +}; + +&spi0 { + device-id = <0x7a2a>; +}; + +&spi1 { + device-id = <0x7a2b>; +}; + +&spi2 { + device-id = <0x7a7b>; +}; + +&uart0 { + device-id = <0x7a28>; +}; + +&uart1 { + device-id = <0x7a29>; +}; + +&uart2 { + device-id = <0x7a7e>; +}; diff --git a/boards/intel/socfpga/agilex5_socdk/board.yml b/boards/intel/socfpga/agilex5_socdk/board.yml index f8ccbf5d8c5a..13726af50a62 100644 --- a/boards/intel/socfpga/agilex5_socdk/board.yml +++ b/boards/intel/socfpga/agilex5_socdk/board.yml @@ -1,5 +1,6 @@ board: name: intel_socfpga_agilex5_socdk full_name: Agilex™ 5 SoC FPGA Development Kit + vendor: intel socs: - name: agilex5 diff --git a/boards/intel/socfpga/agilex_socdk/board.yml b/boards/intel/socfpga/agilex_socdk/board.yml index 80763baa41b9..fe7d24f4b395 100644 --- a/boards/intel/socfpga/agilex_socdk/board.yml +++ b/boards/intel/socfpga/agilex_socdk/board.yml @@ -1,5 +1,6 @@ board: name: intel_socfpga_agilex_socdk full_name: Agilex SoC Development Kit + vendor: intel socs: - name: agilex diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.yml b/boards/intel/socfpga_std/cyclonev_socdk/board.yml index 222de69429ac..4c47d3f9a5bb 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/board.yml +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.yml @@ -1,5 +1,6 @@ board: name: cyclonev_socdk full_name: Cyclone® V SoC Development Kit + vendor: intel socs: - name: cyclonev diff --git a/boards/ite/it515xx_evb/Kconfig.defconfig b/boards/ite/it515xx_evb/Kconfig.defconfig new file mode 100644 index 000000000000..e5033cdd7c32 --- /dev/null +++ b/boards/ite/it515xx_evb/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT515XX_EVB + +if PM + +config PM_DEVICE + default y + +choice PM_POLICY + default PM_POLICY_CUSTOM +endchoice + +endif # PM + +endif # BOARD_IT515XX_EVB diff --git a/boards/ite/it515xx_evb/Kconfig.it515xx_evb b/boards/ite/it515xx_evb/Kconfig.it515xx_evb new file mode 100644 index 000000000000..123837216ab8 --- /dev/null +++ b/boards/ite/it515xx_evb/Kconfig.it515xx_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT515XX_EVB + select SOC_IT51526AW diff --git a/boards/ite/it515xx_evb/board.yml b/boards/ite/it515xx_evb/board.yml new file mode 100644 index 000000000000..d4c7074979fa --- /dev/null +++ b/boards/ite/it515xx_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: it515xx_evb + full_name: IT51XXX series + vendor: ite + socs: + - name: it51526aw diff --git a/boards/ite/it515xx_evb/doc/index.rst b/boards/ite/it515xx_evb/doc/index.rst new file mode 100644 index 000000000000..cdd3ad54735b --- /dev/null +++ b/boards/ite/it515xx_evb/doc/index.rst @@ -0,0 +1,163 @@ +.. zephyr:board:: it515xx_evb + +Overview +******** + +The IT51XXX is a 32-bit RISC-V microcontroller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT51526 development board (also known as it515xx_evb) and its debug card. + +.. figure:: it515xx_evb_and_debug_card.webp + :align: center + :alt: IT51526 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT51XXX series contains different chip types(ex, it51526, it51527), +and they support different hardware features. +Listing the IT51526 hardware features as following: + +- RISC-V RV32IMC instruction set +- 4KB instruction cache size +- 128KB SRAM in total +- Built-in 32.768 kHz clock generator +- Embedded Flash, 512K/1024K-byte e-flash +- eSPI, SPI, BRAM, KBC, PECI, UART +- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG +- Support 3 Voltage Comparator +- Support Cryptographic Engine +- 9 SMBus hosts, 3 targets, with 12 SMBus channels, compatible with I2C +- I3C host: Support two I3C controllers, compliant with the MIPI I3C v1.0 SEPC. +- Two-wire serial interface up to 12.5MHz using Push-Pull. +- Support SDR, IBI, Hot-Join. +- I3C target: Support SDR, FIFO co-use DLM. Support Push-Pull output. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and debugging on it51526 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it515xx_evb to the evolution motherboard. + +#. Connect the Download Board J5 to J38(GPC1 & GPC2) on the evolution motherboard. + +#. Connect the USB to UART wire to UART0 connector on the evolution motherboard. + + .. image:: it515xx_evb_wiring.webp + :align: center + :alt: it515xx_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it515xx_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it515xx_evb | + | Connector | J38 Connector | + +=============+===============+ + | 2 | C1 | + +-------------+---------------+ + | 3 | C2 | + +-------------+---------------+ + | 4 | GND | + +-------------+---------------+ + + For USB to UART cable, connect the evolution motherboard as below: + + +-------------+---------------+ + | USB to UART | Evolution | + | cable | motherboard | + | | UART0 | + | | Connector | + +=============+===============+ + | USB | UART0 | + +-------------+---------------+ + +Building +======== + +#. Build :zephyr:code-sample:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it515xx_evb + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it515xx board flash. + +#. Flashing steps as described in the link: `Flashing steps`_. + +#. Turn on the it515xx_evb board switch, you should see ``"Hello World! it515xx_evb"`` + sent by the board. If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use the Linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it515xx_evb"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +it515xx_evb board can be debugged by connecting USB to UART. We can write commands and +read messages through minicom in the Ubuntu terminal. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it515xx_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: https://www.ite.com.tw/en +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html +.. _Flashing steps: https://docs.zephyrproject.org/latest/boards/ite/it82xx2_evb/doc/index.html#flashing diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp b/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp new file mode 100644 index 000000000000..d6d81db1aea6 Binary files /dev/null and b/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp differ diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp b/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp new file mode 100644 index 000000000000..c942044b5562 Binary files /dev/null and b/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp differ diff --git a/boards/ite/it515xx_evb/it515xx_evb.dts b/boards/ite/it515xx_evb/it515xx_evb.dts new file mode 100644 index 000000000000..926c93bd921f --- /dev/null +++ b/boards/ite/it515xx_evb/it515xx_evb.dts @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +/ { + model = "IT515XX EV-Board"; + compatible = "ite,it515xx-evb"; + + aliases { + i2c-0 = &i2c0; + led0 = &led0; + watchdog0 = &twd0; + pwm-0 = &pwm0; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &flashctrl; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_clk_gpf2_default + &i2c0_data_gpf3_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <1843200>; + pinctrl-0 = <&uart1_rx_gpc7_default + &uart1_tx_gpe6_default>; + pinctrl-names = "default"; +}; + +&ite_uart1_wrapper { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + slot1_partition: partition@20000 { + label = "image-1"; + reg = <0x00020000 DT_SIZE_K(128)>; + }; + + storage_partition: partition@40000 { + label = "storage"; + reg = <0x00040000 DT_SIZE_K(256)>; + }; + }; +}; + +&kbd { + status = "okay"; + pinctrl-0 = <&ksi0_default + &ksi1_default + &ksi2_default + &ksi3_default + &ksi4_default + &ksi5_default + &ksi6_default + &ksi7_default + &kso0_default + &kso1_default + &kso2_default + &kso3_default + &kso4_default + &kso5_default + &kso6_default + &kso7_default + &kso8_default + &kso9_default + &kso10_default + &kso11_default + &kso12_default + &kso13_default + &kso14_default + &kso15_default>; + pinctrl-names = "default"; + row-size = <8>; + col-size = <16>; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3_gpi3_default>; + pinctrl-names = "default"; +}; + +/* + * test pwm: + * If we need pwm output in ITE chip power saving mode, + * then we should set pwm output frequency <=324Hz. + */ +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* test fan */ +&pwm7 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + +/* test fan tachometer sensor */ +&tach0 { + status = "okay"; + input-pin = ; + pulses-per-round = <2>; + pinctrl-0 = <&tach0a_gpd6_default>; + pinctrl-names = "default"; +}; + +&sha256 { + status = "okay"; +}; diff --git a/boards/ite/it515xx_evb/it515xx_evb.yaml b/boards/ite/it515xx_evb/it515xx_evb.yaml new file mode 100644 index 000000000000..5ac8ab272d7e --- /dev/null +++ b/boards/ite/it515xx_evb/it515xx_evb.yaml @@ -0,0 +1,15 @@ +identifier: it515xx_evb +name: ITE IT51XXX EVB +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 128 +supported: + - flash + - gpio + - i2c + - pinctrl + - pm + - uart +vendor: ite diff --git a/boards/ite/it515xx_evb/it515xx_evb_defconfig b/boards/ite/it515xx_evb/it515xx_evb_defconfig new file mode 100644 index 000000000000..b14dac07519d --- /dev/null +++ b/boards/ite/it515xx_evb/it515xx_evb_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +# General Kernel Options +CONFIG_XIP=y + +# UART Driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console Driver +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Driver +CONFIG_GPIO=y + +# Clock Driver +CONFIG_CLOCK_CONTROL=y diff --git a/boards/ite/it82xx2_evb/Kconfig.defconfig b/boards/ite/it82xx2_evb/Kconfig.defconfig deleted file mode 100644 index a106a9d61514..000000000000 --- a/boards/ite/it82xx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT82XX2_EVB - -config INPUT - default y if KSCAN - -endif diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst index d31b989f225c..938264879b8e 100644 --- a/boards/ite/it82xx2_evb/doc/index.rst +++ b/boards/ite/it82xx2_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _it82xx2_evb: - -ITE IT82XX2 series -###################### +.. zephyr:board:: it82xx2_evb Overview ******** @@ -40,63 +37,8 @@ Listing the IT82202 hardware features as following: Supported Features ================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - FLASH - - on-chip - - flash controller - * - PINCTRL - - on-chip - - pin controller - * - ESPI - - on-chip - - espi - * - PECI - - on-chip - - peci - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - PWM - - on-chip - - pwm - * - ADC - - on-chip - - adc - * - TIMER - - on-chip - - timer - * - WATCHDOG - - on-chip - - watchdog - * - KSCAN - - on-chip - - kscan - * - SENSOR - - on-chip - - voltage comparator - * - I2C - - on-chip - - i2c - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/ite/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file. + +.. zephyr:board-supported-hw:: Programming and debugging on it82202 ************************************ diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts index 29e8ad721c88..8dc3188edc16 100644 --- a/boards/ite/it82xx2_evb/it82xx2_evb.dts +++ b/boards/ite/it82xx2_evb/it82xx2_evb.dts @@ -17,7 +17,6 @@ i2c-0 = &i2c0; peci-0 = &peci0; led0 = &led0; - kscan0 = &kscan_input; watchdog0 = &twd0; pwm-0 = &pwm0; }; @@ -30,7 +29,6 @@ zephyr,flash = &flash0; zephyr,flash-controller = &flashctrl; zephyr,code-partition = &slot0_partition; - zephyr,keyboard-scan = &kscan_input; }; leds { @@ -136,15 +134,14 @@ pinctrl-names = "default"; }; -/* pwm for test */ +/* + * pwm for test: + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ &pwm0 { status = "okay"; prescaler-cx = ; - /* - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ - pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -153,7 +150,6 @@ &pwm7 { status = "okay"; prescaler-cx = ; - pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; @@ -196,10 +192,6 @@ pinctrl-names = "default"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &peci0 { diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.yaml b/boards/ite/it82xx2_evb/it82xx2_evb.yaml index 505c2d7d9101..e4e0b9742647 100644 --- a/boards/ite/it82xx2_evb/it82xx2_evb.yaml +++ b/boards/ite/it82xx2_evb/it82xx2_evb.yaml @@ -15,7 +15,6 @@ supported: - gpio - usb_device - i2c - - kscan - pm - pwm - tach diff --git a/boards/ite/it82xx2_evb/it82xx2_evb_defconfig b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig index 2b174670d483..2a244e464eba 100644 --- a/boards/ite/it82xx2_evb/it82xx2_evb_defconfig +++ b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig @@ -18,8 +18,3 @@ CONFIG_UART_CONSOLE=y # GPIO Driver CONFIG_GPIO=y - -# Power Management -CONFIG_PM=y -CONFIG_PM_DEVICE=y -CONFIG_PM_POLICY_CUSTOM=y diff --git a/boards/ite/it8xxx2_evb/Kconfig.defconfig b/boards/ite/it8xxx2_evb/Kconfig.defconfig index 57fc0404475f..0c81c3577624 100644 --- a/boards/ite/it8xxx2_evb/Kconfig.defconfig +++ b/boards/ite/it8xxx2_evb/Kconfig.defconfig @@ -14,7 +14,4 @@ endchoice endif # PM -config INPUT - default y if KSCAN - endif # BOARD_IT8XXX2_EVB diff --git a/boards/ite/it8xxx2_evb/board.cmake b/boards/ite/it8xxx2_evb/board.cmake index 6a3abe8ddd91..a9763a8bad41 100644 --- a/boards/ite/it8xxx2_evb/board.cmake +++ b/boards/ite/it8xxx2_evb/board.cmake @@ -1,4 +1,2 @@ -set(SUPPORTED_EMU_PLATFORMS renode) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/it8xxx2_evb.resc) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst index 0e215fddf7ef..751294a77b68 100644 --- a/boards/ite/it8xxx2_evb/doc/index.rst +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _it8xxx2_evb: - -ITE IT8XXX2 series -###################### +.. zephyr:board:: it8xxx2_evb Overview ******** @@ -37,42 +34,8 @@ Listing the IT81302 hardware features as following: Supported Features ================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - TIMER - - on-chip - - timer - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - ADC - - on-chip - - adc - * - I2C - - on-chip - - i2c - * - KSCAN - - on-chip - - kscan - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file. + +.. zephyr:board-supported-hw:: Hardware reworks **************** diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts index 0ee42f981f08..2116f89b20ce 100644 --- a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts @@ -17,7 +17,6 @@ i2c-0 = &i2c0; peci-0 = &peci0; led0 = &led0; - kscan0 = &kscan_input; watchdog0 = &twd0; pwm-0 = &pwm0; }; @@ -30,7 +29,6 @@ zephyr,flash = &flash0; zephyr,flash-controller = &flashctrl; zephyr,code-partition = &slot0_partition; - zephyr,keyboard-scan = &kscan_input; }; leds { @@ -123,15 +121,14 @@ &uart2_tx_gph2_default>; pinctrl-names = "default"; }; -/* pwm for test */ +/* + * pwm for test: + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ &pwm0 { status = "okay"; prescaler-cx = ; - /* - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ - pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -139,7 +136,6 @@ &pwm7 { status = "okay"; prescaler-cx = ; - pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; @@ -180,10 +176,6 @@ pinctrl-names = "default"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &peci0 { status = "okay"; diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml index 0a57a0937f7c..31ef24d2811a 100644 --- a/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml @@ -13,7 +13,6 @@ supported: - gpio - adc - i2c - - kscan - pwm - watchdog vendor: ite diff --git a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc deleted file mode 100644 index 5ef1ae4e5bbc..000000000000 --- a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc +++ /dev/null @@ -1,17 +0,0 @@ -:name: ITE-evb -:description: This script is prepared to run Zephyr on a Mi-V RISC-V board. - -$name?="ITE-evb" - -using sysbus -mach create $name -machine LoadPlatformDescription @platforms/boards/it8xxx2_evb.repl - -showAnalyzer uart -cpu PerformanceInMips 80 - -macro reset -""" - sysbus LoadELF $elf -""" -runMacro $reset diff --git a/boards/khadas/edge2/doc/index.rst b/boards/khadas/edge2/doc/index.rst index 337ff3aa24e5..f0ac6de53f8e 100644 --- a/boards/khadas/edge2/doc/index.rst +++ b/boards/khadas/edge2/doc/index.rst @@ -17,23 +17,7 @@ See `Hardware details`_ Supported Features ================== -The ``khadas_edge2`` board target supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-600 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Synopsys DesignWare 8250 serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in (NON-SMP) -:zephyr_file:`boards/khadas/edge2/khadas_edge2_defconfig` +.. zephyr:board-supported-hw:: There are multiple serial ports on the board: Zephyr is using uart2 as serial console. @@ -41,6 +25,8 @@ uart2 as serial console. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Use the following configuration to run basic Zephyr applications and kernel tests on Khadas Edge2 board. For example, with the :zephyr:code-sample:`hello_world`: diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst index 82294c07e994..b645563e5b2a 100644 --- a/boards/khadas/edgev/doc/index.rst +++ b/boards/khadas/edgev/doc/index.rst @@ -13,23 +13,7 @@ See Supported Features ================== -Khadas Edge-V board default configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-500 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Synopsys DesignWare 8250 serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in (NON-SMP) -:zephyr_file:`boards/khadas/edgev/khadas_edgev_defconfig` +.. zephyr:board-supported-hw:: There are multiple serial ports on the board: Zephyr is using uart2 as serial console. @@ -37,6 +21,8 @@ uart2 as serial console. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Use the following configuration to run basic Zephyr applications and kernel tests on Khadas Edge-V board. For example, with the :zephyr:code-sample:`hello_world`: diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst index d88eec584c67..6a001bbfdd8e 100644 --- a/boards/kincony/kincony_kc868_a32/doc/index.rst +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -40,6 +40,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/kws/common/pico_spe-pinctrl-common.dtsi b/boards/kws/common/pico_spe-pinctrl-common.dtsi new file mode 100644 index 000000000000..bfdcff973f9f --- /dev/null +++ b/boards/kws/common/pico_spe-pinctrl-common.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 KWS Computersysteme Gmbh + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; +}; diff --git a/boards/kws/index.rst b/boards/kws/index.rst new file mode 100644 index 000000000000..0f8fc102b945 --- /dev/null +++ b/boards/kws/index.rst @@ -0,0 +1,10 @@ +.. _boards-kws: + +KWS Computersysteme Gmbh +######################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/kws/pico2_spe/Kconfig.defconfig b/boards/kws/pico2_spe/Kconfig.defconfig new file mode 100644 index 000000000000..3daadffce788 --- /dev/null +++ b/boards/kws/pico2_spe/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2025 KWS Computersysteme Gmbh +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PICO2_SPE + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_LAN865X + +config NET_IF_MAX_IPV4_COUNT + default 2 + +endif # ETH_LAN865X + +endif # NETWORKING + +endif # BOARD_PICO2_SPE diff --git a/boards/kws/pico2_spe/Kconfig.pico2_spe b/boards/kws/pico2_spe/Kconfig.pico2_spe new file mode 100644 index 000000000000..9487cc1d8101 --- /dev/null +++ b/boards/kws/pico2_spe/Kconfig.pico2_spe @@ -0,0 +1,5 @@ +# Copyright (c) 2025 KWS Computersysteme Gmbh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PICO2_SPE + select SOC_RP2350A_M33 if BOARD_PICO2_SPE_RP2350A_M33 diff --git a/boards/kws/pico2_spe/board.cmake b/boards/kws/pico2_spe/board.cmake new file mode 100644 index 000000000000..feae063129ac --- /dev/null +++ b/boards/kws/pico2_spe/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") + +board_runner_args(uf2 "--board-id=RP2350") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/kws/pico2_spe/board.yml b/boards/kws/pico2_spe/board.yml new file mode 100644 index 000000000000..e292243d1b01 --- /dev/null +++ b/boards/kws/pico2_spe/board.yml @@ -0,0 +1,6 @@ +board: + name: pico2_spe + full_name: Pico2-SPE + vendor: kws + socs: + - name: rp2350a diff --git a/boards/kws/pico2_spe/doc/img/pico2_spe.webp b/boards/kws/pico2_spe/doc/img/pico2_spe.webp new file mode 100644 index 000000000000..1cf931ddf991 Binary files /dev/null and b/boards/kws/pico2_spe/doc/img/pico2_spe.webp differ diff --git a/boards/kws/pico2_spe/doc/index.rst b/boards/kws/pico2_spe/doc/index.rst new file mode 100644 index 000000000000..09302b967add --- /dev/null +++ b/boards/kws/pico2_spe/doc/index.rst @@ -0,0 +1,70 @@ +.. zephyr:board:: pico2_spe + +Overview +******** + +The Pico2-SPE is a small, low-cost, versatile boards from +KWS Computersysteme Gmbh. They are equipped with an RP2350a SoC, an on-board LED, +a USB connector, an SWD interface. The Pico2-SPE additionally contains an +Microchip LAN8651 10Base-T1S module. The USB bootloader allows the +ability to flash without any adapter, in a drag-and-drop manner. +It is also possible to flash and debug the boards with their SWD interface, +using an external adapter. + +Hardware +******** + +- Dual Cortex-M33 or Hazard3 processors at up to 150MHz +- 520KB of SRAM, and 4MB of on-board flash memory +- USB 1.1 with device and host support +- Low-power sleep and dormant modes +- Drag-and-drop programming using mass storage over USB +- 26 multi-function GPIO pins including 3 that can be used for ADC +- 1 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels +- 2 Timer with 4 alarms, 1 AON Timer +- Temperature sensor +- Microchip LAN8651 10Base-T1S +- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support + + - Flexible, user-programmable high-speed IO + - Can emulate interfaces such as SD Card and VGA + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The default pin mapping is unchanged from the Pico-SPE. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +As with the Pico-SPE, the SWD interface can be used to program and debug the device, +e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. +Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. + +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: pico2_spe/rp2350a/m33 + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd + +References +********** + +.. _Getting Started with Pico-SPE-Series: + https://kws-computer.de/go/pico-spe-getting-started + +.. _Pico2-SPE Documentation: + https://kws-computer.de/go/pico2-spe-datasheet + +.. target-notes:: diff --git a/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi b/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi new file mode 100644 index 000000000000..889f287c642a --- /dev/null +++ b/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 KWS Computersysteme Gmbh + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../common/pico_spe-pinctrl-common.dtsi" diff --git a/boards/kws/pico2_spe/pico2_spe.dtsi b/boards/kws/pico2_spe/pico2_spe.dtsi new file mode 100644 index 000000000000..87211d91effb --- /dev/null +++ b/boards/kws/pico2_spe/pico2_spe.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2025 KWS Computersysteme Gmbh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "pico2_spe-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + }; + + pico_header: connector { + compatible = "raspberrypi,pico-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* GP0 */ + <1 0 &gpio0 1 0>, /* GP1 */ + <2 0 &gpio0 2 0>, /* GP2 */ + <3 0 &gpio0 3 0>, /* GP3 */ + <4 0 &gpio0 4 0>, /* GP4 */ + <5 0 &gpio0 5 0>, /* GP5 */ + <6 0 &gpio0 6 0>, /* GP6 */ + <7 0 &gpio0 7 0>, /* GP7 */ + <8 0 &gpio0 8 0>, /* GP8 */ + <9 0 &gpio0 9 0>, /* GP9 */ + <10 0 &gpio0 10 0>, /* GP10 */ + <11 0 &gpio0 11 0>, /* GP11 */ + <12 0 &gpio0 12 0>, /* GP12 */ + <13 0 &gpio0 13 0>, /* GP13 */ + <14 0 &gpio0 14 0>, /* GP14 */ + <15 0 &gpio0 15 0>, /* GP15 */ + <16 0 &gpio0 16 0>, /* GP16 */ + <17 0 &gpio0 17 0>, /* GP17 */ + <18 0 &gpio0 18 0>, /* GP18 */ + <19 0 &gpio0 19 0>, /* GP19 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>, /* GP21 */ + <22 0 &gpio0 22 0>, /* GP22 */ + <26 0 &gpio0 26 0>, /* GP26 */ + <27 0 &gpio0 27 0>, /* GP27 */ + <28 0 &gpio0 28 0>; /* GP28 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(4)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for an image definition block. The block is much + * smaller than 256 bytes, but in practice the linker places the vector + * table at a much larger alignment offset. + */ + image_def: partition@0 { + label = "image_def"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the image definition block. + * The partition size is 4MB minus the 0x100 bytes taken by the + * image definition. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(4) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&spi1 { + clock-frequency = ; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&pico_header 13 GPIO_ACTIVE_LOW>; + + lan8651: lan865x@0 { + compatible = "microchip,lan865x"; + reg = <0x0>; + spi-max-frequency = ; + int-gpios = <&gpio0 21 (GPIO_ACTIVE_LOW)>; + rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + + local-mac-address = [ CA 2F B7 10 23 79]; + + lan865x_mdio: lan865x_mdio { + compatible = "microchip,lan865x-mdio"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethernet-phy@0 { + compatible = "microchip,t1s-phy"; + reg = <0x0>; + plca-enable; + plca-node-id = <0>; + plca-node-count = <8>; + plca-burst-count = <0>; + plca-burst-timer = <0x80>; + plca-to-timer = <0x20>; + status = "okay"; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&timer0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +pico_serial: &uart0 {}; diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts new file mode 100644 index 000000000000..4bebd86dbd0c --- /dev/null +++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 KWS Computersysteme Gmbh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "pico2_spe.dtsi" diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml new file mode 100644 index 000000000000..acdaeafe3a6b --- /dev/null +++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml @@ -0,0 +1,20 @@ +identifier: pico2_spe/rp2350a/m33 +name: KWS Pico2 SinglePairEthernet +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig new file mode 100644 index 000000000000..8bd68e351139 --- /dev/null +++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig @@ -0,0 +1,14 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/kws/pico2_spe/support/openocd.cfg b/boards/kws/pico2_spe/support/openocd.cfg new file mode 100644 index 000000000000..82666bb53314 --- /dev/null +++ b/boards/kws/pico2_spe/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/kws/pico_spe/Kconfig b/boards/kws/pico_spe/Kconfig new file mode 100644 index 000000000000..e1a877543e64 --- /dev/null +++ b/boards/kws/pico_spe/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 KWS Computersysteme Gmbh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PICO_SPE + select RP2_FLASH_W25Q080 diff --git a/boards/kws/pico_spe/Kconfig.defconfig b/boards/kws/pico_spe/Kconfig.defconfig new file mode 100644 index 000000000000..4f5d50901633 --- /dev/null +++ b/boards/kws/pico_spe/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2024 KWS Computersysteme Gmbh +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PICO_SPE + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_LAN865X + +config NET_IF_MAX_IPV4_COUNT + default 2 + +endif # ETH_LAN865X + +endif # NETWORKING + +endif # BOARD_PICO_SPE diff --git a/boards/kws/pico_spe/Kconfig.pico_spe b/boards/kws/pico_spe/Kconfig.pico_spe new file mode 100644 index 000000000000..1ecb279b3f66 --- /dev/null +++ b/boards/kws/pico_spe/Kconfig.pico_spe @@ -0,0 +1,5 @@ +# Copyright (c) 2024 KWS Computersysteme Gmbh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PICO_SPE + select SOC_RP2040 diff --git a/boards/kws/pico_spe/board.cmake b/boards/kws/pico_spe/board.cmake new file mode 100644 index 000000000000..ff6f71a2c50a --- /dev/null +++ b/boards/kws/pico_spe/board.cmake @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This configuration allows selecting what debug adapter debugging Pico-SPE +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b pico_spe -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) \ No newline at end of file diff --git a/boards/kws/pico_spe/board.yml b/boards/kws/pico_spe/board.yml new file mode 100644 index 000000000000..5d80b878c0b3 --- /dev/null +++ b/boards/kws/pico_spe/board.yml @@ -0,0 +1,6 @@ +board: + name: pico_spe + full_name: Pico-SPE + vendor: kws + socs: + - name: rp2040 diff --git a/boards/kws/pico_spe/doc/img/pico_spe.webp b/boards/kws/pico_spe/doc/img/pico_spe.webp new file mode 100644 index 000000000000..00e143500b49 Binary files /dev/null and b/boards/kws/pico_spe/doc/img/pico_spe.webp differ diff --git a/boards/kws/pico_spe/doc/index.rst b/boards/kws/pico_spe/doc/index.rst new file mode 100644 index 000000000000..1352905638b7 --- /dev/null +++ b/boards/kws/pico_spe/doc/index.rst @@ -0,0 +1,110 @@ +.. zephyr:board:: pico_spe + +Overview +******** + +The Pico-SPE is a small, low-cost, versatile boards from +KWS Computersysteme Gmbh. They are equipped with an RP2040 SoC, an on-board LED, +a USB connector, an SWD interface. The Pico-SPE additionally contains an +Microchip LAN8651 10Base-T1S module. The USB bootloader allows the +ability to flash without any adapter, in a drag-and-drop manner. +It is also possible to flash and debug the boards with their SWD interface, +using an external adapter. + +Hardware +******** +- Dual core Arm Cortex-M0+ processor running up to 133MHz +- 264KB on-chip SRAM +- 16MB on-board QSPI flash with XIP capabilities +- 16 GPIO pins +- 3 Analog inputs +- 2 UART peripherals +- 2 I2C controllers +- 16 PWM channels +- USB 1.1 controller (host/device) +- 8 Programmable I/O (PIO) for custom peripherals +- On-board LED +- 1 Watchdog timer peripheral +- Microchip LAN8651 10Base-T1S + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Pin Mapping +=========== + +The peripherals of the RP2040 SoC can be routed to various pins on the board. +The configuration of these routes can be modified through DTS. Please refer to +the datasheet to see the possible routings for each peripheral. + +External pin mapping on the Pico-SPE is identical to the Pico, but note that internal +RP2040 GPIO lines 10, 11, 12, 13, 20, 21 are routed to the Microchip LAN8651 on the +Pico-SPE. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART0_TX : P0 +- UART0_RX : P1 +- I2C0_SDA : P4 +- I2C0_SCL : P5 +- I2C1_SDA : P6 +- I2C1_SCL : P7 +- ADC_CH0 : P26 +- ADC_CH1 : P27 +- ADC_CH2 : P28 + +Programmable I/O (PIO) +********************** +The RP2040 SoC comes with two PIO periherals. These are two simple +co-processors that are designed for I/O operations. The PIOs run +a custom instruction set, generated from a custom assembly language. +PIO programs are assembled using :command:`pioasm`, a tool provided by Raspberry Pi. + +Zephyr does not (currently) assemble PIO programs. Rather, they should be +manually assembled and embedded in source code. An example of how this is done +can be found at :zephyr_file:`drivers/serial/uart_rpi_pico_pio.c`. + +Sample: SPI via PIO +==================== + +The :zephyr:code-sample:`bme280` sample includes a +demonstration of using the PIO SPI driver to communicate with an +environmental sensor. The PIO SPI driver supports using any +combination of GPIO pins for an SPI bus, as well as allowing up to +four independent SPI buses on a single board (using the two SPI +devices as well as both PIO devices). + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The SWD interface can be used to program and debug the device, +e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. +Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. + +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: pico_spe + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd + +.. target-notes:: + +.. _pico_setup.sh: + https://raw.githubusercontent.com/raspberrypi/pico-setup/master/pico_setup.sh + +.. _Getting Started with Pico-SPE-Series: + https://kws-computer.de/go/pico-spe-getting-started + +.. _Pico-SPE Documentation: + https://kws-computer.de/go/pico-spe-datasheet diff --git a/boards/kws/pico_spe/pico_spe-pinctrl.dtsi b/boards/kws/pico_spe/pico_spe-pinctrl.dtsi new file mode 100644 index 000000000000..ba6d29bb19b9 --- /dev/null +++ b/boards/kws/pico_spe/pico_spe-pinctrl.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 KWS Computersysteme Gmbh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../common/pico_spe-pinctrl-common.dtsi" diff --git a/boards/kws/pico_spe/pico_spe.dts b/boards/kws/pico_spe/pico_spe.dts new file mode 100644 index 000000000000..5a4e89ead581 --- /dev/null +++ b/boards/kws/pico_spe/pico_spe.dts @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2024 KWS Computersysteme Gmbh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "pico_spe-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "LED"; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + + pwm_led0: pwm_led_0 { + pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + rtc = &rtc; + watchdog0 = &wdt0; + }; + + pico_header: connector { + compatible = "raspberrypi,pico-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* GP0 */ + <1 0 &gpio0 1 0>, /* GP1 */ + <2 0 &gpio0 2 0>, /* GP2 */ + <3 0 &gpio0 3 0>, /* GP3 */ + <4 0 &gpio0 4 0>, /* GP4 */ + <5 0 &gpio0 5 0>, /* GP5 */ + <6 0 &gpio0 6 0>, /* GP6 */ + <7 0 &gpio0 7 0>, /* GP7 */ + <8 0 &gpio0 8 0>, /* GP8 */ + <9 0 &gpio0 9 0>, /* GP9 */ + <10 0 &gpio0 10 0>, /* GP10 */ + <11 0 &gpio0 11 0>, /* GP11 */ + <12 0 &gpio0 12 0>, /* GP12 */ + <13 0 &gpio0 13 0>, /* GP13 */ + <14 0 &gpio0 14 0>, /* GP14 */ + <15 0 &gpio0 15 0>, /* GP15 */ + <16 0 &gpio0 16 0>, /* GP16 */ + <17 0 &gpio0 17 0>, /* GP17 */ + <18 0 &gpio0 18 0>, /* GP18 */ + <19 0 &gpio0 19 0>, /* GP19 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>, /* GP21 */ + <22 0 &gpio0 22 0>, /* GP22 */ + <26 0 &gpio0 26 0>, /* GP26 */ + <27 0 &gpio0 27 0>, /* GP27 */ + <28 0 &gpio0 28 0>; /* GP28 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = ; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "disabled"; + clock-frequency = ; +}; + +&spi1 { + clock-frequency = ; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&pico_header 13 GPIO_ACTIVE_LOW>; + + lan8651: lan865x@0 { + compatible = "microchip,lan865x"; + reg = <0x0>; + spi-max-frequency = ; + int-gpios = <&gpio0 21 (GPIO_ACTIVE_LOW)>; + rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + local-mac-address = [ CA 2F B7 10 23 78]; + + lan865x_mdio: lan865x_mdio { + compatible = "microchip,lan865x-mdio"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethernet-phy@0 { + compatible = "microchip,t1s-phy"; + reg = <0x0>; + plca-enable; + plca-node-id = <0>; + plca-node-count = <8>; + plca-burst-count = <0>; + plca-burst-timer = <0x80>; + plca-to-timer = <0x20>; + status = "okay"; + }; + }; + }; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>; + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +pico_spi: &spi1 {}; +pico_i2c0: &i2c0 {}; +pico_i2c1: &i2c1 {}; +pico_serial: &uart0 {}; diff --git a/boards/kws/pico_spe/pico_spe.yaml b/boards/kws/pico_spe/pico_spe.yaml new file mode 100644 index 000000000000..c0b383270f57 --- /dev/null +++ b/boards/kws/pico_spe/pico_spe.yaml @@ -0,0 +1,23 @@ +identifier: pico_spe +name: KWS Pico SinglePairEthernet +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - counter + - clock diff --git a/boards/kws/pico_spe/pico_spe_defconfig b/boards/kws/pico_spe/pico_spe_defconfig new file mode 100644 index 000000000000..df003531af9c --- /dev/null +++ b/boards/kws/pico_spe/pico_spe_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/kws/pico_spe/support/openocd.cfg b/boards/kws/pico_spe/support/openocd.cfg new file mode 100644 index 000000000000..34ab592b1861 --- /dev/null +++ b/boards/kws/pico_spe/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/lilygo/tdongle_s3/Kconfig b/boards/lilygo/tdongle_s3/Kconfig new file mode 100644 index 000000000000..2da6bfecb7c9 --- /dev/null +++ b/boards/lilygo/tdongle_s3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TDONGLE_S3_ESP32S3_PROCPU + default 256 if BOARD_TDONGLE_S3_ESP32S3_APPCPU diff --git a/boards/lilygo/tdongle_s3/Kconfig.sysbuild b/boards/lilygo/tdongle_s3/Kconfig.sysbuild new file mode 100644 index 000000000000..420778b68b24 --- /dev/null +++ b/boards/lilygo/tdongle_s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3 b/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3 new file mode 100644 index 000000000000..12f013272e00 --- /dev/null +++ b/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3 @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TDONGLE_S3 + select SOC_ESP32S3_WROOM_N16R8 + select SOC_ESP32S3_PROCPU if BOARD_TDONGLE_S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_TDONGLE_S3_ESP32S3_APPCPU diff --git a/boards/lilygo/tdongle_s3/board.cmake b/boards/lilygo/tdongle_s3/board.cmake new file mode 100644 index 000000000000..57d1a920ecd3 --- /dev/null +++ b/boards/lilygo/tdongle_s3/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/tdongle_s3/board.yml b/boards/lilygo/tdongle_s3/board.yml new file mode 100644 index 000000000000..ad92d0100c94 --- /dev/null +++ b/boards/lilygo/tdongle_s3/board.yml @@ -0,0 +1,6 @@ +board: + name: tdongle_s3 + full_name: T-Dongle S3 + vendor: lilygo + socs: + - name: esp32s3 diff --git a/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp b/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp new file mode 100644 index 000000000000..b970f6b1b8d9 Binary files /dev/null and b/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp differ diff --git a/boards/lilygo/tdongle_s3/doc/index.rst b/boards/lilygo/tdongle_s3/doc/index.rst new file mode 100644 index 000000000000..b90f5a214172 --- /dev/null +++ b/boards/lilygo/tdongle_s3/doc/index.rst @@ -0,0 +1,189 @@ +.. zephyr:board:: tdongle_s3 + +Overview +******** + +Lilygo T-Dongle S3 is an IoT mini development board based on the +Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. + +It features the following integrated components: + +- ESP32-S3 chip (240MHz dual core, Bluetooth 5, WiFi) +- On-board antenna and IPEX connector +- USB-A connector with integrated TF Card slot +- MX 1.25mm 2-pin battery connector +- APA102 RGB LED +- JST SH 1.0mm 4-pin UART connector +- Transparent plastic case + +Functional Description +********************** +This board is based on the ESP32-S3 with 16MB of flash, WiFi and BLE support. It +has an USB-A port for programming and debugging, integrated battery charging +and an on-board antenna. The fitted U.FL external antenna connector can be +enabled by moving a 0-ohm resistor. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Start Application Development +***************************** + +Before powering up your Lilygo T-Dongle T8-S3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Simple boot +=========== + +The board could be loaded using a single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code-block:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes it possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: tdongle_s3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flashed at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: tdongle_s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``tdongle_s3`` board target. +Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: tdongle_s3/esp32s3/procpu + :goals: flash + +The default baud rate for the Lilygo T-Dongle S3 is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! tdongle_s3/esp32s3/procpu + +References +********** + +.. target-notes:: + +.. _`Lilygo T-Dongle S3 schematic`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/shcematic/T-Dongle-S3.pdf +.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3.git +.. _`ESP32-S3 Datasheet`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/doc/esp32-s3_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/doc/esp32-s3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/lilygo/tdongle_s3/support/openocd.cfg b/boards/lilygo/tdongle_s3/support/openocd.cfg new file mode 100644 index 000000000000..0b2c4909fe0e --- /dev/null +++ b/boards/lilygo/tdongle_s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32s3.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi b/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi new file mode 100644 index 000000000000..a4bff2af2d28 --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2025 Stefan Golinschi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + }; + + sdhc0_default: sdhc0_default { + group1 { + pinmux = , + , + , + , + , + ; + bias-pull-up; + output-high; + }; + }; +}; diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts new file mode 100644 index 000000000000..2d2422e11a9e --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2025 Stefan Golinschi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "TDONGLE S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml new file mode 100644 index 000000000000..b9bea7145c3e --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: tdongle_s3/esp32s3/appcpu +name: LILYGO T-DONGLE S3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: lilygo diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig new file mode 100644 index 000000000000..6087787aad3d --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts new file mode 100644 index 000000000000..d325c30273b8 --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts @@ -0,0 +1,160 @@ +/* + * Copyright 2025 Stefan Golinschi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "tdongle_s3-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "TDONGLE S3 PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + watchdog0 = &wdt0; + sdhc0 = &sdhc0; + uart-0 = &uart0; + sw0 = &button0; + led-strip = &apa102; + }; + + chosen { + zephyr,sram = &sram0; + /* console can be UART or USB CDC */ + /* zephyr,console = &uart0; */ + /* zephyr,shell-uart = &uart0; */ + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7735r; + zephyr,sdhc = &sdhc0; + }; + + buttons { + compatible = "gpio-keys"; + status = "okay"; + + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + /* Enable D/C line for 4wire mode */ + dc-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + spi-dev = <&spi2>; + #address-cells = <1>; + #size-cells = <0>; + write-only; + status = "okay"; + + st7735r: st7735r@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = <20000000>; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + reg = <0>; + width = <160>; + height = <80>; + inversion-on; + rgb-is-inverted; + madctl = <0xBE>; + x-offset = <1>; + y-offset = <26>; + gamctrp1 = [02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10]; + gamctrn1 = [03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; + te-delay = <0x0A>; + vmctr1 = <0x0E>; + colmod = <0x05>; + caset = [00 02 00 81]; + raset = [00 01 00 A0]; + status = "okay"; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + clock-frequency = <20000000>; + status = "okay"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + clock-frequency = <20000000>; + status = "okay"; + + apa102: apa102@0 { + compatible = "apa,apa102"; + reg = <0>; + spi-max-frequency = <24000000>; + chain-length = <1>; + color-mapping = ; + status = "okay"; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&sdhc { + sdhc0: sdhc@0 { + pinctrl-0 = <&sdhc0_default>; + pinctrl-names = "default"; + power-delay-ms = <100>; + max-bus-freq = <52000000>; + bus-width = <4>; + status = "okay"; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; + }; +}; diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml new file mode 100644 index 000000000000..5b01812a0bfd --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: tdongle_s3/esp32s3/procpu +name: TDONGLE S3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - i2s + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input + - video + - display +vendor: lilygo diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig b/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig new file mode 100644 index 000000000000..fbb8fd6b9109 --- /dev/null +++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Stefan Golinschi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst index fa6613d7414d..1b662bb030c3 100644 --- a/boards/lilygo/ttgo_lora32/doc/index.rst +++ b/boards/lilygo/ttgo_lora32/doc/index.rst @@ -15,39 +15,13 @@ It's available in two versions supporting two different frequency ranges and fea Some of the ESP32 I/O pins are accessible on the board's pin headers. -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the Lilygo TTGO LoRa32 board. - -.. _SX127x: https://www.semtech.com/products/wireless-rf/lora-connect/sx1276#documentation -.. _ESP32-PICO-D4: https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf -.. _SSD1306: https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf - -+------------------+-------------------------------------------------------------------------+ -| Key Component | Description | -+==================+=========================================================================+ -| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | -| | functionalities and integrates a 4-MB SPI flash. | -+------------------+-------------------------------------------------------------------------+ -| Diagnostic LED | One user LED connected to the GPIO pin. | -+------------------+-------------------------------------------------------------------------+ -| USB Port | USB interface. Power supply for the board as well as the | -| | serial communication interface between a computer and the board. | -| | Micro-USB type connector. | -+------------------+-------------------------------------------------------------------------+ -| Power Switch | Sliding power switch. | -+------------------+-------------------------------------------------------------------------+ -| OLED display | Built-in OLED display \(`SSD1306`_, 0.96", 128x64 px\) controlled | -| | by I2C interface | -+------------------+-------------------------------------------------------------------------+ -| SX1276/SX1278 | LoRa radio frontend chip, connected via SPI. | -| | Use SX1276 for 433MHz and SX1276 for 868/915/923MHz. | -+------------------+-------------------------------------------------------------------------+ -| TF card slot | TF card slot wired to the SDHC interface of the MCU. | -+------------------+-------------------------------------------------------------------------+ +Hardware +******** + +Supported Features +================== +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -61,7 +35,7 @@ System requirements Prerequisites ============= -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command below to retrieve those files. .. code-block:: console @@ -75,10 +49,12 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== -The board could be loaded using the single binary image, without 2nd stage bootloader. +The board could be loaded using a single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration. .. note:: @@ -108,7 +84,7 @@ There are two options to be used when building an application: Sysbuild ======== -The sysbuild makes possible to build and flash all necessary images needed to +The sysbuild makes it possible to build and flash all necessary images needed to bootstrap the board with the ESP32-PICO-D4 SoC. To build the sample application using sysbuild use the command: @@ -193,7 +169,7 @@ message in the monitor: .. code-block:: console ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! ttgo_lora32 + Hello World! ttgo_lora32/esp32/procpu Code samples ============ @@ -218,3 +194,5 @@ Related Documents - `ESP32-PICO-D4 Datasheet `_ (PDF) - `ESP32 Datasheet `_ (PDF) - `ESP32 Hardware Reference `_ +- `SX127x Datasheet `_ +- `SSD1306 Datasheet `_ (PDF) diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts index 6ae0dbeb0152..42c3391f387d 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts @@ -148,3 +148,7 @@ }; }; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_t7v1_5/doc/index.rst b/boards/lilygo/ttgo_t7v1_5/doc/index.rst index 13f5107cd80e..57d12645c9ae 100644 --- a/boards/lilygo/ttgo_t7v1_5/doc/index.rst +++ b/boards/lilygo/ttgo_t7v1_5/doc/index.rst @@ -13,38 +13,17 @@ It features the following integrated components: - JST GH 2-pin battery connector - LED -Functional Description -********************** +Hardware +******** + This board is based on the ESP32-WROVER-E module with 4MB of flash (there are models 16MB as well), WiFi and BLE support. It has a Micro-USB port for programming and debugging, integrated battery charging and an on-board antenna. -Connections and IOs -=================== +Supported Features +================== -The ``ttgo_t7v1_5/esp32/procpu`` board target supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| CPU | ESP32 | arch/xtensa | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| LoRa | SX1276 | lora_sx127x | -+-----------+------------+------------------+ -| WiFi | on-chip | wifi_esp32 | -+-----------+------------+------------------+ -| BLE | on-chip | bluetooth_esp32 | -+-----------+------------+------------------+ -| Flash | on-chip | flash_esp32 | -+-----------+------------+------------------+ +.. zephyr:board-supported-hw:: System requirements ******************* @@ -52,7 +31,7 @@ System requirements Prerequisites ============= -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command below to retrieve those files. .. code-block:: console @@ -66,10 +45,12 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== -The board could be loaded using the single binary image, without 2nd stage bootloader. +The board could be loaded using a single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration. .. note:: @@ -80,7 +61,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -92,14 +73,14 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - .. code:: cfg + .. code-block:: cfg CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== -The sysbuild makes possible to build and flash all necessary images needed to +The sysbuild makes it possible to build and flash all necessary images needed to bootstrap the board with the ESP32 SoC. To build the sample application using sysbuild use the command: @@ -142,7 +123,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst index 4179528b6af5..33cab6415243 100644 --- a/boards/lilygo/ttgo_t8c3/doc/index.rst +++ b/boards/lilygo/ttgo_t8c3/doc/index.rst @@ -14,39 +14,18 @@ It features the following integrated components: - JST GH 2-pin battery connector - LED -Functional Description -********************** +Hardware +******** + This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It has an USB-C port for programming and debugging, integrated battery charging and an on-board antenna. The fitted U.FL external antenna connector can be enabled by moving a 0-ohm resistor. -Connections and IOs -=================== +Supported Features +================== -The ``ttgo_t8c3`` board target supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -60,7 +39,7 @@ System requirements Prerequisites ============= -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command below to retrieve those files. .. code-block:: console @@ -74,10 +53,12 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== -The board could be loaded using the single binary image, without 2nd stage bootloader. +The board could be loaded using a single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration. .. note:: @@ -107,7 +88,7 @@ There are two options to be used when building an application: Sysbuild ======== -The sysbuild makes possible to build and flash all necessary images needed to +The sysbuild makes it possible to build and flash all necessary images needed to bootstrap the board with the ESP32-C3 SoC. To build the sample application using sysbuild use the command: diff --git a/boards/lilygo/ttgo_t8s3/doc/index.rst b/boards/lilygo/ttgo_t8s3/doc/index.rst index 09455ed19a60..fb29b2e5f7b6 100644 --- a/boards/lilygo/ttgo_t8s3/doc/index.rst +++ b/boards/lilygo/ttgo_t8s3/doc/index.rst @@ -15,51 +15,18 @@ It features the following integrated components: - JST SH 1.0mm 4-pin UART connector - SD card slot -Functional Description -********************** +Hardware +******** + This board is based on the ESP32-S3 with 16MB of flash, WiFi and BLE support. It has an USB-C port for programming and debugging, integrated battery charging and an on-board antenna. The fitted U.FL external antenna connector can be enabled by moving a 0-ohm resistor. -Connections and IOs -=================== - -The ``ttgo_t8s3`` board target supports the following hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi, sdmmc | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ +Supported Features +================== + +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -73,7 +40,7 @@ System requirements Prerequisites ============= -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command below to retrieve those files. .. code-block:: console @@ -87,10 +54,12 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== -The board could be loaded using the single binary image, without 2nd stage bootloader. +The board could be loaded using a single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration. .. note:: @@ -120,7 +89,7 @@ There are two options to be used when building an application: Sysbuild ======== -The sysbuild makes possible to build and flash all necessary images needed to +The sysbuild makes it possible to build and flash all necessary images needed to bootstrap the board with the ESP32 SoC. To build the sample application using sysbuild use the command: diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts index a034a9cb49a4..0bc8b8470922 100644 --- a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts @@ -144,3 +144,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_tbeam/Kconfig b/boards/lilygo/ttgo_tbeam/Kconfig new file mode 100644 index 000000000000..c95a97a11aa2 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TTGO_TBEAM_ESP32_PROCPU + default 256 if BOARD_TTGO_TBEAM_ESP32_APPCPU + +config GNSS_INIT_PRIORITY + default 87 diff --git a/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild b/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild new file mode 100644 index 000000000000..3a2d17ac5cfd --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam b/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam new file mode 100644 index 000000000000..3b3202cf8e42 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_TBEAM + select SOC_ESP32_PICO_D4 + select SOC_ESP32_PROCPU if BOARD_TTGO_TBEAM_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_TTGO_TBEAM_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_tbeam/board.cmake b/boards/lilygo/ttgo_tbeam/board.cmake new file mode 100644 index 000000000000..91b3caa2c75d --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +# the default ESP32 baud rate is not supported +board_runner_args(esp32 "--esp-baud-rate=1500000") diff --git a/boards/lilygo/ttgo_tbeam/board.yml b/boards/lilygo/ttgo_tbeam/board.yml new file mode 100644 index 000000000000..fad0e34cdcad --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/board.yml @@ -0,0 +1,6 @@ +board: + name: ttgo_tbeam + full_name: TTGO TBeam + vendor: lilygo + socs: + - name: esp32 diff --git a/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp b/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp new file mode 100644 index 000000000000..eb488921e4a5 Binary files /dev/null and b/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp differ diff --git a/boards/lilygo/ttgo_tbeam/doc/index.rst b/boards/lilygo/ttgo_tbeam/doc/index.rst new file mode 100644 index 000000000000..fa6082abaa29 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/doc/index.rst @@ -0,0 +1,204 @@ +.. zephyr:board:: ttgo_tbeam + +Overview +******** + +The Lilygo TTGO TBeam, is an ESP32-based development board for LoRa applications. + +It's available in two versions supporting two different frequency ranges and features the following integrated components: + +- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- SSD1306, 128x64 px, 0.96" screen (optional) +- SX1278 (433MHz) or SX1276 (868/915/923MHz) LoRa radio frontend (optional, with SMA or IPEX connector) +- NEO-6M or NEO-M8N GNSS module +- X-Powers AXP2101 PMIC +- JST GH 2-pin battery connector +- 18650 Li-Ion battery clip + +Some of the ESP32 I/O pins are accessible on the board's pin headers. + +Hardware +******** + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Start Application Development +***************************** + +Before powering up your Lilygo TTGO TBeam, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Simple boot +=========== + +The board could be loaded using a single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code-block:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes it possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-PICO-D4 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ttgo_tbeam/esp32/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-PICO-D4 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_tbeam/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``ttgo_tbeam`` board target. +Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_tbeam/esp32/procpu + :goals: flash + +The default baud rate for the Lilygo TTGO TBeam is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_tbeam/esp32/procpu + +Code samples +============ + +The following sample applications will work out of the box with this board: + +* :zephyr:code-sample:`lora-send` +* :zephyr:code-sample:`lora-receive` +* :zephyr:code-sample:`gnss` +* :zephyr:code-sample:`wifi-shell` +* :zephyr:code-sample:`character-frame-buffer` +* :zephyr:code-sample:`blinky` + +Debugging +********* + +Lilygo TTGO TBeam debugging is not supported due to pinout limitations. + +Related Documents +***************** +- `Lilygo TTGO TBeam schematic `_ (PDF) +- `Lilygo TTGO TBeam documentation `_ +- `Lilygo github repo `_ +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ +- `SX127x Datasheet `_ +- `SSD1306 Datasheet `_ (PDF) +- `NEO-6M Datasheet `_ (PDF) +- `NEO-N8M Datasheet `_ (PDF) diff --git a/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg b/boards/lilygo/ttgo_tbeam/support/openocd.cfg similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/support/openocd.cfg rename to boards/lilygo/ttgo_tbeam/support/openocd.cfg diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi b/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi new file mode 100644 index 000000000000..a8a93a72bf8f --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts new file mode 100644 index 000000000000..3547f3e351ae --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "TTGO TBeam APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml new file mode 100644 index 000000000000..8eca6127690f --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml @@ -0,0 +1,28 @@ +identifier: ttgo_tbeam/esp32/appcpu +name: TTGO TBeam APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp + - gnss +vendor: lilygo diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig new file mode 100644 index 000000000000..48546641cadd --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts new file mode 100644 index 000000000000..88deaae04d21 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "ttgo_tbeam-pinctrl.dtsi" +#include +#include + +/ { + model = "TTGO TBeam PROCPU"; + compatible = "lilygo,ttgo-tbeam"; + + aliases { + led0 = &red_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + lora0 = &lora0; + gnss = &gnss; + regulator0 = &axp2101; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ssd1306_128x64; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "Red - LED0"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <9600>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + + gnss: gnss-nmea-generic { + compatible = "gnss-nmea-generic"; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + ssd1306_128x64: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + width = <128>; + height = <64>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <63>; + segment-remap; + com-invdir; + prechargep = <0x22>; + }; + + axp2101: axp2101@34 { + status = "okay"; + reg = <0x34>; + compatible = "x-powers,axp2101"; + regulator { + compatible = "x-powers,axp2101-regulator"; + + vdd_mcu: DCDC1 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_lora: ALDO2 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gnss: ALDO3 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + }; + + charger: charger { + compatible = "x-powers,axp2101-charger"; + charge-term-current-microamp = <25000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4200000>; + }; + + fuel_gauge: fuel_gauge { + compatible = "x-powers,axp2101-fuel-gauge"; + }; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + + lora0: lora@0 { + compatible = "semtech,sx1276"; + reg = <0>; + reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + dio-gpios = + /* SX1276 D0 -> GPIO26 */ + <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO33 */ + <&gpio1 1 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D2 -> GPIO32 */ + <&gpio1 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + spi-max-frequency = <1000000>; + power-amplifier-output = "pa-boost"; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml new file mode 100644 index 000000000000..6d2fe9c703a5 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml @@ -0,0 +1,22 @@ +identifier: ttgo_tbeam/esp32/procpu +name: TTGO TBeam PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - display + - lora + - nvs + - gnss +testing: + ignore_tags: + - net + - bluetooth +vendor: lilygo diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig new file mode 100644 index 000000000000..6b1097cdb389 --- /dev/null +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +CONFIG_GPIO=y +CONFIG_MFD=y +CONFIG_REGULATOR=y diff --git a/boards/lilygo/ttgo_toiplus/Kconfig b/boards/lilygo/ttgo_toiplus/Kconfig new file mode 100644 index 000000000000..c6a99b1032dc --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild b/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild new file mode 100644 index 000000000000..3a2d17ac5cfd --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus b/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus new file mode 100644 index 000000000000..ddca709de7ad --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus @@ -0,0 +1,5 @@ +# Copyright 2025 aisuneko icecat +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_TOIPLUS + select SOC_ESP32C3_FN4 diff --git a/boards/lilygo/ttgo_toiplus/board.cmake b/boards/lilygo/ttgo_toiplus/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/ttgo_toiplus/board.yml b/boards/lilygo/ttgo_toiplus/board.yml new file mode 100644 index 000000000000..e5295b2bec22 --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/board.yml @@ -0,0 +1,6 @@ +board: + name: ttgo_toiplus + full_name: TTGO T-OI-PLUS + vendor: lilygo + socs: + - name: esp32c3 diff --git a/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp b/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp new file mode 100644 index 000000000000..115cc04fa29f Binary files /dev/null and b/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp differ diff --git a/boards/lilygo/ttgo_toiplus/doc/index.rst b/boards/lilygo/ttgo_toiplus/doc/index.rst new file mode 100644 index 000000000000..3ea6b50446fa --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/doc/index.rst @@ -0,0 +1,199 @@ +.. zephyr:board:: ttgo_toiplus + +Overview +******** + +Lilygo TTGO T-OI-PLUS is an mini IoT development board based on +Espressif's ESP32-C3 WiFi/Bluetooth dual-mode chip. + +It features the following integrated components: + +- ESP32-C3 SoC (RISC-V 160MHz single core, 400KB SRAM, Wi-Fi, Bluetooth) +- on board Grove connector +- USB-C connector for power and communication (on board serial) +- optional 18340 Li-ion battery holder +- LED + +Functional Description +********************** +This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an Grove connector. + +Connections and IOs +=================== + +.. zephyr:board-supported-hw:: + +(Note: the above UART interface also supports connecting through USB.) + +Start Application Development +***************************** + +Before powering up your Lilygo TTGO T-OI-PLUS, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-C3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ttgo_toiplus + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-C3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_toiplus + :goals: build + +The usual ``flash`` target will work with the ``ttgo_toiplus`` board target. +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_toiplus + :goals: flash + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_toiplus + +Sample applications +=================== + +The following samples will run out of the box on the TTGO T-OI-PLUS board. + +To build the blinky sample: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/basic/blinky + :board: ttgo_toiplus + :goals: build + +To build the bluetooth beacon sample: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/bluetooth/beacon + :board: ttgo_toiplus + :goals: build + + +Related Documents +***************** +.. _`Lilygo TTGO T-OI-PLUS schematic`: https://github.com/Xinyuan-LilyGO/LilyGo-T-OI-PLUS/blob/main/schematic/T-OI_PLUS_Schematic.pdf +.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGO +.. _`Espressif ESP32-C3 datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`Espressif ESP32-C3 technical reference manual`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/lilygo/ttgo_toiplus/support/openocd.cfg b/boards/lilygo/ttgo_toiplus/support/openocd.cfg new file mode 100644 index 000000000000..02754ff2a73c --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/support/openocd.cfg @@ -0,0 +1,6 @@ +set ESP_RTOS none + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32c3.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi b/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi new file mode 100644 index 000000000000..874d3c94639b --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + + /* GPIO6 is CS */ + + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts new file mode 100644 index 000000000000..6db7d4c16e6f --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2025 aisuneko icecat + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ttgo_toiplus-pinctrl.dtsi" +#include + +/ { + model = "Lilygo TTGO T-OI-PLUS"; + compatible = "lilygo,ttgo-toiplus"; + + aliases { + led0 = &green_led; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,canbus = &twai; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + label = "Green - LED0"; + }; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&twai { + status = "okay"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&wifi { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml new file mode 100644 index 000000000000..746472787cb2 --- /dev/null +++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml @@ -0,0 +1,14 @@ +identifier: ttgo_toiplus +name: TTGO T-OI-PLUS +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - uart + - watchdog + - can +vendor: lilygo diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig b/boards/lilygo/ttgo_toiplus/ttgo_toiplus_defconfig similarity index 100% rename from boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig rename to boards/lilygo/ttgo_toiplus/ttgo_toiplus_defconfig diff --git a/boards/lilygo/twatch_s3/Kconfig b/boards/lilygo/twatch_s3/Kconfig new file mode 100644 index 000000000000..8d5a48cfc2c6 --- /dev/null +++ b/boards/lilygo/twatch_s3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 BayLibre SAS +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TWATCH_S3_ESP32S3_PROCPU + default 256 if BOARD_TWATCH_S3_ESP32S3_APPCPU diff --git a/boards/lilygo/twatch_s3/Kconfig.defconfig b/boards/lilygo/twatch_s3/Kconfig.defconfig new file mode 100644 index 000000000000..f7e4f32af392 --- /dev/null +++ b/boards/lilygo/twatch_s3/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright 2025 BayLibre SAS +# SPDX-License-Identifier: Apache-2.0 + +if DISPLAY + +choice ST7789V_PIXEL_FORMAT + default ST7789V_BGR565 +endchoice + +if LVGL + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY diff --git a/boards/lilygo/twatch_s3/Kconfig.sysbuild b/boards/lilygo/twatch_s3/Kconfig.sysbuild new file mode 100644 index 000000000000..7d37de9b1aab --- /dev/null +++ b/boards/lilygo/twatch_s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 BayLibre SAS +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/twatch_s3/Kconfig.twatch_s3 b/boards/lilygo/twatch_s3/Kconfig.twatch_s3 new file mode 100644 index 000000000000..338ccb6bec90 --- /dev/null +++ b/boards/lilygo/twatch_s3/Kconfig.twatch_s3 @@ -0,0 +1,7 @@ +# Copyright 2025 BayLibre SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TWATCH_S3 + select SOC_ESP32S3_WROOM_N16R8 + select SOC_ESP32S3_PROCPU if BOARD_TWATCH_S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_TWATCH_S3_ESP32S3_APPCPU diff --git a/boards/lilygo/twatch_s3/board.cmake b/boards/lilygo/twatch_s3/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/lilygo/twatch_s3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/twatch_s3/board.yml b/boards/lilygo/twatch_s3/board.yml new file mode 100644 index 000000000000..e894af0d251c --- /dev/null +++ b/boards/lilygo/twatch_s3/board.yml @@ -0,0 +1,6 @@ +board: + name: twatch_s3 + full_name: T-Watch S3 + vendor: lilygo + socs: + - name: esp32s3 diff --git a/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp b/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp new file mode 100644 index 000000000000..b79ef6813171 Binary files /dev/null and b/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp differ diff --git a/boards/lilygo/twatch_s3/doc/index.rst b/boards/lilygo/twatch_s3/doc/index.rst new file mode 100644 index 000000000000..3dc07e37673e --- /dev/null +++ b/boards/lilygo/twatch_s3/doc/index.rst @@ -0,0 +1,198 @@ +.. zephyr:board:: twatch_s3 + +Overview +******** + +LILYGO T-Watch S3 is an ESP32-S3 based smartwatch with the following features: + +- ESP32-S3-R8 chip + + - Dual core Xtensa LX-7 up to 240MHz + - 8 MB of integrated PSRAM + - Bluetooth LE v5.0 + - Wi-Fi 802.11 b/g/n + +- 16 MB external QSPI flash (Winbond W25Q128JWPIQ) +- Power Management Unit (X-Powers AXP2101) which provides + + - Regulators (DC-DCs and LDOs) + - Battery charging + - Fuel gauge + +- 470 mAh battery +- RTC (NXP PCF8563) +- Haptic (Texas Instruments DRV2605) +- Accelerometer (Bosch BMA423) +- 240x240 pixels LCD with touchscreen + + - ST7789V LCD Controller + - Focaltech FT5336 touch sensor + +- Microphone (Knowles SPM1423HM4H-B) +- LoRA radio (Semtech SX1262) +- Audio amplifier (Maxim MAX98357A) + +The board features a single micro USB connector which can be used for serial +flashing, debugging and console thanks to the integrated JTAG support in the +chip. + +It does not have any GPIO that can easily be connected to something external. +There is only 1 physical button which is connected to the PMU and it's used +to turn on/off the device. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Simple boot +=========== + +The board could be loaded using a single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code-block:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes it possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild, use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: twatch_s3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-built and re-flashed + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly as possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flashed at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twatch_s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``twatch_s3`` board target +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twatch_s3/esp32s3/procpu + :goals: flash + +The default baud rate is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! twatch_s3/esp32s3/procpu + +References +********** + +.. target-notes:: + +.. _`Lilygo Twatch S3 schematic`: https://github.com/Xinyuan-LilyGO/TTGO_TWatch_Library/blob/t-watch-s3/schematic/T_WATCH_S3.pdf +.. _`Lilygo T-Watch S3 repo`: https://github.com/Xinyuan-LilyGO/TTGO_TWatch_Library/tree/t-watch-s3 +.. _`Lilygo T-Watch Deps repo`: https://github.com/Xinyuan-LilyGO/T-Watch-Deps +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/lilygo/twatch_s3/support/openocd.cfg b/boards/lilygo/twatch_s3/support/openocd.cfg new file mode 100644 index 000000000000..0b2c4909fe0e --- /dev/null +++ b/boards/lilygo/twatch_s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32s3.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi b/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi new file mode 100644 index 000000000000..b62a16f797a8 --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + ledc0_default: ledc0_default { + group1 { + pinmux = ; + output-enable; + }; + }; +}; diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts b/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts new file mode 100644 index 000000000000..35d19fc17b1c --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "T-Watch S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(16)>; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml b/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml new file mode 100644 index 000000000000..e834a090c9fc --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: twatch_s3/esp32s3/appcpu +name: T-Watch S3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: lilygo diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig b/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig new file mode 100644 index 000000000000..48546641cadd --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu.dts b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts new file mode 100644 index 000000000000..b78676a8b0a0 --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2025 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "twatch_s3-pinctrl.dtsi" +#include +#include + +/ { + model = "T-Watch S3 PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + i2c-1 = &i2c1; + watchdog0 = &wdt0; + rtc = &pfc8563_rtc; + pwm-led0 = &backlight_pwm; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v; + zephyr,touch = &ft5336; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + reg = <0>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <80>; + mdac = <0xc8>; + ram-param = [00 e0]; + colmod = <0x55>; + porch-param = [0c 0c 00 33 33]; + gctrl = <0x35>; + vcom = <0x28>; + lcm = <0x0c>; + vrhs = <0x10>; + vdvs = <0x20>; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + /* Values below are not set by the eTFT_SPI driver from + * LilyGO. Therefore let's keep ST7789V values. + */ + gamma = <0x01>; + cmd2en-param = [5a 69 02 00]; + rgb-param = [40 02 14]; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + backlight_pwm: pwm_0 { + label = "LCD backlight PWM"; + pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + swap-xy; + }; +}; + +&ledc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + + channel0@0 { + reg = <0x0>; + timer = <0>; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + pfc8563_rtc: pfc8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; + + bma423: bma423@19 { + compatible = "bosch,bma4xx"; + reg = <0x19>; + status = "okay"; + int1-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + haptic: drv2605@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + status = "okay"; + actuator-mode = "ERM"; + }; + + axp2101@34 { + compatible = "x-powers,axp2101"; + reg = <0x34>; + + charger { + compatible = "x-powers,axp2101-charger"; + constant-charge-current-max-microamp = <300000>; + constant-charge-voltage-max-microvolt = <4200000>; + charge-term-current-microamp = <100000>; + vbackup-enable; + }; + + regulators { + compatible = "x-powers,axp2101-regulator"; + + dcdc1 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + dcdc2 { + regulator-boot-off; + }; + + dcdc3 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + dcdc4 { + regulator-boot-off; + }; + + dcdc5 { + regulator-boot-off; + }; + + aldo1 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + aldo3 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + aldo4 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + bldo1 { + regulator-boot-off; + }; + + bldo2 { + regulator-min-microvolt = <3300000>; + regulator-init-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + cplusldo { + regulator-boot-off; + }; + + dldo1 { + regulator-boot-off; + }; + + dldo2 { + regulator-boot-off; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; + + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(16)>; +}; + +&timer0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml b/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml new file mode 100644 index 000000000000..975c4750ac09 --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml @@ -0,0 +1,19 @@ +identifier: twatch_s3/esp32s3/procpu +name: T-Watch S3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma + - input + - video + - rtc +vendor: lilygo diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig b/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig new file mode 100644 index 000000000000..d8fbaa879257 --- /dev/null +++ b/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lowrisc/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst index b91c0700def2..bfc13c121816 100644 --- a/boards/lowrisc/opentitan_earlgrey/doc/index.rst +++ b/boards/lowrisc/opentitan_earlgrey/doc/index.rst @@ -1,7 +1,4 @@ -.. _opentitan_earlgrey: - -OpenTitan Earl Grey -################### +.. zephyr:board:: opentitan_earlgrey Overview ******** @@ -51,6 +48,8 @@ Other hardware features are not yet supported on Zephyr porting. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + First, build and install Verilator as described in the `OpenTitan Verilator Setup`_ guide . diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index f000b61f3162..1b0a13b77dfe 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -96,3 +96,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi index 43ee4b452646..fc3c57e1b9f0 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi @@ -107,3 +107,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_atom_lite/doc/index.rst b/boards/m5stack/m5stack_atom_lite/doc/index.rst index 87e56a236774..9b84f801fd6f 100644 --- a/boards/m5stack/m5stack_atom_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atom_lite/doc/index.rst @@ -16,39 +16,7 @@ It features the following integrated components: Supported Features ================== -The Zephyr m5stack_atom_lite board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -76,6 +44,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts index 012c2b1f8fe7..226b1d1a0040 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts @@ -147,3 +147,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst index 1b863cb08be5..9cedbfb51805 100644 --- a/boards/m5stack/m5stack_atoms3/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -18,39 +18,7 @@ It features the following integrated components: Supported Features ================== -The Zephyr m5stack_atoms3 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -78,6 +46,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts index ed9634074074..bb81fbbb39ff 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts @@ -158,3 +158,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst index 23af62d96e67..8403358be1e4 100644 --- a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -16,39 +16,7 @@ It features the following integrated components: Supported Features ================== -The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -76,6 +44,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts index c5884a846a15..60bc3d6429a2 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts @@ -117,3 +117,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig index c90a78870ba0..1999b90c5b8d 100644 --- a/boards/m5stack/m5stack_core2/Kconfig.defconfig +++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig @@ -14,7 +14,7 @@ config GPIO_HOGS_INIT_PRIORITY config MFD_INIT_PRIORITY default 70 -config REGULATOR_AXP192_INIT_PRIORITY +config REGULATOR_AXP192_AXP2101_INIT_PRIORITY default 71 config GPIO_AXP192_INIT_PRIORITY diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 9855ef1de599..fb21227767c4 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -104,39 +104,7 @@ These voltages can be controlled via regulator api. Supported Features ================== -The Zephyr m5stack_core2 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - +.. zephyr:board-supported-hw:: Start Application Development ***************************** @@ -164,6 +132,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 554e1885488e..172fb1c6c5df 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -87,8 +87,7 @@ }; &psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "disabled"; + size = ; }; &uart0 { @@ -191,7 +190,7 @@ ft5336_touch: ft5336@38 { compatible = "focaltech,ft5336"; reg = <0x38>; - int-gpios = <&gpio1 7 0>; + int-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; }; @@ -253,3 +252,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig index 22e46419ab62..0fcad2e5e26d 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig @@ -1,11 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 - CONFIG_GPIO=y - CONFIG_REGULATOR=y - CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/m5stack/m5stack_cores3/doc/index.rst b/boards/m5stack/m5stack_cores3/doc/index.rst index d9025e3f6d8a..2fdd042c38e6 100644 --- a/boards/m5stack/m5stack_cores3/doc/index.rst +++ b/boards/m5stack/m5stack_cores3/doc/index.rst @@ -52,6 +52,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts index 1def598cdec7..5a579251bb65 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts @@ -30,3 +30,20 @@ reg = <0x10>; }; }; + +®ulator { + vddcam_3v3: ALDO3 { + regulator-min-microvolt = <3000000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3500000>; + regulator-boot-on; + status = "okay"; + }; + + avdd: BLDO1 { + regulator-min-microvolt = <2700000>; + /* regulator-init-microvolt = <2800000>; */ + regulator-max-microvolt = <3300000>; + status = "okay"; + }; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi index 1f0bf306dfca..1d4fd8c4a6f1 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi @@ -31,6 +31,7 @@ watchdog0 = &wdt0; rtc = &bm8563_rtc; sdhc0 = &sd0; + led0 = &axp2101_led; }; lvgl_pointer { @@ -78,6 +79,94 @@ pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; + axp2101@34 { + compatible = "x-powers,axp2101"; + reg = <0x34>; + status = "okay"; + + regulator: regulator { + compatible = "x-powers,axp2101-regulator"; + status = "okay"; + + /* + * Typically, no initialization is performed since non-volatile + * values are used. + * If you remove the commenting, initialization will be performed + * with the default value. + */ + + vdd_3v3: DCDC1 { + regulator-min-microvolt = <3000000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; + + vcc_3v3: DCDC3 { + regulator-min-microvolt = <3100000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3500000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; + + vdd_1v8: ALDO1 { + regulator-min-microvolt = <1700000>; + /* regulator-init-microvolt = <1800000>; */ + regulator-max-microvolt = <1900000>; + regulator-boot-on; + status = "okay"; + }; + + vdda_3v3: ALDO2 { + regulator-min-microvolt = <3100000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3500000>; + regulator-boot-on; + status = "okay"; + }; + + vdd_3v3_sd: ALDO4 { + regulator-min-microvolt = <3100000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3500000>; + regulator-boot-on; + status = "okay"; + }; + + dvdd: BLDO2 { + regulator-min-microvolt = <3100000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3500000>; + status = "okay"; + }; + + vcc_bl: DLDO1 { + regulator-min-microvolt = <2500000>; + /* regulator-init-microvolt = <3300000>; */ + regulator-max-microvolt = <3300000>; + regulator-boot-on; + status = "okay"; + }; + }; + + charger: charger { + compatible = "x-powers,axp2101-charger"; + constant-charge-current-max-microamp = <200000>; + constant-charge-voltage-max-microvolt = <4200000>; + charge-term-current-microamp = <125000>; + }; + + axp2101_led: led { + compatible = "x-powers,axp2101-led"; + status = "okay"; + x-powers,mode = "by-reg"; + }; + }; + bm8563_rtc: bm8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -156,3 +245,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst index 3762fd49b1cb..4e006eca8a39 100644 --- a/boards/m5stack/m5stack_stamps3/doc/index.rst +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -134,6 +134,8 @@ below to retrieve those files. Building & Flashing ------------------- +.. zephyr:board-supported-runners:: + Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts index f2733a571954..d2aa01fa61c7 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts @@ -156,3 +156,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig index 86819dba82d3..9399c4d1f328 100644 --- a/boards/m5stack/m5stickc_plus/Kconfig.defconfig +++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig @@ -11,7 +11,7 @@ config GPIO_HOGS_INIT_PRIORITY config MFD_INIT_PRIORITY default 70 -config REGULATOR_AXP192_INIT_PRIORITY +config REGULATOR_AXP192_AXP2101_INIT_PRIORITY default 71 config GPIO_AXP192_INIT_PRIORITY diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst index f40e21fbd5e6..e6e65a3e1d8f 100644 --- a/boards/m5stack/m5stickc_plus/doc/index.rst +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -84,6 +84,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts index 6b1a2dd8ba21..2a85c2c0353d 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts @@ -218,3 +218,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst index a953b595b2c7..704bacc6cad9 100644 --- a/boards/m5stack/stamp_c3/doc/index.rst +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -11,30 +11,7 @@ For more details see the `M5Stack STAMP-C3`_ page. Supported Features ================== -The STAMP-C3 board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ - +.. zephyr:board-supported-hw:: Prerequisites ************* @@ -53,6 +30,8 @@ below to retrieve those files. Building & Flashing ******************* +.. zephyr:board-supported-runners:: + Simple boot =========== diff --git a/boards/m5stack/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts index cbd3a3fdd92d..800ae9f36c05 100644 --- a/boards/m5stack/stamp_c3/stamp_c3.dts +++ b/boards/m5stack/stamp_c3/stamp_c3.dts @@ -96,3 +96,7 @@ &esp32_bt_hci { status = "okay"; }; + +&wifi { + status = "okay"; +}; diff --git a/boards/madmachine/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst index 7c1b985fc701..c717db21baa9 100644 --- a/boards/madmachine/mm_feather/doc/index.rst +++ b/boards/madmachine/mm_feather/doc/index.rst @@ -44,33 +44,7 @@ Hardware Supported Features ================== -The mm_feather board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | I2S | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -166,8 +140,10 @@ The Swift ID is not the same as the Zephyr driver ID. +-----------+---------------+----------+---------------+----------+---------------+ -Programming and Flash -************************* +Programming and Flashing +************************ + +.. zephyr:board-supported-runners:: Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index 0b655edd1c29..cd398cc5234f 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -56,14 +56,17 @@ &flexspi { + status = "okay"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; }; }; @@ -170,6 +173,12 @@ pinctrl-2 = <&pinmux_usdhc1_med>; pinctrl-3 = <&pinmux_usdhc1_fast>; pinctrl-names = "default", "slow", "med", "fast"; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; }; &edma0 { diff --git a/boards/madmachine/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml index a4541bc88a83..dfd28db8b7ac 100644 --- a/boards/madmachine/mm_feather/mm_feather.yaml +++ b/boards/madmachine/mm_feather/mm_feather.yaml @@ -22,4 +22,3 @@ supported: - uart - pwm - spi -vendor: nxp diff --git a/boards/madmachine/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst index 6845fa1fa360..80cff7d6c96f 100644 --- a/boards/madmachine/mm_swiftio/doc/index.rst +++ b/boards/madmachine/mm_swiftio/doc/index.rst @@ -26,31 +26,7 @@ Hardware Supported Features ================== -The mm_swiftio board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -166,10 +142,12 @@ The Swift ID is not the same as the Zephyr driver ID. +-----------+---------------+----------+---------------+----------+---------------+ -Programming and Flash -************************* +Programming and Flashing +************************ + +.. zephyr:board-supported-runners:: -Build applications as usual (see :ref:`build_an_application` for more details). +Build applications as usual (see :ref:`build_an_application` for more details). Configuring a Debug Probe ========================= diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index cbdf85c3c12e..54ad772396c5 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -56,14 +56,17 @@ &flexspi { + status = "okay"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; }; }; diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml index dbd5b79b7b63..fa4ad27a5c6b 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.yaml +++ b/boards/madmachine/mm_swiftio/mm_swiftio.yaml @@ -16,4 +16,3 @@ flash: 8192 supported: - counter - sdhc -vendor: nxp diff --git a/boards/makerbase/mks_canable_v20/doc/index.rst b/boards/makerbase/mks_canable_v20/doc/index.rst index 0a86e6fa6fcc..abc27df5189e 100644 --- a/boards/makerbase/mks_canable_v20/doc/index.rst +++ b/boards/makerbase/mks_canable_v20/doc/index.rst @@ -30,27 +30,7 @@ More information about STM32G431KB can be found here: Supported Features ================== -The Zephyr ``mks_canable_v20`` board target supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| USB | on-chip | universal-serial-bus | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FDCAN | on-chip | can | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig` - +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -84,6 +64,8 @@ The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + MKS CANable V2.0 board includes an SWDIO debug connector header J4. .. note:: diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/board.cmake b/boards/makerdiary/nrf52840_mdk_usb_dongle/board.cmake index 1f43fd93827b..895ec1a36bd9 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/board.cmake +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/board.cmake @@ -2,6 +2,7 @@ board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst index ac4743c77488..83b5621bee84 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst @@ -3,24 +3,40 @@ Overview ******** -The nRF52840 MDK USB Dongle is a small and low-cost development platform enabled -by the nRF5240 multiprotocol SoC in a convenient USB dongle form factor. +The nRF52840 MDK USB Dongle is a small and low-cost development platform +enabled by the nRF52840 multiprotocol SoC in a convenient USB dongle +form factor. -The design features a programmable user button, RGB LED, up to 12 GPIOs and 2.4G -Chip antenna on board. It can be used as a low-cost -Bluetooth5/Tread/802.15.4/ANT/2.4GHz multiprotocol node or development -board. Alternatively the USB Dongle can be used as a Network Co-Processor(NCP) -with a simple connection to a PC or other USB enabled device. +Hardware +******** + +The design features: + +* Programmable user button +* RGB LED +* Up to 12 GPIOs +* 2.4 GHz chip antenna -See `nrf52840-mdk-usb-dongle website`_ for more information about the development -board and `nRF52840 website`_ for the official reference on the IC itself. +The USB Dongle can be used as: +* A low-cost Bluetooth 5/Thread/802.15.4/ANT/2.4GHz multiprotocol node +* A development board +* A Network Co-Processor (NCP) with a simple connection to a PC or other USB enabled device + +For more information: + +* See the `nrf52840-mdk-usb-dongle website`_ for details about the development board +* See the `nRF52840 website`_ for the official reference on the IC itself +* See the `nrf52840-mdk-usb-dongle pinout diagram`_ for details about the pin usage of the board References ********** + .. target-notes:: .. _nRF52840 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52840 .. _nrf52840-mdk-usb-dongle website: https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle/ +.. _nrf52840-mdk-usb-dongle pinout diagram: + https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle/assets/attachments/nrf52840-mdk-usb-dongle-pinout_v1_1.pdf diff --git a/boards/mediatek/mt8186/afe-mt8186.dts b/boards/mediatek/mt8186/afe-mt8186.dts index c4d16826b81d..e6bd2ac557cc 100644 --- a/boards/mediatek/mt8186/afe-mt8186.dts +++ b/boards/mediatek/mt8186/afe-mt8186.dts @@ -1,7 +1,7 @@ afe_dl1: afe_dl1 { compatible = "mediatek,afe"; - afe_name = "DL1"; - dai_id = <0>; + afe-name = "DL1"; + dai-id = <0>; downlink; base = <0x11210050 0x11210054>; cur = <0x11210058 0x1121005c>; @@ -14,8 +14,8 @@ afe_dl2: afe_dl2 { compatible = "mediatek,afe"; - afe_name = "DL2"; - dai_id = <1>; + afe-name = "DL2"; + dai-id = <1>; downlink; base = <0x1121006c 0x11210070>; cur = <0x11210074 0x11210078>; @@ -28,22 +28,22 @@ afe_ul1: afe_ul1 { compatible = "mediatek,afe"; - afe_name = "UL1"; - dai_id = <2>; + afe-name = "UL1"; + dai-id = <2>; base = <0x11210378 0x1121037c>; cur = <0x11210380 0x11210384>; end = <0x11210388 0x1121038c>; fs = <0x11210374 24 4>; mono = <0x11210374 8 1>; - quad_ch = <0x11210374 11 1>; + quad-ch = <0x11210374 11 1>; enable = <0x11210010 31 1>; hd = <0x11210374 0 1>; }; afe_ul2: afe_ul2 { compatible = "mediatek,afe"; - afe_name = "UL2"; - dai_id = <3>; + afe-name = "UL2"; + dai-id = <3>; base = <0x11210860 0x11210864>; cur = <0x11210868 0x1121086c>; end = <0x11210870 0x11210874>; diff --git a/boards/mediatek/mt8188/afe-mt8188.dts b/boards/mediatek/mt8188/afe-mt8188.dts index 41daf54f62c7..fbe47f5a2b4d 100644 --- a/boards/mediatek/mt8188/afe-mt8188.dts +++ b/boards/mediatek/mt8188/afe-mt8188.dts @@ -1,7 +1,7 @@ afe_dl2: afe_dl2 { compatible = "mediatek,afe"; - afe_name = "DL2"; - dai_id = <0>; + afe-name = "DL2"; + dai-id = <0>; downlink; base = <0x00000000 0x10b11250>; cur = <0x00000000 0x10b11254>; @@ -11,14 +11,14 @@ hd = <0x10b1125c 5 1>; msb = <0x10b1192c 18 1>; msb2 = <0x10b11930 18 1>; - agent_disable = <0x10b10014 18 1>; - ch_num = <0x10b1125c 0 5>; + agent-disable = <0x10b10014 18 1>; + ch-num = <0x10b1125c 0 5>; }; afe_dl3: afe_dl3 { compatible = "mediatek,afe"; - afe_name = "DL3"; - dai_id = <1>; + afe-name = "DL3"; + dai-id = <1>; downlink; base = <0x00000000 0x10b11260>; cur = <0x00000000 0x10b11264>; @@ -28,40 +28,40 @@ hd = <0x10b1126c 5 1>; msb = <0x10b1192c 19 1>; msb2 = <0x10b11930 19 1>; - agent_disable = <0x10b10014 19 1>; - ch_num = <0x10b1126c 0 5>; + agent-disable = <0x10b10014 19 1>; + ch-num = <0x10b1126c 0 5>; }; afe_ul4: afe_ul4 { compatible = "mediatek,afe"; - afe_name = "UL4"; - dai_id = <2>; + afe-name = "UL4"; + dai-id = <2>; base = <0x00000000 0x10b11330>; cur = <0x00000000 0x10b11334>; end = <0x00000000 0x10b11338>; fs = <0x10b115a8 15 5>; mono = <0x10b1133c 1 1>; - int_odd = <0x10b1133c 0 1>; + int-odd = <0x10b1133c 0 1>; enable = <0x10b11200 4 1>; hd = <0x10b1133c 5 1>; msb = <0x10b1192c 3 1>; msb2 = <0x10b11930 3 1>; - agent_disable = <0x10b10014 3 1>; + agent-disable = <0x10b10014 3 1>; }; afe_ul5: afe_ul5 { compatible = "mediatek,afe"; - afe_name = "UL5"; - dai_id = <3>; + afe-name = "UL5"; + dai-id = <3>; base = <0x00000000 0x10b11340>; cur = <0x00000000 0x10b11344>; end = <0x00000000 0x10b11348>; fs = <0x10b115a8 20 5>; mono = <0x10b1134c 1 1>; - int_odd = <0x10b1134c 0 1>; + int-odd = <0x10b1134c 0 1>; enable = <0x10b11200 5 1>; hd = <0x10b1134c 5 1>; msb = <0x10b1192c 4 1>; msb2 = <0x10b11930 4 1>; - agent_disable = <0x10b10014 4 1>; + agent-disable = <0x10b10014 4 1>; }; diff --git a/boards/mediatek/mt8195/afe-mt8195.dts b/boards/mediatek/mt8195/afe-mt8195.dts index f51f1a783e36..37b335754df4 100644 --- a/boards/mediatek/mt8195/afe-mt8195.dts +++ b/boards/mediatek/mt8195/afe-mt8195.dts @@ -1,7 +1,7 @@ afe_dl2: afe_dl2 { compatible = "mediatek,afe"; - afe_name = "DL2"; - dai_id = <0>; + afe-name = "DL2"; + dai-id = <0>; downlink; base = <0x00000000 0x10891250>; cur = <0x00000000 0x10891254>; @@ -11,14 +11,14 @@ hd = <0x1089125c 5 1>; msb = <0x1089192c 18 1>; msb2 = <0x10891930 18 1>; - agent_disable = <0x10890014 18 1>; - ch_num = <0x1089125c 0 5>; + agent-disable = <0x10890014 18 1>; + ch-num = <0x1089125c 0 5>; }; afe_dl3: afe_dl3 { compatible = "mediatek,afe"; - afe_name = "DL3"; - dai_id = <1>; + afe-name = "DL3"; + dai-id = <1>; downlink; base = <0x00000000 0x10891260>; cur = <0x00000000 0x10891264>; @@ -28,14 +28,14 @@ hd = <0x1089126c 5 1>; msb = <0x1089192c 19 1>; msb2 = <0x10891930 19 1>; - agent_disable = <0x10890014 19 1>; - ch_num = <0x1089126c 0 5>; + agent-disable = <0x10890014 19 1>; + ch-num = <0x1089126c 0 5>; }; afe_ul4: afe_ul4 { compatible = "mediatek,afe"; - afe_name = "UL4"; - dai_id = <2>; + afe-name = "UL4"; + dai-id = <2>; base = <0x00000000 0x10891330>; cur = <0x00000000 0x10891334>; end = <0x00000000 0x10891338>; @@ -45,13 +45,13 @@ hd = <0x1089133c 5 1>; msb = <0x1089192c 3 1>; msb2 = <0x10891930 3 1>; - agent_disable = <0x10890014 3 1>; + agent-disable = <0x10890014 3 1>; }; afe_ul5: afe_ul5 { compatible = "mediatek,afe"; - afe_name = "UL5"; - dai_id = <3>; + afe-name = "UL5"; + dai-id = <3>; base = <0x00000000 0x10891340>; cur = <0x00000000 0x10891344>; end = <0x00000000 0x10891348>; @@ -61,5 +61,5 @@ hd = <0x1089134c 5 1>; msb = <0x1089192c 4 1>; msb2 = <0x10891930 4 1>; - agent_disable = <0x10890014 4 1>; + agent-disable = <0x10890014 4 1>; }; diff --git a/boards/mediatek/mt8196/afe-mt8196.dts b/boards/mediatek/mt8196/afe-mt8196.dts index fba314a61e37..a28d9f658e16 100644 --- a/boards/mediatek/mt8196/afe-mt8196.dts +++ b/boards/mediatek/mt8196/afe-mt8196.dts @@ -1,7 +1,7 @@ afe_dl1: afe_dl1 { compatible = "mediatek,afe"; - afe_name = "DL1"; - dai_id = <1>; + afe-name = "DL1"; + dai-id = <1>; downlink; base = <0x1a114470 0x1a114474>; cur = <0x1a114478 0x1a11447c>; @@ -14,8 +14,8 @@ afe_dl_24ch: afe_dl_24ch { compatible = "mediatek,afe"; - afe_name = "DL_24CH"; - dai_id = <0>; + afe-name = "DL_24CH"; + dai-id = <0>; downlink; base = <0x1a114620 0x1a114624>; cur = <0x1a114628 0x1a11462c>; @@ -23,13 +23,13 @@ fs = <0x1a114640 8 5>; enable = <0x1a114640 31 1>; hd = <0x1a114640 0 1>; - ch_num = <0x1a114640 24 6>; + ch-num = <0x1a114640 24 6>; }; afe_ul0: afe_ul0 { compatible = "mediatek,afe"; - afe_name = "UL0"; - dai_id = <2>; + afe-name = "UL0"; + dai-id = <2>; base = <0x1a114d60 0x1a114d64>; cur = <0x1a114d68 0x1a114d6c>; end = <0x1a114d70 0x1a114d74>; @@ -41,8 +41,8 @@ afe_ul1: afe_ul1 { compatible = "mediatek,afe"; - afe_name = "UL1"; - dai_id = <3>; + afe-name = "UL1"; + dai-id = <3>; base = <0x1a114d90 0x1a114d94>; cur = <0x1a114d98 0x1a114d9c>; end = <0x1a114da0 0x1a114da4>; @@ -54,8 +54,8 @@ afe_ul2: afe_ul2 { compatible = "mediatek,afe"; - afe_name = "UL2"; - dai_id = <4>; + afe-name = "UL2"; + dai-id = <4>; base = <0x1a114dc0 0x1a114dc4>; cur = <0x1a114dc8 0x1a114dcc>; end = <0x1a114dd0 0x1a114dd4>; diff --git a/boards/microchip/ev11l78a/doc/index.rst b/boards/microchip/ev11l78a/doc/index.rst index 95d05add0c0e..15661123062a 100644 --- a/boards/microchip/ev11l78a/doc/index.rst +++ b/boards/microchip/ev11l78a/doc/index.rst @@ -20,51 +20,10 @@ Hardware Supported Features ================== -The ev11l78a board configuration supports the following hardware -features: - - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. +.. zephyr:board-supported-hw:: Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram. -The default configuration can be found in the Kconfig -:zephyr_file:`boards/microchip/ev11l78a/ev11l78a_defconfig`. - Serial Port =========== diff --git a/boards/microchip/m2gl025_miv/doc/index.rst b/boards/microchip/m2gl025_miv/doc/index.rst index 88a4fa2b9512..d48d0bebcab3 100644 --- a/boards/microchip/m2gl025_miv/doc/index.rst +++ b/boards/microchip/m2gl025_miv/doc/index.rst @@ -11,6 +11,8 @@ More information can be found on Programming and debugging ************************* +.. zephyr:board-supported-runners:: + Building ======== diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig index 0ca8a90ad484..0b7eb516d7e8 100644 --- a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig @@ -3,40 +3,11 @@ if BOARD_MEC1501MODULAR_ASSY6885 -config INPUT - default y if KSCAN - #PS/2 driver is compiled in terms of this flag. config ESPI_PERIPHERAL_8042_KBC default y depends on ESPI_XEC -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - if ESPI config ESPI_PERIPHERAL_UART_SOC_MAPPING @@ -44,6 +15,4 @@ config ESPI_PERIPHERAL_UART_SOC_MAPPING endif # ESPI -endif # RTOS_TIMER - endif # BOARD_MEC1501MODULAR_ASSY6885 diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst index 910ba104da13..8a65f8713603 100644 --- a/boards/microchip/mec1501modular_assy6885/doc/index.rst +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -45,44 +45,7 @@ For more information about the SOC please see the `MEC152x Reference Manual`_ Supported Features ================== -The mec1501modular_assy6885 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ESPI | on-chip | espi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RTOS | on-chip | timer | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PS2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig` -Kconfig file. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -225,6 +188,8 @@ Jumper location map Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Setup ===== diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts index c259a7a44cdc..7c5c131cf52a 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts @@ -17,7 +17,6 @@ zephyr,sram = &sram0; zephyr,console = &uart1; zephyr,flash = &flash0; - zephyr,keyboard-scan = &kscan_input; }; aliases { @@ -26,7 +25,6 @@ i2c0 = &i2c_smb_0; i2c1 = &i2c_smb_1; - kscan0 = &kscan_input; watchdog0 = &wdog; }; }; @@ -70,9 +68,9 @@ &espi0 { status = "okay"; - io_girq = <19>; - vw_girqs = <24 25>; - pc_girq = <15>; + io-girq = <19>; + vw-girqs = <24 25>; + pc-girq = <15>; pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066 &espi_alert_n_gpio063 &espi_clk_gpio065 &espi_io0_gpio070 &espi_io1_gpio071 @@ -120,10 +118,6 @@ pinctrl-names = "default", "sleep"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &peci0 { diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml index d78477f825f4..da7c46a8a545 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml @@ -21,6 +21,5 @@ supported: - i2c - pwm - watchdog - - kscan - tach vendor: microchip diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig index 3039d18174eb..164cb7182e76 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig @@ -7,12 +7,9 @@ # Make sure external power management setup is as indicated in documentation CONFIG_SOC_MEC1501_VTR3_1_8V=y CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n -CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y - -CONFIG_PM=y diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig index 229ba41dff77..01a7081bcf41 100644 --- a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig @@ -3,40 +3,8 @@ if BOARD_MEC15XXEVB_ASSY6853 -config INPUT - default y if KSCAN - config ESPI_XEC default y depends on ESPI -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - endif # BOARD_MEC15XXEVB_ASSY6853 diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst index c712d74b563d..9a3c9e22aeb2 100644 --- a/boards/microchip/mec15xxevb_assy6853/doc/index.rst +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -42,38 +42,7 @@ For more information about the SOC's please see `MEC152x Reference Manual`_ Supported Features ================== -The mec15xxevb_assy6853 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ - - - - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -233,6 +202,8 @@ in reference section below. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Setup ===== #. If you use Dediprog SF100 programmer, then setup it. diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index 161536c867de..fbc1aa677af0 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -16,7 +16,6 @@ zephyr,sram = &sram0; zephyr,console = &uart2; zephyr,flash = &flash0; - zephyr,keyboard-scan = &kscan_input; }; aliases { @@ -29,7 +28,6 @@ i2c-0 = &i2c_smb_0; i2c1 = &i2c_smb_1; i2c7 = &i2c_smb_2; - kscan0 = &kscan_input; watchdog0 = &wdog; }; @@ -123,9 +121,9 @@ &espi0 { status = "okay"; - io_girq = <19>; - vw_girqs = <24 25>; - pc_girq = <15>; + io-girq = <19>; + vw-girqs = <24 25>; + pc-girq = <15>; pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066 &espi_alert_n_gpio063 &espi_clk_gpio065 &espi_io0_gpio070 &espi_io1_gpio071 @@ -177,10 +175,6 @@ pinctrl-names = "default", "sleep"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &peci0 { @@ -192,8 +186,8 @@ &spi0 { status = "okay"; - port_sel = <0>; - chip_select = <0>; + port-sel = <0>; + chip-select = <0>; lines = <1>; pinctrl-0 = < &shd_cs0_n_gpio055 &shd_clk_gpio056 diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml index 8b8190d20d81..afd985cb020b 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml @@ -21,5 +21,4 @@ supported: - i2c - pwm - watchdog - - kscan vendor: microchip diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig index 51e8498df60e..731a1c2d63fe 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig @@ -5,13 +5,9 @@ # CONFIG_SOC_MEC1501_VTR3_1_8V=y -CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y - -# power management stuff -CONFIG_PM=y diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig deleted file mode 100644 index 2c93b83e744d..000000000000 --- a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XEVB_ASSY6906 - -config INPUT - default y if KSCAN - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst index 0671beb41436..b05c4d5bd3ff 100644 --- a/boards/microchip/mec172xevb_assy6906/doc/index.rst +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -36,37 +36,7 @@ For more information about the SOC's please see `MEC172x Reference Manual`_ Supported Features ================== -The mec172xevb_assy6906 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ -| RPMFAN | on-chip | Fan speed controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -260,6 +230,8 @@ NOTE: ``JP121 3-4`` on base board also needs to be loaded. Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Setup ===== diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts index 076e84eda600..bc2ad391664a 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -233,10 +233,6 @@ pinctrl-names = "default", "sleep"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &ksi0_gpio017 { diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig index d1aeaeaac581..f2b72ae4282f 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_RTOS_TIMER=y - CONFIG_CLOCK_CONTROL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt index 92626f6319fb..6e36ea0dec8e 100644 --- a/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt +++ b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -zephyr_library() - #Allow users to pre-specify the tool using '-DMEC172X_SPI_GEN=/toolname' if (NOT DEFINED MEC172X_SPI_GEN) set(MEC172X_SPI_GEN $ENV{MEC172X_SPI_GEN}) diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig deleted file mode 100644 index c3487f561e99..000000000000 --- a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2022 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XMODULAR_ASSY6930 - -config INPUT - default y if KSCAN - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XMODULAR_ASSY6930 diff --git a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index a6bc75fc8fb8..18441232c41f 100644 --- a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -46,36 +46,7 @@ The board is powered through the +5V USB micro-A connector or from the MECC conn Supported Features ================== -The mec172xmodular_assy6930 (Rev. B) board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ -| RPMFAN | on-chip | Fan speed controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file. +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -150,6 +121,8 @@ or Master Attached Flash (MAF). Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Setup ===== diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts index 24d600dd0404..e5d7e888baac 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts @@ -211,10 +211,6 @@ pinctrl-names = "default", "sleep"; row-size = <8>; col-size = <16>; - - kscan_input: kscan-input { - compatible = "zephyr,kscan-input"; - }; }; &ksi0_gpio017 { diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig index c191b0b1555e..ec6ae819151f 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_RTOS_TIMER=y - CONFIG_CLOCK_CONTROL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/microchip/mec_assy6941/CMakeLists.txt b/boards/microchip/mec_assy6941/CMakeLists.txt new file mode 100644 index 000000000000..84b859f1f176 --- /dev/null +++ b/boards/microchip/mec_assy6941/CMakeLists.txt @@ -0,0 +1,59 @@ +# +# Copyright (c) 2025 Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_SERIES_MEC174X) + set(PART_PREFIX mec174x) +elseif(CONFIG_SOC_SERIES_MEC175X) + set(PART_PREFIX mec175x) +else() + message(NOTICE "Unknown SoC series! No SPI image will be generated") +endif() + +if(DEFINED ENV{MEC5_SPI_GEN}) + # Grab it from environment variable if defined + set(MEC5_SPI_GEN $ENV{MEC5_SPI_GEN}) +else() + # Else find the tool in PATH + if(CMAKE_HOST_APPLE) + # CMAKE_HOST_UNIX is also true for Apple, + # but there is no tool for Apple. So + # we need to skip it. + message(NOTICE "There is no SPI image generation tool for MacOS.") + elseif(CMAKE_HOST_UNIX) + set(MEC5_SPI_GEN_FILENAME ${PART_PREFIX}_spi_gen_linux_x86_64) + elseif(CMAKE_HOST_WIN32) + set(MEC5_SPI_GEN_FILENAME ${PART_PREFIX}_spi_gen.exe) + endif() + + find_file(MEC5_SPI_GEN_FINDFILE ${MEC5_SPI_GEN_FILENAME}) + if(MEC5_SPI_GEN_FINDFILE STREQUAL MEC5_SPI_GEN_FINDFILE-NOTFOUND) + message(WARNING "Microchip SPI Image Generation tool (${MEC5_SPI_GEN_FILENAME}) is not available. SPI Image will not be generated.") + else() + set(MEC5_SPI_GEN ${MEC5_SPI_GEN_FINDFILE}) + endif() + + unset(MEC5_SPI_GEN_FINDFILE) + unset(MEC5_SPI_GEN_FILENAME) +endif() + +if(DEFINED MEC5_SPI_GEN) + if(DEFINED ENV{MEC5_SPI_CFG}) + set(MEC5_SPI_CFG $ENV{MEC5_SPI_CFG}) + else() + set(MEC5_SPI_CFG ${BOARD_DIR}/support/${PART_PREFIX}_spi_cfg.txt) + endif() + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${MEC5_SPI_GEN} + -i ${MEC5_SPI_CFG} + -o ${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME} + ) + + unset(MEC5_SPI_GEN) + unset(MEC5_SPI_CFG) +endif() + +unset(PART_PREFIX) diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 new file mode 100644 index 000000000000..85a094ac8d1d --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941 + select SOC_MEC1743_QLJ if BOARD_MEC_ASSY6941_MEC1743_QLJ + select SOC_MEC1743_QSZ if BOARD_MEC_ASSY6941_MEC1743_QSZ + select SOC_MEC1753_QLJ if BOARD_MEC_ASSY6941_MEC1753_QLJ + select SOC_MEC1753_QSZ if BOARD_MEC_ASSY6941_MEC1753_QSZ diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj new file mode 100644 index 000000000000..b58c53c2bcc5 --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941_MEC1743_QLJ + select SOC_MEC1743_QLJ diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz new file mode 100644 index 000000000000..951583698bdd --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941_MEC1743_QSZ + select SOC_MEC1743_QSZ diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj new file mode 100644 index 000000000000..0ea3dbcffa4b --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941_MEC1753_QLJ + select SOC_MEC1753_QLJ diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz new file mode 100644 index 000000000000..2d631fca2807 --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941_MEC1753_QSZ + select SOC_MEC1753_QSZ diff --git a/boards/microchip/mec_assy6941/board.cmake b/boards/microchip/mec_assy6941/board.cmake new file mode 100644 index 000000000000..840168650d46 --- /dev/null +++ b/boards/microchip/mec_assy6941/board.cmake @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SPI_IMAGE_NAME spi_image.bin) + +board_set_flasher_ifnset(dediprog) + +# --vcc=0 - use 3.5V to flash +board_finalize_runner_args(dediprog + "--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}" + "--vcc=0" +) + +# This allows a custom script to be used for flashing the SPI chip. +include(${ZEPHYR_BASE}/boards/common/misc.board.cmake) diff --git a/boards/microchip/mec_assy6941/board.yml b/boards/microchip/mec_assy6941/board.yml new file mode 100644 index 000000000000..2849b6b8a08f --- /dev/null +++ b/boards/microchip/mec_assy6941/board.yml @@ -0,0 +1,9 @@ +board: + name: mec_assy6941 + full_name: MEC17xxEVB ASSY6941 + vendor: microchip + socs: + - name: mec1743_qlj + - name: mec1743_qsz + - name: mec1753_qlj + - name: mec1753_qsz diff --git a/boards/microchip/mec_assy6941/doc/index.rst b/boards/microchip/mec_assy6941/doc/index.rst new file mode 100644 index 000000000000..da25d132cef0 --- /dev/null +++ b/boards/microchip/mec_assy6941/doc/index.rst @@ -0,0 +1,394 @@ +.. zephyr:board:: mec_assy6941 + +Overview +******** + +The MEC5 Assembly 6941 EVB kit is a development platform to evaluate the Microchip +MEC174x and MEC175x series microcontrollers. This board requires a CPU daughter card: +DC 176WFBGA DC ASSY 6942 for MEC1743Q-LJ or MEC1753Q-LJ (176-pin package) + +Hardware +******** + +- MEC174xQ-LJ/SZ or MEC175xQ-LJ/SZ ARM Cortex-M4 Processor +- 480 KB total SRAM (416 KB code, 64 KB data) and 128 KB boot ROM +- Keyboard interface +- ADC & GPIO headers +- Four DB9 UART connectors +- FAN0, FAN1, FAN2 headers +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- 10 SMBUS headers +- VCI interface +- Two Hardware Driven PS/2 Port +- eSPI header +- 2 Sockets for SPI NOR chips +- One reset and VCC_PWRDGD pushbuttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. +- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. +- MEC175x has one I3C Host controller and one I3C secondary controller each with multiple ports. + +For more information about the MEC174x please see `MEC174x Data Brief`_ +For more information about the MEC175x please see `MEC175x Data Brief`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC174x EVB ASSY 6941 Rev B +- MEC174x 176WFBGA SOLDER DC ASSY 6942 with MEC1743Q-LJ or MEC1753Q-LJ silicon +- SPI DONGLE ASSY 6791 + +System Clock +============ + +The MEC174x/MEC175x MCU is configured to use the 96Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 96 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART1 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper settings for EVB Assy 6941 Rev B +======================================= + +Power-related jumpers +--------------------- + +If you wish to power from +5V power brick, then connect to barrel connector ``P1`` +(5.5mm OD, 2.1mm ID) and set the jumper ``J1 5-6``. + +If you wish to power from the Host USB micro-USB type A/B connector ``J62``, move the +jumper to ``J1 9-10`` ``J59 1-2`` and ``J61 1-2``. + + +.. note:: A single jumper is required in ``J1``. + +Required power jumpers on: + + * ``JP42 1-2``, ``JP43 1-2``, ``JP45 1-2``, ``JP47 1-2``, ``JP48 1-2`` + * ``JP50 1-2``, ``JP53 1-2``, ``JP56 1-2``, ``JP58 1-2``, ``JP60 1-2`` + * ``JP62 1-2``, ``JP65 1-2``, ``JP66 1-2``, ``JP68 1-2`` + +Select board +3.3V_STBY for: + + * ``JP161 1-2`` VBAT_CHIP power rail + * ``J67 1-2`` VCHIP_VTR_REG power rail + * ``JP157 1-2`` VCHIP_VTR_PLL power rail + * ``JP158 1-2`` VCHIP_VTR_ANALOG power rail + * ``JP159 1-2`` VCHIP_VTR1 power rail + +VCHIP_VTR2 power rail can be +3.3V or +1.8V affecting the pins on VTR2. +NOTE: QSPI shared port pins are on the VTR2 power rail. +Select one only: + + * ``J68 1-2`` VTR2 is connected to +3.3V_STBY + * ``J68 3-4`` VTR2 is connected to +1.8V_STBY + +VCHIP_VTR3 power rail in normal operation is connected to +1.8V. + * ``JP160 1-2`` VTR3 is connected to +1.8V_STBY + +Jumper selection for VCC_PWRGD +VCC_PWRGD is connected to a 4.75K pull-up to VTR1, switch S1 to ground it, +and reset generator U2. + + * ``JP17 3x7 19-20`` + * ``JP19 3x6 8-9`` + * ``JP36 1-2`` + * ``JP34 1-2`` + +Jumper selection for nRESET_IN +nRESET_IN is connected to a 4.75K pull-up to VTR1, switch S2 to ground it, +and reset generator U3. + + * ``JP37 1-2`` + * ``JP35 1-2`` + +Boot-ROM Straps +--------------- + +These jumpers configure MEC174x/MEC175x Boot-ROM straps. + + * ``JP1 1-2`` UART_BSTRAP Normal Boot + * ``JP2 1-2`` CR_STRAP Normal Boot + * ``JP3 2-3`` JTAG_STRAP JTAG/SWD interface is not held in reset + * ``JP4 2-3`` CMP_STRAP GPIO207 is available as a GPIO + * ``JP5 1-2`` PWRGD_STRAP + * ``JP7 1-2`` BSS_STRAP Select eSPI CAF vs G3 if enabled in OTP + * ``JP8 1-2`` BSS_STRAP Default BSS_STRAP. Select load from Shared SPI + * ``JP6 1-2`` VTR2_STRAP + * ``JP9 1-2`` CRISIS_RECOVERY_STRAP + +Peripheral Routing Jumpers +-------------------------- + +UART0 to P19A DB9(top) + + * ``JP89 No jumper`` RS-232 transceiver U8 not in reset. + * ``JP21 2-3, 8-9`` Select UART0_TX and UART0_RX from GPIOs. + * ``JP22 1-2, 4-5`` Select UART0_TX and UART0_RX to U8. + +UART1 to P19B DB9(bottom) + + * ``JP90 No jumper`` RS-232 transceiver U9 not in reset. + * ``JP91 1-2, 4-5`` Connect UART1_TX and UART1_RX to U9. + * ``JP24 2-3, 5-6`` Select UART1_TX and UART1_RX from GPIOs. + +Shared SPI on J18 2x10 header. + + * ``JP18 14-15`` Select SHD_nCS0. + * ``JP18 17-18`` Select SHD_CLK. + * ``JP18 2-3`` Select SHD_IO0. + * ``JP18 5-6`` Select SHD_IO1. + * ``JP18 8-9`` Select SHD_IO2(nWP). + * ``JP18 11-12`` Select SHD_IO3(nHOLD). + +Second chip select for accessing SPI dongle flash U7. + * ``JP18 20-12`` Select SHD_nCS1. + +JTAG/SWD ARM JTAG 2x10 J29. + + * ``JP80 1-2`` No jumper. This jumper holds JTAG/SWD interface in reset. + * ``JP12 2-3`` Select JTAG_TDO or SWO. + * ``JP12 5-6`` Select JTAG_TDI Not required for ARM SWD. + * ``JP12 8-9`` Select JTAG_TMS or SWDIO. + * ``JP12 11-12`` Select JTAG_CLK or SWCLK. + +NOTE: +ARM SWD is a two pin interface using JTAG_TMS as a bidirectional I/O pin and JTAG_CLK. +The ARM Serial Wire Output Trace feature is on a third pin, JTAG_TDO. +Configuration options are: + + 1. 4-pin JTAG or SWD plus SWO. Connect all four JP12 jumpers shown above. + 2. 2-pin SWD plus SWO. Connect JP12 jumpers for JTAG_TDO, JTAG_TMS, and JTAG_CLK. JTAG_TDI is available to use as GPIO145. + 3. 2-pin SWD only. Connect JP12 jumpers for JTAG_TMS and JTAG_CLK. JTAG_TDI and JTAG_TDO are available as GPIO145 and GPIO146 respectively + +Jumper settings for MEC174x/MEC175x 176WFBGA Socket DC Assy 6942 Rev A0p1 +========================================================================= + +The jumper configuration explained above covers the base board. The ASSY +6942 MEC174x/MEC175x CPU board provides capability for an optional, external 32KHz +clock source. The card includes a 32KHz crystal oscillator. The card can +also be configured to use an external 50% duty cycle 32KHz source on the +XTAL2/32KHZ_IN pin. Note, firmware must set the MEC174x/MEC175x clock enable +register to select the external source matching the jumper settings. If +using the MEC174x/MEC175x internal silicon oscillator then the 32K jumper settings +are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please +refer to the schematic in reference section below. + +Parallel 32KHz crystal configuration +------------------------------------ +``JP1 1x2 ON`` +``JP2 1x3 2-3`` + +External 32KHz 50% duty cycle configuration +------------------------------------------- +``JP1 1x2 NC`` +``JP2 1x3 1-2`` + +NOTE: EVB ``JP117 3-4`` Connects 32KHz OSC U15 output to DC. + +Building +======== + +#. Build :zephyr:code-sample:'hello_world` application as you normally do. + +#. The file :file:`spi_image.bin` will be created if the build system + can find the image generation tool. This binary image can be used + to flash the SPI chip. + +Programming and Debugging +========================= + +Setup +===== + +#. Example programming the SPI flash on the Assy6791 SPI dongle. + +#. We use a low cost USB-to-GPIO device based on the FTDI FT232H device. + + The FT232H device used here is the `AdaFruit FT232H`_ + The AdaFruit FT232H supports both 5V and 3.3V parts. + + The linux flashrom tool supports FT232H USB-to-GPIO used as an SPI programmer. + + .. code-block:: console + + $ sudo /usr/sbin/flashrom -V -p ft2232_spi:type=232H,divisor=30 -w spi_image.bin + +#. Clone the `MEC174x SPI Image Gen`_ or `MEC175x SPI Image Gen`_ repository or download the + files within that directory. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``MEC5_SPI_GEN``, for example: + + .. code-block:: console + + export MEC5_SPI_GEN=/mec174x_spi_gen_linux_x86_64 + or + export MEC5_SPI_GEN=/mec175x_spi_gen_linux_x86_64 + + +#. The default configuration file is mec174x_spi_cfg.txt or mec175x_spi_cfg.txt located in + ${BOARD_DIR}/support. If needed, a custom SPI image configuration file can be specified + to override the default one. + + .. code-block:: console + + export MEC5_SPI_CFG=custom_spi_cfg.txt + +Wiring +======== + +#. Connect the SPI Dongle ASSY 6791 to ``J18`` in the EVB. + + .. image:: spi_dongle_assy6791.webp + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. IMPORTANT: Temporarily remove the jumper from JP87 to isolate SPI dongle power from EVB power rails. + This will prevent the SPI programmer from back driving voltage to the EVB. + +#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip + ``U3``. + + .. note:: The AdaFruit FT232H board supports +5V or +3.3V SPI flash devices. It has + separate +3V and +5V pins. You should connect the appropriate voltage rail to the + Assy6791 flash dongle's J6-1 power pin. It is recommended to remove the Assy6791 + dongle from the EVB when flashing. If the dongle is attached to an unpowered EVB then + then the SPI programmer will back drive all the components. Back driving voltage can + be avoided by removing the jumper on EVB JP87 disconnecting VTR1/VTR2 from the 2x10 + header J18. + + +------------+---------------+ + | AdaFruit | Assy6791 | + | Connector | J6 Connector | + +============+===============+ + | 3V or 5V | 1 | + +------------+---------------+ + | GND | 2 | + +------------+---------------+ + | D3 | 3 | + +------------+---------------+ + | D0 | 4 | + +------------+---------------+ + | D2 | 6 | + +------------+---------------+ + | D1 | 5 | + +------------+---------------+ + +#. The AdaFruit FT232H has USB type-C connector. Connect it to your + development system with the appropriate USB cable. The FT232H board and + Assy6791 dongle will be powered. + + +Flashing +======== + +#. Run your favorite terminal program + +#. Flash the SPI image created by Microchip SPI image generator during the + zephyr build process. The divisor option flashrom passes to the linux + FT232 driver divides down the 60 MHz SPI clock. You can read the current + SPI image by changing the '-w' option to '-r'. + + .. code-block:: console + + $ sudo /usr/sbin/flashrom -V -p ft2232_spi:type=232H,divisor=30 -w spi_image.bin + + +#. When flashrom completes. + Disconnect USB cable to remove power from the AdaFruit FT232H programmer. + Disconnect FT232H from Assy6791 dongle. + Replace the jumper on EVB JP87. + +# Power on the EVB. + +#. You should see ``"Hello World! "`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Troubleshooting +=============== + +#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` + are lit. If one of these is off, then check the power-related jumpers again. + +#. If you suspect the SPI image was not programmed remove the SPI dongle from the EVB + and try flashing it again. + +PCA9555 Enabling +================ +#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: + + As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, + however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, + so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use + I2C01 port by making some jumpers setting as below: + + +---------+---------+------------------------------------------+ + | Pin 1 | Pin 2 | Comment | + +=========+=========+==========================================+ + | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | + +---------+---------+------------------------------------------+ + | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | + +---------+---------+------------------------------------------+ + | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | + +---------+---------+------------------------------------------+ + | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | + +---------+---------+------------------------------------------+ + | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | + +---------+---------+------------------------------------------+ + | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | + +---------+---------+------------------------------------------+ + +References +********** + +.. target-notes:: + +.. _MEC174x Data Brief: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/MEC174x/MEC174x_DataBrief.pdf +.. _MEC175x Data Brief: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/MEC175x/MEC175x_DataBrief.pdf +.. _EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/EVB_Assy6941.pdf +.. _SOC Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/MEC174x_176WFBGA_DC_6942.pdf +.. _SPI Dongle Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/SPI_Flash_and_EEPROM_Dongle_Assy6791_Rev_B1p0.pdf +.. _MEC174x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/main/MEC174x/SPI_image_gen +.. _MEC175x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/main/MEC175x/SPI_image_gen +.. _AdaFruit FT232H: + https://www.adafruit.com/product/2264 diff --git a/boards/microchip/mec_assy6941/doc/mec_assy6941_evb.webp b/boards/microchip/mec_assy6941/doc/mec_assy6941_evb.webp new file mode 100644 index 000000000000..950e721cea87 Binary files /dev/null and b/boards/microchip/mec_assy6941/doc/mec_assy6941_evb.webp differ diff --git a/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp b/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp new file mode 100644 index 000000000000..f71375f86905 Binary files /dev/null and b/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp differ diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts new file mode 100644 index 000000000000..a2b52bd505c3 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Microchip MEC ASSY6941 MEC1743-QLJ evaluation board"; + compatible = "microchip,mec_assy6941-mec1743_qlj"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart1; + rtimer-busy-wait-timer = &timer5; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; + status = "okay"; + cpu-power-states = <&idle &suspend_to_ram>; +}; + +/* Disable ARM SysTick kernel timer driver */ +&systick { + status = "disabled"; +}; + +/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ +&rtimer { + compatible = "microchip,mec5-ktimer"; + status = "okay"; +}; + +/* We chose 32-bit basic timer 5 for use by ktimer */ +&timer5 { + status = "okay"; +}; + +&uart1 { + compatible = "microchip,mec5-uart"; + status = "okay"; + clock-frequency = <1843200>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml new file mode 100644 index 000000000000..cfdc0564d2ff --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml @@ -0,0 +1,27 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec_assy6941/mec1743_qlj +name: MEC174X EVB ASSY 6941 with MEC1743-QLJ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 60 +flash: 416 +supported: + - gpio + - pinctrl + - i2c + - spi +testing: + binaries: + - spi_image.bin + ignore_tags: + - bluetooth + - net +vendor: microchip diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig new file mode 100644 index 000000000000..47eaa31ebd3f --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts new file mode 100644 index 000000000000..fc4eb98d5685 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Microchip MEC ASSY6941 MEC1743-QSZ evaluation board"; + compatible = "microchip,mec_assy6941-mec1743_qsz"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart1; + rtimer-busy-wait-timer = &timer5; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; + status = "okay"; + cpu-power-states = <&idle &suspend_to_ram>; +}; + +/* Disable ARM SysTick kernel timer driver */ +&systick { + status = "disabled"; +}; + +/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ +&rtimer { + compatible = "microchip,mec5-ktimer"; + status = "okay"; +}; + +/* We chose 32-bit basic timer 5 for use by ktimer */ +&timer5 { + status = "okay"; +}; + +&uart1 { + compatible = "microchip,mec5-uart"; + status = "okay"; + clock-frequency = <1843200>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml new file mode 100644 index 000000000000..ae39df56b046 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml @@ -0,0 +1,27 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec_assy6941/mec1743_qsz +name: MEC174X EVB ASSY 6941 with MEC1743-QSZ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 60 +flash: 416 +supported: + - gpio + - pinctrl + - i2c + - spi +testing: + binaries: + - spi_image.bin + ignore_tags: + - bluetooth + - net +vendor: microchip diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig new file mode 100644 index 000000000000..47eaa31ebd3f --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts new file mode 100644 index 000000000000..1187fef8a072 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Microchip MEC ASSY6941 MEC1753-QLJ evaluation board"; + compatible = "microchip,mec_assy6941-mec1753_qlj"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart1; + rtimer-busy-wait-timer = &timer5; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; + status = "okay"; + cpu-power-states = <&idle &suspend_to_ram>; +}; + +/* Disable ARM SysTick kernel timer driver */ +&systick { + status = "disabled"; +}; + +/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ +&rtimer { + compatible = "microchip,mec5-ktimer"; + status = "okay"; +}; + +/* We chose 32-bit basic timer 5 for use by ktimer */ +&timer5 { + status = "okay"; +}; + +&uart1 { + compatible = "microchip,mec5-uart"; + status = "okay"; + clock-frequency = <1843200>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml new file mode 100644 index 000000000000..ad4578718f43 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml @@ -0,0 +1,27 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec_assy6941/mec1753_qlj +name: MEC174X EVB ASSY 6941 with MEC1753-QLJ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 60 +flash: 416 +supported: + - gpio + - pinctrl + - i2c + - spi +testing: + binaries: + - spi_image.bin + ignore_tags: + - bluetooth + - net +vendor: microchip diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig new file mode 100644 index 000000000000..47eaa31ebd3f --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts new file mode 100644 index 000000000000..b2e7c570cc6e --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Microchip MEC ASSY6941 MEC1753-QSZ evaluation board"; + compatible = "microchip,mec_assy6941-mec1753_qsz"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart1; + rtimer-busy-wait-timer = &timer5; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; + status = "okay"; + cpu-power-states = <&idle &suspend_to_ram>; +}; + +/* Disable ARM SysTick kernel timer driver */ +&systick { + status = "disabled"; +}; + +/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ +&rtimer { + compatible = "microchip,mec5-ktimer"; + status = "okay"; +}; + +/* We chose 32-bit basic timer 5 for use by ktimer */ +&timer5 { + status = "okay"; +}; + +&uart1 { + compatible = "microchip,mec5-uart"; + status = "okay"; + clock-frequency = <1843200>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml new file mode 100644 index 000000000000..d825e2177d89 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml @@ -0,0 +1,27 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec_assy6941/mec1753_qsz +name: MEC174X EVB ASSY 6941 with MEC1753-QSZ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 60 +flash: 416 +supported: + - gpio + - pinctrl + - i2c + - spi +testing: + binaries: + - spi_image.bin + ignore_tags: + - bluetooth + - net +vendor: microchip diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig new file mode 100644 index 000000000000..47eaa31ebd3f --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt b/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt new file mode 100644 index 000000000000..62ddf1436911 --- /dev/null +++ b/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt @@ -0,0 +1,51 @@ +; MEC174x SPI Image Generator configuration file +[SPI] +SPISizeMegabits = 128 + +[DEVICE] +TagAddr0 = 0 +TagAddr1 = 0 +; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID +; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image +; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do +; not match. +BoardID = 0x316 + +[IMAGE "0"] +ImageLocation = 0x2000 +SpiFreqMHz = 24 +SpiReadCommand = slow +SpiDriveStrength = 4 +SpiSlewFast = false +SpiSignalControl = 0x00 +IMG1BinFile = zephyr.bin +ImageRevision = 0 +FwOffset = 0 +IMG1LoadAddress = 0xB0000 +IMG1EntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0xff +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0 +RollbackProtPerm063032 = 0 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0 +ECDSAPrivKeyFile = ECC384r.pem +ECDSAPrivKeyPassword = MCHPECC384r +FwEncrypt = false +AesGenECPubKeyFile = ECC384r_crt.pem +TagBuildNumber= 0 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 0 +Comp0ReadCmdByte = 0 +Comp0WritCmdByte = 0 +Comp0DrvValue = 0 +Comp0DrvMask = 0 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 0 +Comp1ReadCmdByte = 0 +Comp1WritCmdByte = 0 +Comp1DrvValue = 0 +Comp1DrvMask = 0 diff --git a/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt b/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt new file mode 100644 index 000000000000..b7428492fc6b --- /dev/null +++ b/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt @@ -0,0 +1,52 @@ +; MEC175x SPI Image Generator configuration file +[SPI] +SPISizeMegabits = 128 + +[DEVICE] +DeviceSel = A +TagAddr0 = 0 +TagAddr1 = 0 +; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID +; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image +; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do +; not match. +BoardID = 0x316 + +[IMAGE "0"] +ImageLocation = 0x2000 +SpiFreqMHz = 24 +SpiReadCommand = slow +SpiDriveStrength = 4 +SpiSlewFast = false +SpiSignalControl = 0x00 +IMG1BinFile = zephyr.bin +ImageRevision = 0 +FwOffset = 0 +IMG1LoadAddress = 0xB0000 +IMG1EntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0xff +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0 +RollbackProtPerm063032 = 0 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0 +ECDSAPrivKeyFile = ECC384r.pem +ECDSAPrivKeyPassword = MCHPECC384r +FwEncrypt = false +AesGenECPubKeyFile = ECC384r_crt.pem +TagBuildNumber= 0 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 0 +Comp0ReadCmdByte = 0 +Comp0WritCmdByte = 0 +Comp0DrvValue = 0 +Comp0DrvMask = 0 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 0 +Comp1ReadCmdByte = 0 +Comp1WritCmdByte = 0 +Comp1DrvValue = 0 +Comp1DrvMask = 0 diff --git a/boards/microchip/mpfs_icicle/Kconfig.defconfig b/boards/microchip/mpfs_icicle/Kconfig.defconfig new file mode 100644 index 000000000000..8c630afbfc01 --- /dev/null +++ b/boards/microchip/mpfs_icicle/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright 2025 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPFS_ICICLE + +choice SPI_NOR_SFDP + default SPI_NOR_SFDP_RUNTIME +endchoice + +endif diff --git a/boards/microchip/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst index ee5d07b5bda0..12c57e62029e 100644 --- a/boards/microchip/mpfs_icicle/doc/index.rst +++ b/boards/microchip/mpfs_icicle/doc/index.rst @@ -10,6 +10,8 @@ More information can be found on the `Microchip website +#include +#include +#include + +/ { + model = "SAMA7G54-EK board"; + compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; + + chosen { + zephyr,sram = &ddram; + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + }; + + clocks { + main_xtal { + clock-frequency = ; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + }; + + ddram: ddram@60000000 { + compatible = "ddram"; + reg = <0x60000000 DT_SIZE_M(512)>; + }; +}; + +&flx3 { + mchp,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + current-speed = <115200>; + pinctrl-0 = <&pinctrl_flx3_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&pinctrl { + pinctrl_flx3_default: flx3_default { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; +}; + +&pit64b0 { + clock-frequency = ; +}; diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml new file mode 100644 index 000000000000..f13a42f23ba4 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml @@ -0,0 +1,14 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# SPDX-License-Identifier: Apache-2.0 + +identifier: sama7g54_ek +name: SAMA7G54-EK +type: mcu +arch: arm +toolchain: + - zephyr +ram: 128 +supported: + - shell + - uart +vendor: microchip diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig b/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig new file mode 100644 index 000000000000..10b06d0f7f42 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig @@ -0,0 +1,9 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index a33f76d8beba..3541b8165e63 100644 --- a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -21,31 +21,8 @@ to the microcontroller. Supported Features ================== -The Zephyr MikroE Clicker 2 configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in -:zephyr_file:`boards/mikroe/clicker_2/mikroe_clicker_2_defconfig` + +.. zephyr:board-supported-hw:: Connections and IOs =================== @@ -59,6 +36,9 @@ For connections on the edge connectors, please refer to `Clicker 2 for STM32 Use Programming and Debugging ************************* + +.. zephyr:board-supported-runners:: + Applications for the ``mikroe_clicker_2`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/mikroe/clicker_ra4m1/doc/index.rst b/boards/mikroe/clicker_ra4m1/doc/index.rst index 56099ee6f429..88a005f03ff0 100644 --- a/boards/mikroe/clicker_ra4m1/doc/index.rst +++ b/boards/mikroe/clicker_ra4m1/doc/index.rst @@ -18,30 +18,13 @@ development board see the `Clicker RA4M1 website`_. Supported Features ================== -The Zephyr Mikroe Clicker RA4M1 configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig`. +.. zephyr:board-supported-hw:: Programming and debugging ************************* +.. zephyr:board-supported-runners:: + Building & Flashing =================== diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi new file mode 100644 index 000000000000..d2bd43dfa190 --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Ian Morris + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx */ + psels = ; + }; + + group2 { + /* rx */ + psels = ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts index 5a626a783648..d5fea8287b32 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts @@ -5,14 +5,15 @@ */ /dts-v1/; -#include +#include #include #include -#include + +#include "mikroe_clicker_ra4m1-pinctrl.dtsi" / { model = "Mikroe Clicker RA4M1"; - compatible = "renesas,r7fa4m1ab3cfm"; + compatible = "renesas,ra4m1", "renesas,ra"; chosen { zephyr,console = &uart0; @@ -27,6 +28,7 @@ gpios = <&ioport4 9 GPIO_ACTIVE_HIGH>; label = "User LED 1"; }; + ld2: led_2 { gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>; label = "User LED 2"; @@ -40,6 +42,12 @@ label = "User Button 1"; zephyr,code = ; }; + + btn2: button_2 { + gpios = <&ioport3 1 GPIO_ACTIVE_LOW>; + label = "User Button 2"; + zephyr,code = ; + }; }; mikrobus_header: mikrobus-connector { @@ -69,19 +77,7 @@ led0 = &ld1; led1 = &ld2; sw0 = &btn1; - }; -}; - -&pinctrl { - sci0_default: sci0_default { - group1 { - /* tx */ - psels = ; - }; - group2 { - /* rx */ - psels = ; - }; + sw1 = &btn2; }; }; @@ -95,6 +91,25 @@ }; }; +&iic1 { + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <10 1>, <11 1>, <12 1>, <13 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + interrupts = <23 1>, <24 1>, <25 1>, <26 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + &ioport0 { status = "okay"; }; @@ -115,7 +130,13 @@ status = "okay"; }; -&fcu { +&port_irq6 { + interrupts = <28 12>; + status = "okay"; +}; + +&port_irq9 { + interrupts = <27 12>; status = "okay"; }; @@ -129,6 +150,7 @@ }; &iclk { + clock-frequency = <12000000>; div = <1>; }; @@ -151,3 +173,7 @@ &fclk { div = <2>; }; + +mikrobus_serial: &uart0 {}; +mikrobus_i2c: &iic1 {}; +mikrobus_spi: &spi0 {}; diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig index 2e434ba45ea3..1c187cb544cd 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2024 Ian Morris # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 - -CONFIG_BUILD_OUTPUT_HEX=y - # Enable uart driver CONFIG_SERIAL=y @@ -14,6 +10,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 02208b66bf32..02504c3bc9a3 100644 --- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -49,37 +49,7 @@ The board can be flashed by using STLinkV2 with the following connections. Supported Features ================== -The MINI-M4 for STM32 board configuration supports the following hardware -features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CRYP | on-chip | crypto | -+-----------+------------+----------------------+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| PWM | on-chip | PWM | -+-----------+------------+----------------------+ -| USB | on-chip | USB | -+-----------+------------+----------------------+ - - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in -:zephyr_file:`boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig` +.. zephyr:board-supported-hw:: Serial Port =========== @@ -89,6 +59,8 @@ The Zephyr console output is assigned to USART2. Default settings are 115200 8N1 Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Applications for the ``mikroe_mini_m4_for_stm32`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). diff --git a/boards/mikroe/quail/Kconfig.defconfig b/boards/mikroe/quail/Kconfig.defconfig new file mode 100644 index 000000000000..ea45af09da97 --- /dev/null +++ b/boards/mikroe/quail/Kconfig.defconfig @@ -0,0 +1,10 @@ +# MikroE Quail board configuration + +# Copyright (c) 2025 ThoseBoards +# SPDX-License-Identifier: Apache-2.0 + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +config SPI_STM32_INTERRUPT + default y + depends on SPI diff --git a/boards/mikroe/quail/Kconfig.mikroe_quail b/boards/mikroe/quail/Kconfig.mikroe_quail new file mode 100644 index 000000000000..f711abe5738e --- /dev/null +++ b/boards/mikroe/quail/Kconfig.mikroe_quail @@ -0,0 +1,5 @@ +# Copyright (c) 2025 ThoseBoards +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_QUAIL + select SOC_STM32F427XX diff --git a/boards/mikroe/quail/board.cmake b/boards/mikroe/quail/board.cmake new file mode 100644 index 000000000000..7718f87e84a9 --- /dev/null +++ b/boards/mikroe/quail/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F427VIT6" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/mikroe/quail/board.yml b/boards/mikroe/quail/board.yml new file mode 100644 index 000000000000..b363f83059c7 --- /dev/null +++ b/boards/mikroe/quail/board.yml @@ -0,0 +1,6 @@ +board: + name: mikroe_quail + full_name: MikroE Quail + vendor: mikroe + socs: + - name: stm32f427xx diff --git a/boards/mikroe/quail/doc/img/mikroe_quail.webp b/boards/mikroe/quail/doc/img/mikroe_quail.webp new file mode 100644 index 000000000000..801b29d3a485 Binary files /dev/null and b/boards/mikroe/quail/doc/img/mikroe_quail.webp differ diff --git a/boards/mikroe/quail/doc/mikroe_quail.rst b/boards/mikroe/quail/doc/mikroe_quail.rst new file mode 100644 index 000000000000..5e2f7d82947f --- /dev/null +++ b/boards/mikroe/quail/doc/mikroe_quail.rst @@ -0,0 +1,99 @@ +.. zephyr:board:: mikroe_quail + +Overview +******** +MikroE Quail for STM32 is a development board containing an `STM32F427`_ +microcontroller. It is equipped with four mikroBUS sockets. +The edges of the board are lined with screw terminals and USB ports for +additional connectivity. + +Hardware +******** +The Quail board contains the following connections: + + - Four mikroBUS connectors + - 32 screw terminals + - two USB ports, one for programming and one for external storage + +Furthermore the board contains three LEDs that are connected +to the microcontroller. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The four mikroBUS interfaces are aliased in the device tree so that their +peripherals can be accessed using ``mikrobus_N_INTERFACE`` so e.g. the SPI on +bus 2 can be found by the alias ``mikrobus_2_spi``. The numbering corresponds +with the marking on the board. + +For connections on the edge connectors, please refer to `Quail for STM32 User Manual`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``mikroe_quail`` board can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` for more details). + + +Flashing +======== +The board ships with a locked flash, and will fail with the message: + +.. code-block:: console + + Error: stm32x device protected + +Unlocking with OpenOCD makes it possible to flash. + +.. code-block:: console + + $ openocd -f /usr/share/openocd/scripts/interface/stlink-v2.cfg \ + -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ + -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mikroe_quail + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! mikroe_quail + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mikroe_quail + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Quail website: + https://www.mikroe.com/quail +.. _Quail for STM32 User Manual: + https://download.mikroe.com/documents/starter-boards/other/quail/quail-board-manual-v100.pdf +.. _STM32F427VIT6 Website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html +.. _STM32F427: + https://www.st.com/resource/en/datasheet/stm32f427vg.pdf diff --git a/boards/mikroe/quail/mikroe_quail.dts b/boards/mikroe/quail/mikroe_quail.dts new file mode 100644 index 000000000000..c314f658c389 --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail.dts @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2025 ThoseBoards + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "MikroE Quail for STM32"; + compatible = "mikroe,stm32-e427", "st,stm32f427"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &flash1; + zephyr,ccm = &ccm0; + }; + + leds { + compatible = "gpio-leds"; + + ld1: led_1 { + gpios = <&gpioe 15 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + + ld2: led_2 { + gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + + ld3: led_3 { + gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + zephyr,user { + io-channels = <&adc1 0>, <&adc1 1>, <&adc2 0>, <&adc2 1>; + }; + + mikrobus_1_header: mikrobus-connector-1 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 6 0>, /* AN */ + <1 0 &gpioa 2 0>, /* RST */ + <2 0 &gpioa 3 0>, /* CS */ + <3 0 &gpiob 3 0>, /* SCK */ + <4 0 &gpiob 4 0>, /* MISO */ + <5 0 &gpiob 5 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpioe 9 0>, /* PWM */ + <7 0 &gpioa 1 0>, /* INT */ + <8 0 &gpiod 9 0>, /* RX */ + <9 0 &gpiod 8 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_2_header: mikrobus-connector-2 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 4 0>, /* AN */ + <1 0 &gpioe 1 0>, /* RST */ + <2 0 &gpioe 0 0>, /* CS */ + <3 0 &gpiob 3 0>, /* SCK */ + <4 0 &gpiob 4 0>, /* MISO */ + <5 0 &gpiob 5 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 15 0>, /* PWM */ + <7 0 &gpiob 9 0>, /* INT */ + <8 0 &gpiod 6 0>, /* RX */ + <9 0 &gpiod 5 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_3_header: mikrobus-connector-3 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 7 0>, /* AN */ + <1 0 &gpiod 8 0>, /* RST */ + <2 0 &gpiod 11 0>, /* CS */ + <3 0 &gpioc 10 0>, /* SCK */ + <4 0 &gpioc 11 0>, /* MISO */ + <5 0 &gpioc 12 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 13 0>, /* PWM */ + <7 0 &gpioc 8 0>, /* INT */ + <8 0 &gpioc 7 0>, /* RX */ + <9 0 &gpioc 6 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_4_header: mikrobus-connector-4 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 5 0>, /* AN */ + <1 0 &gpiod 0 0>, /* RST */ + <2 0 &gpiod 1 0>, /* CS */ + <3 0 &gpioc 10 0>, /* SCK */ + <4 0 &gpioc 11 0>, /* MISO */ + <5 0 &gpioc 12 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 14 0>, /* PWM */ + <7 0 &gpioa 14 0>, /* INT */ + <8 0 &gpioa 10 0>, /* RX */ + <9 0 &gpioa 9 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + edge_header: connector { + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 5 0>, /* ,PC5 */ + <1 0 &gpiob 0 0>, /* ,PB0 */ + <2 0 &gpioe 7 0>, /* ,PE7 */ + <3 0 &gpioe 8 0>, /* ,PE8 */ + <4 0 &gpioe 11 0>, /* ,PE11 */ + <5 0 &gpioc 4 0>, /* ,PC4 */ + <6 0 &gpioe 13 0>, /* ,PE13 */ + <7 0 &gpioe 14 0>, /* ,PE14 */ + <8 0 &gpiob 10 0>, /* ,PB10 */ + <9 0 &gpiob 11 0>, /* ,PB11 */ + <10 0 &gpiob 12 0>, /* ,PB12 */ + <11 0 &gpiob 13 0>, /* ,PB13 */ + <12 0 &gpiob 6 0>, /* ,PB6 # I2C1 */ + <13 0 &gpiob 7 0>, /* ,PB7 # I2C1 */ + <14 0 &gpioc 10 0>, /* ,PC10 # SPI3 */ + <15 0 &gpioc 11 0>, /* ,PC11 # SPI3 */ + <16 0 &gpioc 12 0>, /* ,PC12 # SPI3 */ + <17 0 &gpiod 10 0>, /* ,PD10 # SPI3 */ + <18 0 &gpioa 15 0>, /* ,PA15 */ + <19 0 &gpioc 13 0>, /* ,PC13 */ + <20 0 &gpioe 6 0>, /* ,PE6 */ + <21 0 &gpioe 5 0>, /* ,PE5 */ + <22 0 &gpiod 2 0>, /* ,PD2 */ + <23 0 &gpiod 3 0>, /* ,PD3 */ + <24 0 &gpiod 4 0>, /* ,PD4 */ + <25 0 &gpiod 7 0>, /* ,PD7 */ + <26 0 &gpioe 2 0>, /* ,PE2 */ + <27 0 &gpioe 3 0>, /* ,PE3 */ + <28 0 &gpioe 4 0>; /* ,PE4 */ + }; + + aliases { + led0 = &ld1; + led1 = &ld2; + led2 = &ld3; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; + }; + + skd1: socket_1_adc { + status = "okay"; + io-channels = <&adc2 0>; + }; + + skd2: socket_2_adc { + status = "okay"; + io-channels = <&adc1 0>; + }; + + skd3: socket_3_adc { + status = "okay"; + io-channels = <&adc2 1>; + }; + + skd4: socket_4_adc { + status = "okay"; + io-channels = <&adc1 1>; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <96>; + div-p = <2>; + div-q = <4>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> + +&spi1 { + pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>, <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi3 { + status = "okay"; + pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>; + pinctrl-names = "default"; + + cs-gpios = + <&gpiod 11 GPIO_ACTIVE_LOW>, // CS0 + <&gpiod 1 GPIO_ACTIVE_LOW>, // CS1 + <&gpioa 13 GPIO_ACTIVE_LOW>; // CS2 +}; + +/* Flash chip 1 (extra flash connected to CS2) */ +&spi3 { + flash1: flash@2 { + compatible = "jedec,spi-nor"; // Typical flash chip compatibility string + reg = <2>; // The CS0 pin on the SPI bus + // S25FL164K flash's actual JEDEC: Device ID = 16h, Device Type = 40h, + // Capacity = 17h + //jedec-id = [16 40 17]; + jedec-id = [01 60 17]; + spi-max-frequency = <50000000>; // Max frequency for the flash chip (e.g., 50 MHz) + size = <0x800000>; // Flash memory size (16MB example) + page-size = <256>; // Flash page size (usually 256 or 512 bytes) + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc1 { + status ="okay"; + pinctrl-0 = <&adc1_in4_pa4 &adc1_in5_pa5>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <2>; +}; + +&adc2 { + status ="okay"; + pinctrl-0 = <&adc2_in6_pa6 &adc2_in7_pa7>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <2>; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; + +mikrobus_1_adc: &skd1 {}; + +mikrobus_1_i2c: &i2c1 {}; + +mikrobus_1_spi: &spi1 {}; + +mikrobus_1_uart: &usart3 {}; + +mikrobus_2_adc: &skd2 {}; + +mikrobus_2_i2c: &i2c1 {}; + +mikrobus_2_spi: &spi1 {}; + +mikrobus_2_uart: &usart2 {}; + +mikrobus_3_adc: &skd3 {}; + +mikrobus_3_i2c: &i2c1 {}; + +mikrobus_3_spi: &spi3 {}; + +mikrobus_3_uart: &usart6 {}; + +mikrobus_4_adc: &skd4 {}; + +mikrobus_4_i2c: &i2c1 {}; + +mikrobus_4_spi: &spi3 {}; + +mikrobus_4_uart: &usart1 {}; + +mikrobus_adc: &skd1 {}; + +mikrobus_i2c: &i2c1 {}; + +mikrobus_spi: &spi1 {}; + +mikrobus_uart: &usart3 {}; + +mikrobus_header: &mikrobus_1_header {}; diff --git a/boards/mikroe/quail/mikroe_quail.yaml b/boards/mikroe/quail/mikroe_quail.yaml new file mode 100644 index 000000000000..f114861f6bc7 --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail.yaml @@ -0,0 +1,17 @@ +identifier: mikroe_quail +name: MikroE Quail for STM32 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 256 +flash: 2048 +supported: + - spi + - i2c + - uart + - adc + - gpio + - flash +vendor: mikroe diff --git a/boards/mikroe/quail/mikroe_quail_defconfig b/boards/mikroe/quail/mikroe_quail_defconfig new file mode 100644 index 000000000000..e5819cf79508 --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail_defconfig @@ -0,0 +1,11 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/mikroe/stm32_m4_clicker/doc/index.rst b/boards/mikroe/stm32_m4_clicker/doc/index.rst index 8bddfd3f7aaa..77f52fa96bf9 100644 --- a/boards/mikroe/stm32_m4_clicker/doc/index.rst +++ b/boards/mikroe/stm32_m4_clicker/doc/index.rst @@ -18,37 +18,13 @@ board see the `STM32 M4 Clicker website`_. Supported Features ================== -The ``mikroe_stm32_m4_clicker`` board target supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB | -+-----------+------------+-------------------------------------+ - -Other hardware features have not yet been enabled for this board. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig`. +.. zephyr:board-supported-hw:: Programming and debugging ************************* +.. zephyr:board-supported-runners:: + Building & Flashing =================== diff --git a/boards/mxchip/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst index 230073f82955..8ea178b7f930 100644 --- a/boards/mxchip/az3166_iotdevkit/doc/index.rst +++ b/boards/mxchip/az3166_iotdevkit/doc/index.rst @@ -34,25 +34,7 @@ The MXChip AZ3166 IoT DevKit has the following physical features: Supported Features ================== -The az3166_iotdevkit board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vector | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ +.. zephyr:board-supported-hw:: .. note:: @@ -61,6 +43,8 @@ hardware features: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + Flashing ======== diff --git a/boards/native/common/extra_args/extra_args.c b/boards/native/common/extra_args/extra_args.c index b2e57dc674ed..aa71b95552ce 100644 --- a/boards/native/common/extra_args/extra_args.c +++ b/boards/native/common/extra_args/extra_args.c @@ -14,9 +14,7 @@ static void remove_one_char(char *str) { - int i; - - for (i = 0; str[i] != 0; i++) { + for (int i = 0; str[i] != 0; i++) { str[i] = str[i+1]; } } diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index 8906001f1776..6b6a5a5e10eb 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -53,8 +53,8 @@ This port is designed and tested to run in Linux. .. note:: - You must have the 32-bit C library installed in your system - (in Ubuntu 16.04 install the gcc-multilib package) + To build for the 32bit targets you must have the 32-bit C library installed in your system + (in Debian/Ubuntu this is provided by the ``gcc-multilib`` package). .. note:: @@ -306,7 +306,7 @@ Architecture and design .. note:: - This section does not describe anymore the old :ref:`native_posix` or + This section does not describe anymore the old :kconfig:option:`CONFIG_NATIVE_APPLICATION` based architecture. It only describes the new native simulator based architecture used by targets built with the :kconfig:option:`CONFIG_NATIVE_LIBRARY` option. diff --git a/boards/native/native_posix/CMakeLists.txt b/boards/native/native_posix/CMakeLists.txt deleted file mode 100644 index b86941cc8542..000000000000 --- a/boards/native/native_posix/CMakeLists.txt +++ /dev/null @@ -1,34 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2017 Oticon A/S - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) -zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) - -zephyr_library_sources( - hw_models_top.c - timer_model.c - native_rtc.c - irq_handler.c - irq_ctrl.c - main.c - tracing.c - cmdline_common.c - cmdline.c - cpu_wait.c - hw_counter.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - ) - -if(CONFIG_HAS_SDL) - add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) -endif() - -zephyr_ld_options( - -lm -) diff --git a/boards/native/native_posix/Kconfig b/boards/native/native_posix/Kconfig deleted file mode 100644 index b629778f4cbc..000000000000 --- a/boards/native/native_posix/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2017 Oticon A/S -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX - bool - imply NATIVE_POSIX_TIMER - select POSIX_ARCH_CONSOLE - select NATIVE_APPLICATION - select 64BIT if BOARD_NATIVE_POSIX_NATIVE_64 - help - Native POSIX - Will produce a console Linux process which can be executed natively. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. - -if BOARD_NATIVE_POSIX - -comment "Native POSIX options" - -config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time" - default n if ARCH_POSIX_LIBFUZZER - default y if BT_USERCHAN || !TEST - help - When selected the execution of the process will be slowed down to real time. - (if there is a lot of load it may be slower than real time) - If deselected, the process will run as fast as possible. - Note that this only decouples simulated time from real/wall time. In either - case the zephyr kernel and application cannot tell the difference unless they - interact with some other driver/device which runs at real time. - -source "boards/native/common/sdl/Kconfig" - -endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig deleted file mode 100644 index 2d896061f783..000000000000 --- a/boards/native/native_posix/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2017 Oticon A/S -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NATIVE_POSIX - -config BOARD_DEPRECATED_RELEASE - default "v4.2.0" - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - default y - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config ETH_NATIVE_POSIX - default y if NET_L2_ETHERNET && ETH_DRIVER - -endif # NETWORKING - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y if !SERIAL - -config UART_CONSOLE - default y if SERIAL - -endif # CONSOLE - -endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.native_posix b/boards/native/native_posix/Kconfig.native_posix deleted file mode 100644 index cb7c03889c42..000000000000 --- a/boards/native/native_posix/Kconfig.native_posix +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX - select SOC_POSIX diff --git a/boards/native/native_posix/board.cmake b/boards/native/native_posix/board.cmake deleted file mode 100644 index c3f7c89918dd..000000000000 --- a/boards/native/native_posix/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2017 Oticon A/S - -set(SUPPORTED_EMU_PLATFORMS native) - -board_set_debugger_ifnset(native) -board_set_flasher_ifnset(native) -board_finalize_runner_args(native) diff --git a/boards/native/native_posix/board.yml b/boards/native/native_posix/board.yml deleted file mode 100644 index 07defd4185bf..000000000000 --- a/boards/native/native_posix/board.yml +++ /dev/null @@ -1,8 +0,0 @@ -boards: -- name: native_posix - full_name: Native POSIX execution (native_posix) - vendor: zephyr - socs: - - name: native - variants: - - name: "64" diff --git a/boards/native/native_posix/board_irq.h b/boards/native/native_posix/board_irq.h deleted file mode 100644 index 21c29768c8ef..000000000000 --- a/boards/native/native_posix/board_irq.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2017 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H -#define BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H - -#include "../common/irq/board_irq.h" - -#endif /* BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H */ diff --git a/boards/native/native_posix/board_soc.h b/boards/native/native_posix/board_soc.h deleted file mode 100644 index 572617a07365..000000000000 --- a/boards/native/native_posix/board_soc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2017 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ -/** - * @file Extra definitions provided by the board to soc.h - * - * Background: - * The POSIX ARCH/SOC/board layering is different than in normal archs - * The "SOC" does not provide almost any of the typical SOC functionality - * but that is left for the "board" to define it - * Device code may rely on the soc.h defining some things (like the interrupts - * numbers) - * Therefore this file is included from the inf_clock soc.h to allow a board - * to define that kind of SOC related snippets - */ - -#ifndef _POSIX_SP_BOARD_SOC_H -#define _POSIX_SP_BOARD_SOC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define TIMER_TICK_IRQ 0 -#define OFFLOAD_SW_IRQ 1 -#define COUNTER_EVENT_IRQ 2 - -/* - * This interrupt will awake the CPU if IRQs are not locked, - * This interrupt does not have an associated status bit or handler - */ -#define PHONY_WEAK_IRQ 0xFFFE -/* - * This interrupt will awake the CPU even if IRQs are locked, - * This interrupt does not have an associated status bit or handler - * (the lock is only ignored when the interrupt is raised from the HW models, - * SW threads should not try to use this) - */ -#define PHONY_HARD_IRQ 0xFFFF - - -#ifdef __cplusplus -} -#endif - -#endif /* _POSIX_SP_BOARD_SOC_H */ diff --git a/boards/native/native_posix/cmdline.c b/boards/native/native_posix/cmdline.c deleted file mode 100644 index aa0ef1e69748..000000000000 --- a/boards/native/native_posix/cmdline.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2018 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include "cmdline_common.h" -#include -#include "hw_models_top.h" -#include "timer_model.h" -#include "cmdline.h" -#include -#include -#include "native_tracing.h" - -static int s_argc, test_argc; -static char **s_argv, **test_argv; - -static struct args_struct_t *args_struct; -static int used_args; -static int args_aval; -#define ARGS_ALLOC_CHUNK_SIZE 20 - -void native_cleanup_cmd_line(void) -{ - if (args_struct != NULL) { /* LCOV_EXCL_BR_LINE */ - free(args_struct); - args_struct = NULL; - } -} - -/** - * Add a set of command line options to the program. - * - * Each option to be added is described in one entry of the input - * This input must be terminated with an entry containing ARG_TABLE_ENDMARKER. - */ -void native_add_command_line_opts(struct args_struct_t *args) -{ - int count = 0; - - while (args[count].option != NULL) { - count++; - } - count++; /*for the end marker*/ - - if (used_args + count >= args_aval) { - int growby = count; - /* reallocs are expensive let's do them only in big chunks */ - if (growby < ARGS_ALLOC_CHUNK_SIZE) { - growby = ARGS_ALLOC_CHUNK_SIZE; - } - - struct args_struct_t *new_args_struct = realloc(args_struct, - (args_aval + growby)* - sizeof(struct args_struct_t)); - args_aval += growby; - /* LCOV_EXCL_START */ - if (new_args_struct == NULL) { - posix_print_error_and_exit("Could not allocate memory"); - } else { - args_struct = new_args_struct; - } - /* LCOV_EXCL_STOP */ - } - - memcpy(&args_struct[used_args], args, - count*sizeof(struct args_struct_t)); - - used_args += count - 1; - /* - * -1 as the end marker should be overwritten next time something - * is added - */ -} - -void native_add_testargs_option(void) -{ - static struct args_struct_t testargs_options[] = { - /* - * Fields: - * manual, mandatory, switch, - * option_name, var_name ,type, - * destination, callback, - * description - */ - {true, false, false, - "testargs", "arg", 'l', - (void *)NULL, NULL, - "Any argument that follows will be ignored by the top level, " - "and made available for possible tests"}, - ARG_TABLE_ENDMARKER}; - - native_add_command_line_opts(testargs_options); -} - -static void print_invalid_opt_error(char *argv) -{ - posix_print_error_and_exit("Incorrect option '%s'. Did you misspell it?" - " Is that feature supported in this build?" - "\n", - argv); - -} - -/** - * Handle possible command line arguments. - * - * We also store them for later use by possible test applications - */ -void native_handle_cmd_line(int argc, char *argv[]) -{ - int i; - - native_add_tracing_options(); - native_add_testargs_option(); - - s_argv = argv; - s_argc = argc; - - cmd_args_set_defaults(args_struct); - - for (i = 1; i < argc; i++) { - - if ((cmd_is_option(argv[i], "testargs", 0))) { - test_argc = argc - i - 1; - test_argv = &argv[i+1]; - break; - } - - if (!cmd_parse_one_arg(argv[i], args_struct)) { - cmd_print_switches_help(args_struct); - print_invalid_opt_error(argv[i]); - } - } -} - -/** - * The application/test can use this function to inspect all the command line - * arguments - */ -void native_get_cmd_line_args(int *argc, char ***argv) -{ - *argc = s_argc; - *argv = s_argv; -} - -/** - * The application/test can use this function to inspect the command line - * arguments received after --testargs - */ -void native_get_test_cmd_line_args(int *argc, char ***argv) -{ - *argc = test_argc; - *argv = test_argv; -} diff --git a/boards/native/native_posix/cmdline.h b/boards/native/native_posix/cmdline.h deleted file mode 100644 index 05d445ddd1b7..000000000000 --- a/boards/native/native_posix/cmdline.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2018 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _NATIVE_POSIX_CMDLINE_H -#define _NATIVE_POSIX_CMDLINE_H - -#include "cmdline_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void native_handle_cmd_line(int argc, char *argv[]); -void native_get_cmd_line_args(int *argc, char ***argv); -void native_get_test_cmd_line_args(int *argc, char ***argv); -void native_add_command_line_opts(struct args_struct_t *args); -void native_cleanup_cmd_line(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _NATIVE_POSIX_CMDLINE_H */ diff --git a/boards/native/native_posix/cmdline_common.c b/boards/native/native_posix/cmdline_common.c deleted file mode 100644 index 8723505658ac..000000000000 --- a/boards/native/native_posix/cmdline_common.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2018 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include "posix_board_if.h" -#include -#include "cmdline_common.h" - -/** - * Check if is the option