Using split struct/record type with buses, e.g. AvalonMaster

[egk696]

Using structs/records for buses is the mainstream way in the industry, at least in my experience. How is it expected to use a Bus class like the AvalonMaster for records/structs?

Typically we would have a split record/struct of req and resp as shown:

typedef struct  {
  logic [CSR_SW-1:0]  sideband;
  logic [CSR_AW-1:0]  address;
  logic               write;
  logic [CSR_BW-1:0]  byteenable;
  logic [CSR_DW-1:0]  writedata;
  logic               read;
} avmm_csr_req_t;

typedef struct  {
  logic               waitrequest;
  logic [CSR_DW-1:0]  readdata;
  logic               readvalid;
} avmm_csr_resp_t;

To my understanding currently this is not supported and instead convert the bus into a single inout record and instantiate the object as follows:
avmm_csr0 = AvalonMaster(dut.csr0_slave_bus_io, "", dut.pcie0_clk)

Is there another way I am missing? Thanks for the support.