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I have a bus converted into a single inout record and instantiated the object as follows: avmm_csr0 = AvalonMaster(dut.csr0_slave_bus_io, "", dut.pcie0_clk)
However, when simulating the above, I get 'X' on address and writedata signals of the struct, until a read/write command has been issued. I believe X's should not be there. Am I using AvalonMaster wrong or is this a bug or is it expected? Thanks.
The text was updated successfully, but these errors were encountered:
I have a bus converted into a single inout record and instantiated the object as follows:
avmm_csr0 = AvalonMaster(dut.csr0_slave_bus_io, "", dut.pcie0_clk)
However, when simulating the above, I get 'X' on
address
andwritedata
signals of the struct, until a read/write command has been issued. I believe X's should not be there. Am I using AvalonMaster wrong or is this a bug or is it expected? Thanks.The text was updated successfully, but these errors were encountered: