-
Notifications
You must be signed in to change notification settings - Fork 48
Issues: chipsalliance/f4pga
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. Weβll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
How to pass Yosys defines to synthesis using
symbiflow_synth
flow
#668
opened Jun 6, 2024 by
carlosedp
Negative Edge Sensitive Events Being Uploaded as Positive Edge Sensitive Events
#667
opened Nov 14, 2023 by
WGeckle80
Why create ioplace first and then create constraints.place for Artix-7
#659
opened Aug 22, 2023 by
lgl1227
Relative paths in flow configurations are handled in respect to CWD instead of file location.
Bug
Something isn't working
f4pga (python)
Python package
#640
opened Sep 27, 2022 by
kboronski-ant
symbiflow-examples.readthedocs.io is still online
Documentation
Improvements or additions to documentation
Question
Further information is requested
SymbiFlow
Deprecated shell wrappers
#589
opened Jul 29, 2022 by
tcal-x
Merge stdm into f4pga
Enhancement
New feature or request
f4pga (python)
Python package
#556
opened May 18, 2022 by
umarcor
Documentation structure
Documentation
Improvements or additions to documentation
#555
opened May 18, 2022 by
umarcor
VHDL-synthesis using GHDL as option in addition to verific
Enhancement
New feature or request
#292
opened Jun 18, 2020 by
tmeissner
Python API documentation should be included in the Sphinx output
Documentation
Improvements or additions to documentation
Enhancement
New feature or request
f4pga (python)
Python package
#289
opened Jun 16, 2020 by
mithro
ProTip!
Updated in the last three days: updated:>2024-12-11.