From cccc4e6455272f1dfd07c5f8083724bf6be44488 Mon Sep 17 00:00:00 2001 From: Ivor Wanders Date: Mon, 27 Jan 2025 20:14:11 -0500 Subject: [PATCH] IR documentation improvements and improve debug assert (#10130) * Cranelift/x64 backend: improve pointer width assert. (#10118) This adds additional information as to what is wrong when this assert is encountered. * Cranelift/docs: Change pointer width in ir docs to 64 bits (#10118) Most people using this example will likely be on 64 bit systems, so it makes sense to target a system with 64 bit addressses with the example. --- cranelift/codegen/src/isa/x64/lower.rs | 7 ++++++- cranelift/docs/ir.md | 10 +++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index ae780089d4c5..eea24464a443 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -230,7 +230,12 @@ fn lower_to_amode(ctx: &mut Lower, spec: InsnInput, offset: i32) -> Amode // We now either have an add that we must materialize, or some other input; as well as the // final offset. if let Some(add) = matches_input(ctx, spec, Opcode::Iadd) { - debug_assert_eq!(ctx.output_ty(add, 0), types::I64); + let output_ty = ctx.output_ty(add, 0); + debug_assert_eq!( + output_ty, + types::I64, + "Address width of 64 expected, got {output_ty}" + ); let add_inputs = &[ InsnInput { insn: add, diff --git a/cranelift/docs/ir.md b/cranelift/docs/ir.md index 907a984baa2c..8f9b26480221 100644 --- a/cranelift/docs/ir.md +++ b/cranelift/docs/ir.md @@ -37,24 +37,24 @@ float average(const float *array, size_t count) } ``` -Here is the same function compiled into Cranelift IR: +Here is the same function compiled into Cranelift IR (with 64 bit pointers): ``` test verifier -function %average(i32, i32) -> f32 system_v { +function %average(i64, i64) -> f32 system_v { ss0 = explicit_slot 8 ; Stack slot for `sum`. -block1(v0: i32, v1: i32): +block1(v0: i64, v1: i64): v2 = f64const 0x0.0 stack_store v2, ss0 brif v1, block2, block5 ; Handle count == 0. block2: - v3 = iconst.i32 0 + v3 = iconst.i64 0 jump block3(v3) -block3(v4: i32): +block3(v4: i64): v5 = imul_imm v4, 4 v6 = iadd v0, v5 v7 = load.f32 v6 ; array[i]