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fpga_graphics_adapter.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 00:48:22 April 09, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# fpga_graphics_adapter_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY fpga_graphics_adapter
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:48:22 APRIL 09, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_AB16 -to cs
set_location_assignment PIN_AB13 -to data_bi[7]
set_location_assignment PIN_AA16 -to wren
set_location_assignment PIN_AA15 -to rs[3]
set_location_assignment PIN_AB15 -to rs[2]
set_location_assignment PIN_AA14 -to rs[1]
set_location_assignment PIN_AB14 -to rs[0]
set_location_assignment PIN_AA13 -to data_bi[6]
set_location_assignment PIN_AB10 -to data_bi[5]
set_location_assignment PIN_AA10 -to data_bi[4]
set_location_assignment PIN_AB8 -to data_bi[3]
set_location_assignment PIN_AA8 -to data_bi[2]
set_location_assignment PIN_AB5 -to data_bi[1]
set_location_assignment PIN_AA5 -to data_bi[0]
set_location_assignment PIN_U7 -to clk_ext1
set_location_assignment PIN_K18 -to b_vga_o[3]
set_location_assignment PIN_J22 -to b_vga_o[2]
set_location_assignment PIN_K21 -to b_vga_o[1]
set_location_assignment PIN_K22 -to b_vga_o[0]
set_location_assignment PIN_G21 -to clk
set_location_assignment PIN_J21 -to g_vga_o[3]
set_location_assignment PIN_K17 -to g_vga_o[2]
set_location_assignment PIN_J17 -to g_vga_o[1]
set_location_assignment PIN_H22 -to g_vga_o[0]
set_location_assignment PIN_L21 -to h_sync_o
set_location_assignment PIN_H21 -to r_vga_o[3]
set_location_assignment PIN_H20 -to r_vga_o[2]
set_location_assignment PIN_H17 -to r_vga_o[1]
set_location_assignment PIN_H19 -to r_vga_o[0]
set_location_assignment PIN_L22 -to v_sync_o
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE mlbmp_ctrl.v
set_global_assignment -name VERILOG_FILE fpga_graphics_adapter.v
set_global_assignment -name QIP_FILE vga_clk.qip
set_global_assignment -name QIP_FILE screen_ram.qip
set_global_assignment -name QIP_FILE f_clock.qip
set_global_assignment -name QIP_FILE vga_clock.qip
set_global_assignment -name VERILOG_FILE mtxt_ctrl.v
set_global_assignment -name QIP_FILE chr_rom.qip
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name VERILOG_FILE ctxt_ctrl.v
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE commands.v
set_global_assignment -name VERILOG_FILE mmbmp_ctrl.v
set_global_assignment -name VERILOG_FILE clbmp_ctrl.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top