RISC-V

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More to follow

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I'm starting with some RISC-V targets from the QingKe V4 series from WCH, and the WCH-LinkE debug tool.

First set of targets that I want to support:

Target
CH32X035C8T6
CH32X035R8T6
CH32X035G8U6
CH32X035G8R6
CH32X035F8U6

That list will likely grow before the next release.

I've made a lot of progress on this over the last few weeks. The WCH-LinkE debug tool driver is complete. The generic RISC-V target driver (implementing the RISC-V debug specification) is almost complete.

But there's a lot more to do:

• Support for hardware and software breakpoints in RISC-V target driver
• Support for pin state retrieval and manipulation in RISC-V target driver (this is low priority, may drop it)
• Make AVR8 TDF format more generic, to accommodate targets from other families. This includes refactoring TDF validation scripts
• RISC-V GDB server
• Refactor memory inspection pane initialisation in the Insight GUI, to accommodate additional memory regions
• Website/documentation updates
• A lot of testing

There are some limitations in the RISC-V debug spec implementation that I want to note here:

• It only supports debugging a single RISC-V hart at a time. I don't think this will be much of a problem, as most RISC-V MCUs only have a single RISC-V hart.
• I've assumed all supported targets support register and memory access via abstract commands. This checks out for now (with all the QingKe V4 targets), but may need revisiting at a later date, when I add support for other RISC-V targets.

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My time will be much more limited from tomorrow onwards, so development will slow down significantly, but I'd like to include RISC-V support in the next feature release (v1.1.0). No idea when that will be.

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Quick update on this:

I've spent a number of months revising Bloom's TDF format, so that it can better accommodate targets from other families. This includes refactoring all TDF processing build scripts and updating all 260 AVR8 TDFs to conform to the new format, which was a mammoth task.

The next step is to refactor Bloom's TDF parsing code to support the new format. Then I'll be creating new TDFs for the WCH RISC-V targets listed in the previous comment.

There's still a lot more to do, but I'm getting through it. Still hoping to introduce RISC-V support in v1.1.0. Still have no idea when it will be ready.

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Quick update on this:

I have completed the TDF work and refactored Bloom's codebase (excluding the Insight GUI) to accommodate the new TDF format, and RISC-V targets.

I have also begun work on the first TDF for a WCH RISC-V target, which is working pretty well with the testing that I've done so far.

There's still a lot to do:

• Insight GUI refactor
• RISC-V GDB server
• Support for hardware and software breakpoints in RISC-V target driver
• Website/documentation updates (have made good progress on this)
• A lot of testing

With the refactor complete, I'm hoping the remaining work won't take as long to do, but we'll see.

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Quick update on this:

• Support for RISC-V hardware breakpoints is complete
• Insight GUI refactor is almost complete, just the register pane that needs some work.
• Have made progress with the RISC-V GDB server. Program flow control works well, as does memory access.

There's a fair bit more to do, but I'm making good progress.

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Quick update on this:

• RISC-V GDB server is complete.
• Support for programming RISC-V targets is complete