resume_short.tex

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% Personal Resume
% Author: Brendan Long
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% Create from template:
% LaTeX Template
% Version 2.0 (8/5/13)
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% This template has been downloaded from:
% http://www.LaTeXTemplates.com
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% Original author:
% Trey Hunner (http://www.treyhunner.com/)
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% Important note:
% This template requires the resume.cls file to be in the same directory as the
% .tex file. The resume.cls file provides the resume style used for structuring the
% document.
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%	PACKAGES AND OTHER DOCUMENT CONFIGURATIONS
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\documentclass{resume} % Use the custom resume.cls style

\usepackage[left=0.75in,top=0.6in,right=0.75in,bottom=0.6in]{geometry} % Document margins

\name{Brendan Long} % Your name
\address{(512)~$\cdot$~299~$\cdot$~2285 \\ bccbrendan@gmail.com}
\address{https://github.com/bccbrendan}

\begin{document}

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%	TECHNICAL STRENGTHS SECTION
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\begin{rSection}{Technical Strengths}

\begin{tabular}{ @{} >{\bfseries}l @{\hspace{6ex}} l }
Skills & Process evolution through CI/CD, mentoring, training, on-boarding documentation \\
Languages& C++, Python, Rust, C, C\# \\
Technology& boost, asio, gsl, gtest, CMake, I3C, UART, SPI, JTAG, XML, flatbuffers, JSON \\
Tools& Git, Conan, Coverity, Simics, valgrind, CI/CD (Jenkins, GitHub Actions)
\end{tabular}

\end{rSection}

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%	WORK EXPERIENCE SECTION
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\begin{rSection}{Experience}

\begin{rSubsection}{Intel}{2023 - Present}{Staff Software Engineer}{Austin, TX}
\item Mentor and train engineers on multiple global teams through group training and pair programming
\item Curate team work backlog, matching tasks to developers' individual strengths
\item Set up and manage automatic static code analysis for security, drove reduction of open issues by 90\%
\item DRA for resolving debug tool and silicon integration problems in 3 next-gen server products, and identifying prevention strategies
\item 2023 Project awards for successful silicon power-on, for enabling debug tools in record time, and for executing silicon validation test plan 8 weeks ahead of schedule
\end{rSubsection}

\begin{rSubsection}{Intel}{May 2019 - 2023}{Senior Software Developer}{Austin, TX}
\item Led team transition to Git through automated migration process, administration, and team trainings
\item Gathered requirements and led development of debug tools, adapting to new architectures and debug protocols - multiple DRAs and two Project awards
\item As product owner for pre-silicon debug tools, gathered requirements, planned features, and balanced work priorities of a team to deliver tools across the entire product roadmap
\item Led several multi-team sessions on Git and silicon debug technologies. Received 2021 SRA for on-boarding new overseas team
\item Ported debug tool software and custom embedded hardware to Raspberry Pi by for significant savings
\item Developed and verified debug tools and supported record time power-on of discrete graphics product
\item Delivered debug tools for next-gen server cpu with exceptional stability - Q1'2019 DRA
\end{rSubsection}

\begin{rSubsection}{Intel}{June 2012 - April 2019}{Software Developer}{Austin, TX}
\item Designed and developed software libraries bridging silicon debug software to pre-silicon emulation models in every market segment. Received 3 DRAs and one Special Recognition Award
\item Created in-house software replacement for 3rd party probes, saving \$5.75M - DRA and SRA
\item Developed key features of debug tools using Intel's Direct Connect Interrface technology
\item Drove company-wide adoption of 3rd party debug tools by developing seamless compatibility software for existing use cases. Created and provided training for new tools. Received Q2'13 Transformation Award, Q3'13 DRA, Q4'14 DRA, and Q4'14 ``Above and Beyond'' SRA
\end{rSubsection}
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\end{rSection}

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%	EDUCATION SECTION
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\begin{rSection}{Education}

{\bf University of Texas, Austin}  \\ 
M.S. in Software Engineering; B.S. in Electrical and Computer Engineering \\

\end{rSection}



\end{document}