cl_dram_hbm_dma builds but running the way the tutorial says produces "unable to open read dma queue"

[dsw]

I loaded the FPGA with my compiled verilog and confirmed that it was loaded, but it does not run.

I am very carefully following these instructions: https://github.com/aws/aws-fpga/blob/f2/hdk/README.md

$ ./load_aws_fpga_image.sh 
AFI          0       agfi-0c0272c37d36a7915  loaded            0        ok               0       0x10212415
AFIDEVICE    0       0x1d0f      0xf001      0000:34:00.0

$ sudo fpga-describe-local-image -S 0 -H
Type  FpgaImageSlot  FpgaImageId             StatusName    StatusCode   ErrorName    ErrorCode   ShVersion
AFI          0       agfi-0c0272c37d36a7915  loaded            0        ok               0       0x10212415
Type  FpgaImageSlot  VendorId    DeviceId    DBDF
AFIDEVICE    0       0x1d0f      0xf001      0000:34:00.0

And then these instructions: https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma

$ cd aws-fpga/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/

$ make
gcc -DCONFIG_LOGLEVEL=4 -std=gnu11 -g -Wall -Werror -I/home/ubuntu/aws-fpga/sdk/userspace/include   -c -o test_dram_dma_common.o test_dram_dma_common.c
gcc -DCONFIG_LOGLEVEL=4 -std=gnu11 -g -Wall -Werror -I/home/ubuntu/aws-fpga/sdk/userspace/include   -c -o test_dram_hbm_dma.o test_dram_hbm_dma.c
gcc -DCONFIG_LOGLEVEL=4 -std=gnu11 -g -Wall -Werror -I/home/ubuntu/aws-fpga/sdk/userspace/include   -c -o test_dram_dma_hwsw_cosim.o test_dram_dma_hwsw_cosim.c
gcc -DCONFIG_LOGLEVEL=4 -std=gnu11 -g -Wall -Werror -I/home/ubuntu/aws-fpga/sdk/userspace/include -o test_dram_hbm_dma test_dram_hbm_dma.o test_dram_dma_common.o   -lfpga_mgmt
gcc -DCONFIG_LOGLEVEL=4 -std=gnu11 -g -Wall -Werror -I/home/ubuntu/aws-fpga/sdk/userspace/include -o test_dram_dma_hwsw_cosim test_dram_dma_hwsw_cosim.o test_dram_dma_common.o  -lfpga_mgmt

However it does not work.

$ sudo ./test_dram_hbm_dma
2025-09-02T00:34:07.475012Z, test_dram_hbm_dma, ERROR, test_dram_hbm_dma.c +124: dma_example(): unable to open read dma queue
2025-09-02T00:34:07.475059Z, test_dram_hbm_dma, ERROR, test_dram_hbm_dma.c +83: main(): DMA example failed
2025-09-02T00:34:07.475068Z, test_dram_hbm_dma, INFO, test_dram_hbm_dma.c +97: main(): TEST FAILED

Now the code does attempt to read a slot_id from the command line, which the instructions do not say to proivde:

int main(int argc, char **argv) {                                               
    int rc;                                                                     
    int slot_id = 0;                                                            
    // int interrupt_n;                                                         
                                                                                
    switch (argc) {                                                             
    case 1:                                                                     
        break;                                                                  
    case 3:                                                                     
        sscanf(argv[2], "%x", &slot_id);                                        
        break;                                                                  

So that means that it is defaulting to slot_id = 0, but given that case 1 above does not error, that seems to be simply the default.

Any suggestions please?

[mjthimm]

Hi Daniel,

This example, cl_dram_hbm_dma, depends on having a DMA engine implemented within the design. Once the XDMA shell becomes available, you can build this design with it and these software runtime examples will work without any extra effort.

Have you chosen to implement your own DMA engine in this design? If not, I'd recommend taking a look at cl_sde, which shows how to use our Streaming Data Engine (SDE) as a DMA engine. From there, you could meld the two designs.

Please let me know if this helps and if you have any other questions.

Best,
Max

[dsw]

The instructions for your example do not seem to say that, unless I missed it. You really need a simpler hello world example. Is there a hello world example somewhere that looks like the CPU host and the Verilog guest calling back and forth into one another? All I want is the same experience you get with Verilator https://www.veripool.org/verilator/ as follows: Verilator compiles Verilog to C++ and then host C++ code can synchronously call into the top module of the Verilator-generated code on the FPGA, which can then return to the host. I implemented a simple protocol for doing the synchronous handoff between guest and host that works if guest and host just have shared memory so they can talk through the ports of the top module. Is there some example where you show how to set up the ports of the top Verilog module to be mapped to shared memory?

…

On Tue, Sep 2, 2025 at 7:12 AM Maxwell Thimmig ***@***.***> wrote: *mjthimm* left a comment (aws/aws-fpga#744) <#744 (comment)> Hi Daniel, This example, cl_dram_hbm_dma, depends on having a DMA engine implemented within the design. Once the XDMA shell becomes available, you can build this design with it and these software runtime examples will work without any extra effort. Have you chosen to implement your own DMA engine in this design? If not, I'd recommend taking a look at cl_sde, which shows how to use our Streaming Data Engine (SDE) as a DMA engine. From there, you could meld the two designs. Please let me know if this helps and if you have any other questions. Best, Max — Reply to this email directly, view it on GitHub <#744 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAAL6XCAKC3XBRNIZPYNPGT3QWQU5AVCNFSM6AAAAACFI2VV3WVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTENBVGUZTEMBVHE> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[dsw]

Looking at your template instructions: https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/CL_TEMPLATE

It says this:

STEP 4: Develop Software Tests (OPTIONAL)

CL_TEMPLATE does not yet support standalone software tests. Please refer to other examples such as CL_DRAM_HBM_DMA

Which refers to the test that you just said does not work.

Again, how do I find a simple hello world example that allows a C++ host on the CPU to talk to a Verilog guest through the ports of the top module of the Verilog?

[mjthimm]

Hi Daniel,

The best example to look at for a simple show of the Host (CPU) talking to the Verilog guest (FPGA) would be through the Clock Generation example here

Specifically, this example uses the OCL interface to have the Host communicate with the FPGA.

You can build the cl_mem_perf example, load the AFI onto the FPGA, then run this example to see the host communicating with the FPGA. This does not require the XDMA shell.

We will add verbiage to the FPGA Developer Kit to let customers know that this is the simplest example of the Host and the FPGA communicating.

Also, your feedback about a hello world example has been taken by the AWS F2 team.

Best,
Max

[dsw]

What would be super helpful would be to do the following: Provide a simple hello world Verilog program doing something simple that uses all the basic features: input, output, registers, memories. I have one that just lets me read and write a register file. (1) Show compiling and running it using Verilator. Verilator compiles Verilog to C++ such that there is a C++ function that has the same signature as the top module of the Verilog. You then just write a C++ program that loops calling into that top module function once for each cycle. This is very intuitive. (2) Show a way to then get exactly the same experience compiling and running it using F2 as you do with Verilator. That is, provide some Makefile that has a configuration variable that says BACKEND=VERILATOR or BACKEND=F2 but otherwise allows you to keep your source tree the same.

…

On Thu, Sep 4, 2025 at 10:13 AM Maxwell Thimmig ***@***.***> wrote: *mjthimm* left a comment (aws/aws-fpga#744) <#744 (comment)> Hi Daniel, The best example to look at for a simple show of the Host (CPU) talking to the Verilog guest (FPGA) would be through the Clock Generation example here <https://github.com/aws/aws-fpga/blob/f2/hdk/cl/examples/cl_mem_perf/software/runtime/test_aws_clk_gen.c> Specifically, this example uses the OCL interface to have the Host communicate with the FPGA. You can build the cl_mem_perf example, load the AFI onto the FPGA, then run this example to see the host communicating with the FPGA. This does not require the XDMA shell. We will add verbiage to the FPGA Developer Kit to let customers know that this is the simplest example of the Host and the FPGA communicating. Also, your feedback about a hello world example has been taken by the AWS F2 team. Best, Max — Reply to this email directly, view it on GitHub <#744 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAAL6XHXMOZ7KD4EPZXGXXT3RBXMFAVCNFSM6AAAAACFI2VV3WVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTENJUGY3TCMZYG4> . You are receiving this because you authored the thread.Message ID: ***@***.***>