chore: code fmt (#3)

* chore: code fmt

* chore: update dependencies and remove unused patches

Author: ZR233

src/address_space/mod.rs

@@ -20,8 +20,9 @@ use memory_addr::{MemoryAddr, PhysAddr, is_aligned_4k};
 use memory_set::{MemoryArea, MemorySet};
 use page_table_multiarch::PagingHandler;
 
-use crate::npt::NestedPageTable as PageTable;
-use crate::{GuestPhysAddr, GuestPhysAddrRange, mapping_err_to_ax_err};
+use crate::{
+    GuestPhysAddr, GuestPhysAddrRange, mapping_err_to_ax_err, npt::NestedPageTable as PageTable,
+};
 
 mod backend;
 
@@ -183,7 +184,7 @@ impl<H: PagingHandler> AddrSpace<H> {
         }
         self.pt
             .query(vaddr)
-            .map(|(phys_addr, _, _)| {
+            .map(|(phys_addr, ..)| {
                 debug!("vaddr {vaddr:?} translate to {phys_addr:?}");
                 phys_addr
             })
@@ -252,7 +253,7 @@ impl<H: PagingHandler> AddrSpace<H> {
         if let Some(area) = self.areas.find(vaddr) {
             self.pt
                 .query(vaddr)
-                .map(|(phys_addr, _, _)| (phys_addr, area.size()))
+                .map(|(phys_addr, ..)| (phys_addr, area.size()))
                 .ok()
         } else {
             None
@@ -278,13 +279,15 @@ impl<H: PagingHandler> Drop for AddrSpace<H> {
 
 #[cfg(test)]
 mod tests {
+    use core::sync::atomic::Ordering;
+
+    use axin::axin;
+
     use super::*;
     use crate::test_utils::{
         ALLOC_COUNT, BASE_PADDR, DEALLOC_COUNT, MEMORY_LEN, MockHal, mock_hal_test,
         test_dealloc_count,
     };
-    use axin::axin;
-    use core::sync::atomic::Ordering;
 
     /// Generate an address space for the test
     fn setup_test_addr_space() -> (AddrSpace<MockHal>, GuestPhysAddr, usize) {

src/device/device_addr.rs

@@ -16,9 +16,8 @@ use core::fmt::LowerHex;
 
 use memory_addr::AddrRange;
 
-use crate::GuestPhysAddr;
-
 use super::{Port, SysRegAddr};
+use crate::GuestPhysAddr;
 
 /// An address-like type that can be used to access devices.
 pub trait DeviceAddr: Copy + Eq + Ord + core::fmt::Debug {}

src/frame.rs

@@ -15,7 +15,6 @@
 use core::marker::PhantomData;
 
 use axerrno::{AxResult, ax_err_type};
-
 pub(crate) use memory_addr::PAGE_SIZE_4K as PAGE_SIZE;
 
 use crate::{AxMmHal, HostPhysAddr};
@@ -89,12 +88,14 @@ impl<H: AxMmHal> Drop for PhysFrame<H> {
 
 #[cfg(test)]
 mod test {
-    use super::*;
-    use crate::test_utils::{BASE_PADDR, MockHal, mock_hal_test, test_dealloc_count};
     use alloc::vec::Vec;
+
     use assert_matches::assert_matches;
     use axin::axin;
 
+    use super::*;
+    use crate::test_utils::{BASE_PADDR, MockHal, mock_hal_test, test_dealloc_count};
+
     #[test]
     #[axin(decorator(mock_hal_test), on_exit(test_dealloc_count(1)))]
     fn test_alloc_dealloc_cycle() {

src/lib.rs

@@ -31,13 +31,10 @@ mod npt;
 
 pub use addr::*;
 pub use address_space::*;
-
+use axerrno::AxError;
 pub use frame::PhysFrame;
 pub use hal::AxMmHal;
-
 pub use memory_accessor::GuestMemoryAccessor;
-
-use axerrno::AxError;
 use memory_set::MappingError;
 
 /// Information about nested page faults.

src/memory_accessor.rs

@@ -17,10 +17,11 @@
 //! This module provides a safe and consistent way to access guest memory
 //! from VirtIO device implementations, handling address translation and
 //! memory safety concerns.
-use crate::GuestPhysAddr;
 use axerrno::{AxError, AxResult};
 use memory_addr::PhysAddr;
 
+use crate::GuestPhysAddr;
+
 /// A stateful accessor to the memory space of a guest
 pub trait GuestMemoryAccessor {
     /// Translate a guest physical address to host physical address and get access limit
@@ -200,11 +201,12 @@ pub trait GuestMemoryAccessor {
 
 #[cfg(test)]
 mod tests {
-    use super::*;
-    use crate::test_utils::{BASE_PADDR, mock_hal_test};
     use axin::axin;
     use memory_addr::PhysAddr;
 
+    use super::*;
+    use crate::test_utils::{BASE_PADDR, mock_hal_test};
+
     /// Mock implementation of GuestMemoryAccessor for testing
     struct MockTranslator {
         base_addr: PhysAddr,

src/npt/arch/aarch64.rs

@@ -12,10 +12,11 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-use core::arch::asm;
-use core::fmt;
+use core::{arch::asm, fmt};
+
 use page_table_entry::{GenericPTE, MappingFlags};
 use page_table_multiarch::PagingMetaData;
+
 // use memory_addr::HostPhysAddr;
 use crate::{GuestPhysAddr, HostPhysAddr};
 
@@ -72,8 +73,8 @@ bitflags::bitflags! {
 #[repr(u64)]
 #[derive(Debug, Clone, Copy, Eq, PartialEq)]
 enum MemType {
-    Device = 0,
-    Normal = 1,
+    Device         = 0,
+    Normal         = 1,
     NormalNonCache = 2,
 }
 

src/npt/mod.rs

@@ -192,6 +192,6 @@ impl<H: PagingHandler> NestedPageTable<H> {
 
     /// Translates a virtual address to a physical address.
     pub fn translate(&self, vaddr: crate::GuestPhysAddr) -> Option<crate::HostPhysAddr> {
-        self.query(vaddr).ok().map(|(paddr, _, _)| paddr)
+        self.query(vaddr).ok().map(|(paddr, ..)| paddr)
     }
 }

src/test_utils/mod.rs

@@ -12,14 +12,14 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-use crate::{AxMmHal, HostPhysAddr, HostVirtAddr};
 use core::sync::atomic::{AtomicBool, AtomicUsize, Ordering};
+
 use lazy_static::lazy_static;
-use memory_addr::{PhysAddr, VirtAddr};
+use memory_addr::{PAGE_SIZE_4K as PAGE_SIZE, PhysAddr, VirtAddr};
 use page_table_multiarch::PagingHandler;
 use spin::Mutex;
 
-use memory_addr::PAGE_SIZE_4K as PAGE_SIZE;
+use crate::{AxMmHal, HostPhysAddr, HostVirtAddr};
 
 /// The starting physical address for the simulated memory region in tests.
 /// This offset is used to map simulated physical addresses to the `MEMORY` array's virtual address space.