@@ -83,7 +83,15 @@ enum max14001_chip_model {
8383
8484struct max14001_chip_info {
8585 const char * name ;
86- /* TODO: Add more information */
86+ };
87+
88+ struct max14001_state {
89+ struct spi_device * spi ;
90+ const struct max14001_chip_info * chip_info ;
91+ int vref_mv ;
92+
93+ __be16 rx_buffer __aligned (IIO_DMA_MINALIGN );
94+ __be16 tx_buffer ;
8795};
8896
8997static struct max14001_chip_info max14001_chip_info_tbl [] = {
@@ -95,129 +103,41 @@ static struct max14001_chip_info max14001_chip_info_tbl[] = {
95103 },
96104};
97105
98- struct max14001_state {
99- struct spi_device * spi ;
100- const struct max14001_chip_info * chip_info ;
101- int vref_mv ;
102- };
103-
104106static int max14001_spi_read (struct max14001_state * st , u16 reg , int * val )
105107{
106- u16 rx , tx = 0 ;
107- int ret ;
108-
109- tx |= FIELD_PREP (MAX14001_MASK_ADDR , reg );
110- tx |= FIELD_PREP (MAX14001_MASK_WR , MAX14001_REG_READ );
111- tx = bitrev16 (tx );
108+ int ret = 0 ;
112109
113110 struct spi_transfer xfer [] = {
114111 {
115- .tx_buf = & tx ,
116- .len = sizeof (tx ),
112+ .tx_buf = & st -> tx_buffer ,
113+ .len = sizeof (st -> tx_buffer ),
117114 .bits_per_word = 16 ,
118115 .cs_change = 1 ,
119116 },
120117 {
121- .rx_buf = & rx ,
122- .len = sizeof (rx ),
118+ .rx_buf = & st -> rx_buffer ,
119+ .len = sizeof (st -> rx_buffer ),
123120 .bits_per_word = 16 ,
124121 },
125122 };
126- ret = spi_sync_transfer (st -> spi , xfer , ARRAY_SIZE (xfer ));
127-
128- rx = bitrev16 (rx );
129- * val = FIELD_GET (MAX14001_MASK_DATA , rx );
130123
131- return ret ;
132- }
133-
134- static int max14001_spi_write (struct max14001_state * st , u16 reg , u16 val )
135- {
136- u16 tx = 0 ;
137- int ret ;
138-
139- tx |= FIELD_PREP (MAX14001_MASK_ADDR , reg );
140- tx |= FIELD_PREP (MAX14001_MASK_WR , MAX14001_REG_WRITE );
141- tx |= FIELD_PREP (MAX14001_MASK_DATA , val );
142- tx = bitrev16 (tx );
143-
144- struct spi_transfer xfer [] = {
145- {
146- .tx_buf = & tx ,
147- .len = sizeof (tx ),
148- .bits_per_word = 16 ,
149- },
150- };
124+ st -> tx_buffer = FIELD_PREP (MAX14001_MASK_ADDR , reg );
125+ st -> tx_buffer |= FIELD_PREP (MAX14001_MASK_WR , MAX14001_REG_READ );
126+ st -> tx_buffer = bitrev16 (st -> tx_buffer );
151127
152128 ret = spi_sync_transfer (st -> spi , xfer , ARRAY_SIZE (xfer ));
153129 if (ret < 0 )
154130 return ret ;
155131
156- return ret ;
157- }
158-
159- static int max14001_spi_write_single_reg (struct max14001_state * st , u16 reg , u16 val )
160- {
161- int ret ;
162-
163- /* Enable register write */
164- ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_ENABLE );
165- if (ret < 0 )
166- return ret ;
167-
168- /* Write data into register */
169- ret = max14001_spi_write (st , reg , val );
170- if (ret < 0 )
171- return ret ;
172-
173- /* Disable register write */
174- ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_DISABLE );
175- if (ret < 0 )
176- return ret ;
177-
178- return ret ;
179- }
180-
181- static int max14001_set_verification_registers_values (struct max14001_state * st )
182- {
183- struct device * dev = & st -> spi -> dev ;
184- int i , val_read_reg , ret ;
185- u16 val_write_reg ;
186-
187- /* Enable register write */
188- ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_ENABLE );
189- if (ret < 0 )
190- goto erro_condition ;
191-
192- for (i = MAX14001_REG_FLTEN ; i <= MAX14001_REG_ENBL ; i ++ ) {
193- /* Read register value */
194- val_read_reg = 0 ;
195- ret = max14001_spi_read (st , i , & val_read_reg );
196- if (ret < 0 )
197- goto erro_condition ;
198-
199- /* Write verification register value */
200- val_write_reg = (u16 )val_read_reg ;
201- ret = max14001_spi_write (st , MAX14001_REG_VERIFICATION (i ), val_write_reg );
202- if (ret < 0 )
203- goto erro_condition ;
204- }
205-
206- /* Disable register write */
207- ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_DISABLE );
208- if (ret < 0 )
209- goto erro_condition ;
132+ st -> rx_buffer = bitrev16 (st -> rx_buffer );
133+ * val = FIELD_GET (MAX14001_MASK_DATA , st -> rx_buffer );
210134
211135 return ret ;
212-
213- erro_condition :
214- return dev_err_probe (dev , ret , "Failed to set verification registers\n" );
215-
216136}
217137
218138static int max14001_read_raw (struct iio_dev * indio_dev ,
219- struct iio_chan_spec const * chan ,
220- int * val , int * val2 , long mask )
139+ struct iio_chan_spec const * chan ,
140+ int * val , int * val2 , long mask )
221141{
222142 struct max14001_state * st = iio_priv (indio_dev );
223143 int ret ;
@@ -249,7 +169,7 @@ static const struct iio_info max14001_info = {
249169 .read_raw = max14001_read_raw ,
250170};
251171
252- static const struct iio_chan_spec max14001_channel_voltage [] = {
172+ static const struct iio_chan_spec max14001_channel [] = {
253173 {
254174 .type = IIO_VOLTAGE ,
255175 .indexed = 1 ,
@@ -260,31 +180,19 @@ static const struct iio_chan_spec max14001_channel_voltage[] = {
260180 }
261181};
262182
263- static const struct iio_chan_spec max14001_channel_current [] = {
264- {
265- .type = IIO_CURRENT ,
266- .indexed = 1 ,
267- .channel = 0 ,
268- .info_mask_separate = BIT (IIO_CHAN_INFO_RAW ) |
269- BIT (IIO_CHAN_INFO_AVERAGE_RAW ) |
270- BIT (IIO_CHAN_INFO_SCALE ),
271- }
272- };
273-
274183static int max14001_probe (struct spi_device * spi )
275184{
276185 const struct max14001_chip_info * info ;
277186 struct device * dev = & spi -> dev ;
278187 struct max14001_state * st ;
279188 struct iio_dev * indio_dev ;
280189 int ret ;
281- bool current_channel = false;
282190
283191 info = spi_get_device_match_data (spi );
284192 if (!dev )
285193 return dev_err_probe (dev , - ENODEV , "Failed to get match data\n" );
286194
287- indio_dev = devm_iio_device_alloc (& spi -> dev , sizeof (* st ));
195+ indio_dev = devm_iio_device_alloc (dev , sizeof (* st ));
288196 if (!indio_dev )
289197 return - ENOMEM ;
290198
@@ -295,6 +203,8 @@ static int max14001_probe(struct spi_device *spi)
295203 indio_dev -> name = st -> chip_info -> name ;
296204 indio_dev -> modes = INDIO_DIRECT_MODE ;
297205 indio_dev -> info = & max14001_info ;
206+ indio_dev -> channels = max14001_channel ;
207+ indio_dev -> num_channels = ARRAY_SIZE (max14001_channel );
298208
299209 ret = devm_regulator_get_enable (dev , "vdd" );
300210 if (ret )
@@ -305,27 +215,12 @@ static int max14001_probe(struct spi_device *spi)
305215 return dev_err_probe (dev , ret , "Failed to enable specified Vddl supply\n" );
306216
307217 ret = devm_regulator_get_enable_read_voltage (dev , "vrefin" );
308- if (ret < 0 ) {
218+ if (ret < 0 )
309219 st -> vref_mv = 1250000 / 1000 ;
310- } else {
220+ else
311221 st -> vref_mv = ret / 1000 ;
312- }
313-
314- current_channel = device_property_read_bool (dev , "current-channel" );
315- if (current_channel ) {
316- indio_dev -> channels = max14001_channel_current ;
317- indio_dev -> num_channels = ARRAY_SIZE (max14001_channel_current );
318- } else {
319- indio_dev -> channels = max14001_channel_voltage ;
320- indio_dev -> num_channels = ARRAY_SIZE (max14001_channel_voltage );
321- }
322-
323- /* Write the appropriate verification registers values to clear the
324- * failed memory validation (MV Fault)
325- */
326- max14001_set_verification_registers_values (st );
327222
328- return devm_iio_device_register (& spi -> dev , indio_dev );
223+ return devm_iio_device_register (dev , indio_dev );
329224}
330225
331226static const struct spi_device_id max14001_id_table [] = {
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