1+ // SPDX-License-Identifier: GPL-2.0-only
2+ /*
3+ * MAX14001/MAX14002 SPI ADC driver
4+ *
5+ * Copyright (c) 2025 Marilene Andrade Garcia <[email protected] > 6+ *
7+ * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf
8+ */
9+
10+ #include <asm/unaligned.h>
11+ #include <linux/bitfield.h>
12+ #include <linux/bitrev.h>
13+ #include <linux/module.h>
14+ #include <linux/spi/spi.h>
15+ #include <linux/iio/iio.h>
16+ #include <linux/of.h>
17+
18+ /* MAX14001 registers definition */
19+ #define MAX14001_REG_ADC 0x00
20+ #define MAX14001_REG_FADC 0x01
21+ #define MAX14001_REG_FLAGS 0x02
22+ #define MAX14001_REG_FLTEN 0x03
23+ #define MAX14001_REG_THL 0x04
24+ #define MAX14001_REG_THU 0x05
25+ #define MAX14001_REG_INRR 0x06
26+ #define MAX14001_REG_INRT 0x07
27+ #define MAX14001_REG_INRP 0x08
28+ #define MAX14001_REG_CFG 0x09
29+ #define MAX14001_REG_ENBL 0x0A
30+ #define MAX14001_REG_ACT 0x0B
31+ #define MAX14001_REG_WEN 0x0C
32+
33+ /* MAX14001 verification registers definition */
34+ #define MAX14001_REG_VERIFICATION (x ) (0x10 + (x))
35+ #define MAX14001_REG_FLTV 0x13
36+ #define MAX14001_REG_THLV 0x14
37+ #define MAX14001_REG_THUV 0x15
38+ #define MAX14001_REG_INRRV 0x16
39+ #define MAX14001_REG_INRTV 0x17
40+ #define MAX14001_REG_INRPV 0x18
41+ #define MAX14001_REG_CFGV 0x19
42+ #define MAX14001_REG_ENBLV 0x1A
43+
44+ /* MAX14001 CONTROL values*/
45+ #define MAX14001_REG_WRITE 0x1
46+ #define MAX14001_REG_READ 0x0
47+
48+ /* MAX14001 MASKS */
49+ #define MAX14001_MASK_ADDR GENMASK(15,11)
50+ #define MAX14001_MASK_WR BIT(10)
51+ #define MAX14001_MASK_DATA GENMASK(9,0)
52+
53+ /* MAX14001_REG_FLAGS MASKS */
54+ #define MAX14001_MASK_FLAGS_ADC BIT(1)
55+ #define MAX14001_MASK_FLAGS_INRD BIT(2)
56+ #define MAX14001_MASK_FLAGS_SPI BIT(3)
57+ #define MAX14001_MASK_FLAGS_COM BIT(4)
58+ #define MAX14001_MASK_FLAGS_CRCL BIT(5)
59+ #define MAX14001_MASK_FLAGS_CRCF BIT(6)
60+ #define MAX14001_MASK_FLAGS_FET BIT(7)
61+ #define MAX14001_MASK_FLAGS_MV BIT(8)
62+
63+ /* MAX14001_REG_FLTEN MASKS */
64+ #define MAX14001_MASK_FLTEN_DYEN BIT(0)
65+ #define MAX14001_MASK_FLTEN_EADC BIT(1)
66+ #define MAX14001_MASK_FLTEN_EINRD BIT(2)
67+ #define MAX14001_MASK_FLTEN_ESPI BIT(3)
68+ #define MAX14001_MASK_FLTEN_ECOM BIT(4)
69+ #define MAX14001_MASK_FLTEN_ECRCL BIT(5)
70+ #define MAX14001_MASK_FLTEN_ECRCF BIT(6)
71+ #define MAX14001_MASK_FLTEN_EFET BIT(7)
72+ #define MAX14001_MASK_FLTEN_EMV BIT(8)
73+
74+ /* MAX14001_REG_WEN values*/
75+ #define MAX14001_REG_WEN_WRITE_ENABLE 0x294
76+ #define MAX14001_REG_WEN_WRITE_DISABLE 0x0
77+
78+ enum max14001_chips {
79+ max14001 ,
80+ max14002 ,
81+ };
82+
83+ struct max14001_state {
84+ struct spi_device * spi ;
85+ };
86+
87+ static int max14001_spi_read (struct max14001_state * st , u16 reg , u16 * val )
88+ {
89+ u16 tx = 0 ;
90+ u16 rx = 0 ;
91+ u16 reversed = 0 ;
92+ int ret = 0 ;
93+
94+ pr_err ("[Log Debug] max14001_spi_read: reg: %x, val: %x\n" , reg , * val );
95+
96+ tx |= FIELD_PREP (MAX14001_MASK_ADDR , reg );
97+ tx |= FIELD_PREP (MAX14001_MASK_WR , MAX14001_REG_READ );
98+ reversed = bitrev16 (tx );
99+
100+ ret = spi_write_then_read (st -> spi , & reversed , 2 , & rx , 2 );
101+ if (ret < 0 )
102+ return ret ;
103+
104+ reversed = bitrev16 (be16_to_cpu (rx ));
105+ * val = MAX14001_MASK_ADDR & reversed ;
106+
107+ return ret ;
108+ }
109+
110+ static int max14001_spi_write (struct max14001_state * st , u16 reg , u16 val )
111+ {
112+ u16 tx = 0 ;
113+ u16 msg = 0 ;
114+ u16 reversed = 0 ;
115+ int ret = 0 ;
116+
117+ pr_err ("[Log Debug] max14001_spi_write: reg: %x, val: %x\n" , reg , val );
118+
119+ struct spi_transfer xfer = {
120+ .tx_buf = NULL ,
121+ .len = 0 ,
122+ };
123+
124+ msg |= FIELD_PREP (MAX14001_MASK_ADDR , reg );
125+ msg |= FIELD_PREP (MAX14001_MASK_WR , MAX14001_REG_WRITE );
126+ msg |= FIELD_PREP (MAX14001_MASK_DATA , val );
127+
128+ reversed = bitrev16 (msg );
129+ put_unaligned_be16 (reversed , & tx );
130+
131+ xfer .tx_buf = & tx ;
132+ xfer .len = sizeof (tx );
133+
134+ pr_err ("[Log Debug] max14001_spi_write: msg: %x, tx: %x\n" , msg , tx );
135+
136+ ret = spi_sync_transfer (st -> spi , & xfer , 1 );
137+ if (ret < 0 )
138+ return ret ;
139+
140+ return ret ;
141+ }
142+
143+ static int max14001_read_raw (struct iio_dev * indio_dev ,
144+ struct iio_chan_spec const * chan ,
145+ int * val , int * val2 , long mask )
146+ {
147+ struct max14001_state * st = iio_priv (indio_dev );
148+
149+ switch (mask ) {
150+ case IIO_CHAN_INFO_RAW :
151+ pr_err ("[Log Debug] max14001_read_raw: IIO_CHAN_INFO_RAW\n" );
152+ return IIO_VAL_INT ;
153+ case IIO_CHAN_INFO_SCALE :
154+ pr_err ("[Log Debug] max14001_read_raw: IIO_CHAN_INFO_SCALE\n" );
155+ return IIO_VAL_INT ;
156+ }
157+
158+ return - EINVAL ;
159+ }
160+
161+ static int max14001_write_raw (struct iio_dev * indio_dev ,
162+ struct iio_chan_spec const * chan ,
163+ int val , int val2 , long mask )
164+ {
165+ struct max14001_state * st = iio_priv (indio_dev );
166+
167+ switch (mask ) {
168+ case IIO_CHAN_INFO_RAW :
169+ pr_err ("[Log Debug] max14001_write_raw: IIO_CHAN_INFO_RAW\n" );
170+ return 0 ;
171+ }
172+
173+ return - EINVAL ;
174+ }
175+
176+ static const struct iio_info max14001_info = {
177+ .read_raw = max14001_read_raw ,
178+ .write_raw = max14001_write_raw ,
179+ };
180+
181+ static const struct iio_chan_spec max14001_channel_voltage [] = {
182+ {
183+ .type = IIO_VOLTAGE ,
184+ .indexed = 1 ,
185+ .channel = 0 ,
186+ .output = 0 ,
187+ .info_mask_separate = BIT (IIO_CHAN_INFO_RAW ) |
188+ BIT (IIO_CHAN_INFO_SCALE ),
189+ }
190+ };
191+
192+ static const struct iio_chan_spec max14001_channel_current [] = {
193+ {
194+ .type = IIO_CURRENT ,
195+ .indexed = 1 ,
196+ .channel = 0 ,
197+ .output = 0 ,
198+ .info_mask_separate = BIT (IIO_CHAN_INFO_RAW ) |
199+ BIT (IIO_CHAN_INFO_SCALE ),
200+ }
201+ };
202+
203+ static int max14001_probe (struct spi_device * spi )
204+ {
205+ pr_err ("[Log Debug] max14001_probe\n" );
206+
207+ struct max14001_state * st ;
208+ struct iio_dev * indio_dev ;
209+ bool current_channel = false;
210+ int ret ;
211+
212+ indio_dev = devm_iio_device_alloc (& spi -> dev , sizeof (* st ));
213+ if (!indio_dev )
214+ return - ENOMEM ;
215+
216+ st = iio_priv (indio_dev );
217+ st -> spi = spi ;
218+
219+ indio_dev -> name = "max14001" ; //spi_get_device_id(spi)->name;
220+ indio_dev -> modes = INDIO_DIRECT_MODE ;
221+ indio_dev -> info = & max14001_info ;
222+
223+ for_each_available_child_of_node_scoped (spi -> dev .of_node , child ){
224+ current_channel = of_property_read_bool (child , "current-channel" );
225+ if (current_channel )
226+ break ;
227+ }
228+
229+ if (current_channel ){
230+ indio_dev -> channels = max14001_channel_current ;
231+ indio_dev -> num_channels = ARRAY_SIZE (max14001_channel_current );
232+ } else {
233+ indio_dev -> channels = max14001_channel_voltage ;
234+ indio_dev -> num_channels = ARRAY_SIZE (max14001_channel_voltage );
235+ }
236+
237+ //Enable register write
238+ max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_ENABLE );
239+ return devm_iio_device_register (& spi -> dev , indio_dev );
240+ }
241+
242+ static const struct spi_device_id max14001_id_table [] = {
243+ { "max14001" , max14001 },
244+ { "max14002" , max14002 },
245+ {}
246+ };
247+ MODULE_DEVICE_TABLE (spi , max14001_id_table );
248+
249+ static const struct of_device_id max14001_of_match [] = {
250+ { .compatible = "adi,max14001" },
251+ { .compatible = "adi,max14002" },
252+ {}
253+ };
254+ MODULE_DEVICE_TABLE (of , max14001_of_match );
255+
256+ static struct spi_driver max14001_driver = {
257+ .driver = {
258+ .name = "max14001" ,
259+ .of_match_table = max14001_of_match ,
260+ },
261+ .probe = max14001_probe ,
262+ .id_table = max14001_id_table ,
263+ };
264+ module_spi_driver (max14001_driver );
265+
266+ MODULE_AUTHOR (
"Marilene Andrade Garcia <[email protected] >" );
267+ MODULE_DESCRIPTION ("Analog Devices MAX14001/MAX14002 ADCs driver" );
268+ MODULE_LICENSE ("GPL v2" );
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