1414#include <linux/spi/spi.h>
1515#include <linux/iio/iio.h>
1616#include <linux/of.h>
17+ #include <linux/regulator/consumer.h>
1718
1819/* MAX14001 registers definition */
1920#define MAX14001_REG_ADC 0x00
7576#define MAX14001_REG_WEN_WRITE_ENABLE 0x294
7677#define MAX14001_REG_WEN_WRITE_DISABLE 0x0
7778
79+ /* MAX14001 10-bit ADC */
80+ #define MAX14001_NUMBER_OF_DATA_BITS 10
81+ #define MAX14001_BIT_DIV (1 << 10)
82+
7883enum max14001_chip_model {
7984 max14001 ,
8085 max14002 ,
@@ -97,9 +102,52 @@ static struct max14001_chip_info max14001_chip_info_tbl[] = {
97102struct max14001_state {
98103 struct spi_device * spi ;
99104 const struct max14001_chip_info * chip_info ;
105+ int vref_mV ;
100106};
101107
102- static int max14001_spi_read (struct max14001_state * st , u16 reg , u16 * val )
108+ static int max14001_get_scale (struct max14001_state * st )
109+ {
110+ int scale ;
111+
112+ /* scale = range / 2^10 */
113+ scale = st -> vref_mV / MAX14001_BIT_DIV ;
114+ return scale ;
115+ }
116+
117+ static int max14001_get_vref_mV (struct max14001_state * st )
118+ {
119+ struct device * dev = & st -> spi -> dev ;
120+ int ret = 0 ;
121+
122+ ret = devm_regulator_get_enable_read_voltage (dev , "vrefin" );
123+ if (ret < 0 ){
124+ st -> vref_mV = 1250000 / 1000 ;
125+ dev_info (& st -> spi -> dev , "%s: vrefin not found. vref_mV %d\n" , __func__ , st -> vref_mV );
126+ } else {
127+ st -> vref_mV = ret / 1000 ;
128+ dev_info (& st -> spi -> dev , "%s: vrefin found. vref_mV %d\n" , __func__ , st -> vref_mV );
129+ }
130+
131+ return ret ;
132+ }
133+
134+ static int max14001_init_required_regulators (struct max14001_state * st )
135+ {
136+ struct device * dev = & st -> spi -> dev ;
137+ int ret = 0 ;
138+
139+ ret = devm_regulator_get_enable (dev , "vdd" );
140+ if (ret )
141+ return dev_err_probe (dev , ret , "Failed to enable specified Vdd supply\n" );
142+
143+ ret = devm_regulator_get_enable (dev , "vddl" );
144+ if (ret )
145+ return dev_err_probe (dev , ret , "Failed to enable specified Vddl supply\n" );
146+
147+ return ret ;
148+ }
149+
150+ static int max14001_spi_read (struct max14001_state * st , u16 reg , int * val )
103151{
104152 u16 tx , rx , reversed ;
105153 int ret ;
@@ -116,7 +164,7 @@ static int max14001_spi_read(struct max14001_state *st, u16 reg, u16 *val)
116164
117165 /* TODO: Validate this line in the hw, could be le16_to_cpu */
118166 reversed = bitrev16 (be16_to_cpu (rx ));
119- * val = FIELD_GET (MAX14001_MASK_ADDR , reversed );
167+ * val = FIELD_GET (MAX14001_MASK_DATA , reversed );
120168
121169 return ret ;
122170}
@@ -154,17 +202,17 @@ static int max14001_spi_write_single_reg(struct max14001_state *st, u16 reg, u16
154202{
155203 int ret ;
156204
157- // Enable register write
205+ /* Enable register write */
158206 ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_ENABLE );
159207 if (ret < 0 )
160208 return ret ;
161209
162- // Write data into register
210+ /* Write data into register */
163211 ret = max14001_spi_write (st , reg , val );
164212 if (ret < 0 )
165213 return ret ;
166214
167- // Disable register write
215+ /* Disable register write */
168216 ret = max14001_spi_write (st , MAX14001_REG_WEN , MAX14001_REG_WEN_WRITE_DISABLE );
169217 if (ret < 0 )
170218 return ret ;
@@ -177,14 +225,30 @@ static int max14001_read_raw(struct iio_dev *indio_dev,
177225 int * val , int * val2 , long mask )
178226{
179227 struct max14001_state * st = iio_priv (indio_dev );
228+ int ret ;
180229
181230 switch (mask ) {
182231 case IIO_CHAN_INFO_RAW :
183- dev_info (& st -> spi -> dev , "%s: IIO_CHAN_INFO_RAW\n" , __func__ );
232+ ret = max14001_spi_read (st , MAX14001_REG_ADC , val );
233+ dev_info (& st -> spi -> dev , "%s: IIO_CHAN_INFO_RAW: channel: %d, val: %d\n" , __func__ , chan -> channel , val );
234+ if (ret < 0 )
235+ return ret ;
236+
184237 return IIO_VAL_INT ;
185- case IIO_CHAN_INFO_SCALE :
186- dev_info (& st -> spi -> dev , "%s: IIO_CHAN_INFO_SCALE\n" , __func__ );
238+ case IIO_CHAN_INFO_AVERAGE_RAW :
239+ ret = max14001_spi_read (st , MAX14001_REG_FADC , val );
240+ dev_info (& st -> spi -> dev , "%s: IIO_CHAN_INFO_AVERAGE_RAW: channel: %d, val: %d\n" , __func__ , chan -> channel , val );
241+ if (ret < 0 )
242+ return ret ;
243+
187244 return IIO_VAL_INT ;
245+ case IIO_CHAN_INFO_SCALE :
246+ ret = max14001_get_scale (st );
247+ * val = ret ;
248+ * val2 = MAX14001_NUMBER_OF_DATA_BITS ;
249+ dev_info (& st -> spi -> dev , "%s: IIO_CHAN_INFO_SCALE: val: %d, val2: %d\n" , __func__ , val , val2 );
250+
251+ return IIO_VAL_FRACTIONAL_LOG2 ;
188252 }
189253
190254 return - EINVAL ;
@@ -215,6 +279,7 @@ static const struct iio_chan_spec max14001_channel_voltage[] = {
215279 .indexed = 1 ,
216280 .channel = 0 ,
217281 .info_mask_separate = BIT (IIO_CHAN_INFO_RAW ) |
282+ BIT (IIO_CHAN_INFO_AVERAGE_RAW ) |
218283 BIT (IIO_CHAN_INFO_SCALE ),
219284 }
220285};
@@ -225,6 +290,7 @@ static const struct iio_chan_spec max14001_channel_current[] = {
225290 .indexed = 1 ,
226291 .channel = 0 ,
227292 .info_mask_separate = BIT (IIO_CHAN_INFO_RAW ) |
293+ BIT (IIO_CHAN_INFO_AVERAGE_RAW ) |
228294 BIT (IIO_CHAN_INFO_SCALE ),
229295 }
230296};
@@ -254,8 +320,6 @@ static int max14001_probe(struct spi_device *spi)
254320 indio_dev -> modes = INDIO_DIRECT_MODE ;
255321 indio_dev -> info = & max14001_info ;
256322
257- dev_info (& st -> spi -> dev , "%s: probe\n" , __func__ );
258-
259323 for_each_available_child_of_node_scoped (spi -> dev .of_node , child ) {
260324 current_channel = of_property_read_bool (child , "current-channel" );
261325 if (current_channel )
@@ -270,6 +334,11 @@ static int max14001_probe(struct spi_device *spi)
270334 indio_dev -> num_channels = ARRAY_SIZE (max14001_channel_voltage );
271335 }
272336
337+ dev_info (& st -> spi -> dev , "%s: probe\n" , __func__ );
338+
339+ max14001_init_required_regulators (st );
340+ max14001_get_vref_mV (st );
341+
273342 return devm_iio_device_register (& spi -> dev , indio_dev );
274343}
275344
0 commit comments